US20040113136A1 - Phase change memory and method therefor - Google Patents
Phase change memory and method therefor Download PDFInfo
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- US20040113136A1 US20040113136A1 US10/319,753 US31975302A US2004113136A1 US 20040113136 A1 US20040113136 A1 US 20040113136A1 US 31975302 A US31975302 A US 31975302A US 2004113136 A1 US2004113136 A1 US 2004113136A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
Definitions
- Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application.
- phase change materials i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state
- One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states.
- phase change materials suitable for such application include those utilizing various chalcogenide elements.
- the state of the phase change materials are also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reset as that value represents a phase or physical state of the material (e.g., crystalline or amorphous).
- a phase change memory cell may comprise a phase change material disposed on a dielectric material.
- some dielectric materials and phase change materials may not chemically bond well together.
- the layer of phase change material may peel during subsequent manufacturing of the phase change device, which in turn, may affect the yield or reliability of the device.
- phase change memory devices there is a continuing need for alternate ways to manufacture phase change memory devices.
- FIG. 1 is a cross-sectional view of a portion of a memory element during fabrication in accordance with an embodiment of the present invention
- FIG. 2 is a cross-sectional view of the structure of FIG. 1 at a later stage of fabrication in accordance with an embodiment of the present invention
- FIG. 3 is a cross-sectional view of the structure of FIG. 2 at a later stage of fabrication
- FIG. 4 is a cross-sectional view of the structure of FIG. 3 at a later stage of fabrication
- FIG. 5 is a cross-sectional view of the structure of FIG. 4 at a later stage of fabrication
- FIG. 6 is a cross-sectional view of the structure of FIG. 5 at a later stage of fabrication
- FIG. 7 is a cross-sectional view of the structure of FIG. 6 at a later stage of fabrication
- FIG. 8 is a top view of the structure of FIG. 7 at the stage of fabrication illustrated in FIG. 7;
- FIG. 9 is a cross-sectional view of the structure of FIG. 7 at a later stage of fabrication
- FIG. 10 is a cross-sectional view of the structure of FIG. 5 at a later stage of fabrication in accordance with another embodiment of the present invention.
- FIG. 11 is a cross-sectional view of the structure of FIG. 10 at a later stage of fabrication
- FIG. 12 is a cross-sectional view of the structure of FIG. 11 at a later stage of fabrication in accordance with another embodiment of the present invention.
- FIG. 13 is a block diagram illustrating a portion of a system in accordance with an embodiment of the present invention.
- Coupled may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
- FIGS. 1 - 9 may be used to illustrate one embodiment of the fabrication of a memory element 100 and FIGS. 10 and 11 may be used to illustrate another embodiment to manufacture memory element 100 .
- a substrate 110 such as, for example, a semiconductor substrate (e.g., a silicon substrate), although the scope of the present invention is not limited in this respect.
- Other suitable substrates may be, but are not limited to, substrates that contain ceramic material, organic material, or a glass material.
- a reducer material 120 of, in one embodiment, a refractory metal silicide such as, for example, a cobalt silicide (CoSi 2 ) may be formed over a portion of substrate 110 .
- Reducer material 120 may be formed on top of either a P+ or N+ doped junction that either could be part of a diode or a source/drain region of a MOS transistor.
- reducer material 120 may be formed over a P+ region 101 , which may be formed over a N region 102 . Regions 101 and 102 may form a PN diode.
- P+ region 101 may be formed by introducing a P-type dopant such as, for example, boron, in substrate 110 .
- a P-type dopant such as, for example, boron
- a suitable concentration of a P-type dopant is on the order of above about 5 ⁇ 10 18 to about 1 ⁇ 10 20 atoms per cubic centimeters (atoms/cm 3 ), which may be represented as P+.
- N region 102 may be a CMOS N-well on a P-substrate wafer, an N-well of a N-substrate wafer, or a buried N-well/word line (e.g., BWL in a diode matrix array).
- Reducer material 120 may serve as a relatively low resistance material in the fabrication of peripheral circuitry, e.g., addressing circuitry (not shown in FIG. 1). Reducer material 120 is not required in terms of forming a memory element as described, however, reducer material 120 may be included in memory element 100 between a phase change material (not shown in FIG. 1) and an isolation device or switching device such as, for example, a diode, or a transistor (not shown in FIG.1). Reducer material 120 may be formed by introducing a refractory metal (e.g., cobalt) into a portion of substrate 110 .
- a refractory metal e.g., cobalt
- Memory element 100 may also include shallow trench isolation (STI) structures 125 .
- STI structures 125 may serve to isolate individual memory elements from one another as well as associated circuit elements (e.g., transistor devices) formed in and on the substrate.
- STI structure 125 may be an oxide or silicon dioxide, although the scope of the present invention is not limited in this respect.
- a conductive plug 130 may be formed overlying reducer material 120 .
- Conductive plug 130 may serve as a relatively low resistance path to provide current to a programmable material, such as a phase change material (not shown in FIG. 1).
- Conductive plug 130 may include an outer U-shaped barrier material 135 and an inner conductive material 136 .
- barrier material 135 may be a conductive material.
- Barrier material 135 may be titanium nitride (TiN) or tantalum nitride (TaN).
- Conductive material 136 may be tungsten (W) or copper (Cu).
- a layer of insulating material 129 may be formed over substrate 110 .
- An opening (not shown in FIG. 1) may be formed in insulating material 129 , and conductive plug 130 may be formed in this opening, wherein insulating material 129 surrounds conductive plug 130 .
- Examples of insulating material 129 may include an oxide, nitride, or a low K dielectric material, although the scope of the present invention is not limited in this respect.
- a layer of insulating material 140 may be formed overlying insulating material 129 and a portion of conductive plug 130 .
- Insulating material 140 may be an electrically insulating material.
- Insulating material 140 may also be a thermally insulating material. Examples of insulating material 140 may include an oxide, nitride, or a low K dielectric material, although the scope of the present invention is not limited in this respect.
- Insulating material 140 may have a thickness ranging from about 500 angstroms ( ⁇ ) to about 3,000 angstroms, although the scope of the present invention is not limited in this respect.
- a hole or opening 150 having sidewalls 155 may be formed by etching insulating material 140 .
- Opening 150 may be a via or a trench, although the scope of the present invention is not limited in this respect.
- opening 150 may be formed using photolithographic and etch techniques.
- opening 150 may be formed by applying a layer of photoresist material (not shown) on insulating material 140 and exposing this photoresist material to light.
- a mask (not shown) may be used to expose selected areas of the photoresist material, which defines areas to be removed, i.e., etched.
- the etch may be a chemical etch, which may be referred to as a wet etch.
- the etch may be an electrolytic or plasma (ion bombardment) etch, which may be referred to as a dry etch.
- the etch may be an anisotropic etch using a dry plasma etch, although the scope oft the present invention is not limited in this respect. If opening 150 is formed using photolithographic techniques, the diameter or width of opening 150 may be at least one feature size.
- the feature size of a structure may refer to the minimum dimension achievable using photolithography.
- the feature size may refer to a width of a material or spacing of materials in a structure.
- photolithography refers to a process of transferring a pattern or image from one medium to another, e.g., as from a mask to a wafer, using ultra-violet (UV) light.
- UV ultra-violet
- the minimum feature size of the transferred pattern may be limited by the limitations of the UV light.
- Distances, sizes, or dimensions less than the feature size may be referred to as sub-lithographic distances, sizes, or dimensions.
- some structures may have feature sizes of about 2500 angstroms.
- a sub-lithographic distance may refer to a feature having a width of less than about 2500 angstroms.
- Electron beam lithography may refer to a direct-write lithography technique using a beam of electrons to expose resist on a wafer.
- X-ray lithography may refer to a lithographic process for transferring patterns to a silicon wafer in which the electromagnetic radiation used is X-ray, rather than visible radiation.
- the shorter wavelength for X-rays may reduce diffraction, and may be used to achieve feature sizes of about 1000 angstroms.
- sidewall spacers may be used to achieve sub-lithographic dimensions.
- FIG. 2 may be used to illustrate the use of sidewall spacers 160 to achieve sub-lithographic dimensions.
- FIG. 2 depicts the structure of FIG. 1, through the same cross-sectional view, after forming optional sidewall spacers 160 .
- sidewall spacers 160 may be formed along sidewalls 175 of a hard mask material 170 .
- the distance between sidewalls 175 may be one feature size and may be formed using photolithographic and etch techniques.
- Sidewall spacers 160 may be formed by depositing a layer of material in the space between sidewalls 175 and patterning this material using a dry etch such as, for example, an anisotropic etch.
- the distance between sidewall spacers 160 may be sub-lithographic.
- another anisotropic etch may be used to form an opening 150 having a sub-lithographic diameter.
- insulating material 140 may be anisotropically etched using an etching agent that is selective such that the etching agent stops at, or preserves, conductive plug 130 . As shown in FIG. 2, the etching operation exposes a portion of conductive plug 130 through opening 150 .
- sidewall spacers 160 may serve to reduce the quantity of electrode material ( 180 shown in FIG. 3) formed in opening 150 .
- the diameter of opening 150 may be less than about 1000 angstroms, although the scope of the present invention is not limited in this respect.
- hard mask material 170 may be polycrystalline silicon, amorphous silicon, or silicon nitride. Hard mask material 170 may have a thickness ranging from about 1,000 angstroms to about 3,000 angstroms, although the scope of the present invention is not limited in this respect. Sidewall spacers 160 may be formed from a variety of materials such as, for example, poly or amorphous silicon, silicon nitride oxide, or oxide nitride.
- opening 150 is not a limitation of the present invention.
- Other sub-lithographic methods may be used to form opening 150 , wherein opening 150 may have a sub-lithographic diameter.
- opening 150 may be formed using photolithographic techniques and may therefore, have a diameter of greater than or equal to about one feature size.
- FIG. 3 illustrates memory element 100 after the conformal deposition of an electrode material 180 over insulating material 140 and in opening 150 (FIG. 2).
- FIG. 3 has been simplified by illustrating memory element 100 without either sidewall spacers 160 or hard mask material 170 or subsequent to the removal of materials 160 and 170 .
- Spacers 160 or hard mask material 170 may be selectively removed using, for example, an etch or a chemical-mechanical polish (CMP).
- CMP chemical-mechanical polish
- some embodiments may use sidewall spacers 160 to form opening 150 (FIG. 2), and other embodiments may not use sidewall spacers to form opening 150 .
- electrode material 180 may be a layer of carbon or a semi-metal such as a transition metal, including but not limited to titanium, tungsten, titanium nitride (TiN), titanium aluminum nitride (TiAlN), or titanium silicon nitride (TiSiN).
- electrode material 180 may be formed with a chemical vapor deposition (CVD) process, however, the scope of the present invention is not limited by the particular process used to form electrode material 180 . It should also be understood that alternative processes may be used to form electrode material 180 .
- Suitable planarization techniques may include a chemical or chemical-mechanical polish (CMP) technique.
- CMP chemical or chemical-mechanical polish
- FIG. 4 illustrates the structure shown in FIG. 3 after removal of a portion of electrode material 180 .
- a portion of electrode material 180 may be removed by patterning or segmenting material 180 .
- a portion of material 180 may be removed using, for example, a CMP process.
- alternative processes may be used to remove a portion of electrode material 180 .
- a blanket etch may be used to remove portions of electrode material 180 .
- FIG. 5 illustrates memory element 100 after the removal of portions of insulating material 140 .
- insulating layer 140 may be recessed or etched back to expose a portion of the sidewalls of electrode material 180 .
- approximately 1000 to about 3000 angstroms of insulating layer 140 may be removed using a wet or selective etch back, e.g., a selective oxide etch diluted with hydrofluoric acid (HF). Alternatively, a dry etch may also be used.
- Electrode material 180 at this stage of processing may be referred to as a lance structure or a pillar structure and may serve as a lower electrode of memory element 100 .
- FIG. 6 illustrates the structure of FIG. 5 at a later stage of fabrication.
- FIG. 6 illustrates memory element 100 after the conformal forming of an insulating material 210 on a top surface of insulating material 140 , along the sidewalls of electrode material 180 , and on a top surface of electrode material 180 .
- insulating material 210 may be formed surrounding and contacting an upper portion of electrode material 180 .
- Insulating material 210 may be a electrically and/or thermally insulating material such as, for example, an oxide, a nitride, a low K dielectric material, any other relatively low thermally conductive material, or any other relatively low electrically conductive material. Insulating material 210 may be used to provide electrical and/or thermal isolation for memory element 100 . Using an insulating material to surround electrode 180 may increase the efficiency of memory element 100 during programming. Further, using an insulating material that has relatively high thermal insulating properties may increase heating efficiency (e.g., reduce heat loss) and may reduce the amount of electrical current used during programming of memory element 100 .
- insulating material 210 may have a thickness ranging from about 500 angstroms to about 2,500 angstroms, although the scope of the present invention is not limited in this respect. In one embodiment, insulating material 210 may be formed using a low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) process.
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- a layer of a material 220 may be formed overlying insulating layer 210 .
- Material 220 may be an electrically conductive or a thermally conductive material.
- Material 220 may serve as an adhesive material suitable for adhering to a phase change material (e.g., phase change material 300 in FIG. 9), and may be referred to as an adhesive material, adhesive layer, or a glue layer in such applications.
- a phase change material e.g., phase change material 300 in FIG. 9
- the type of material used may be selected depending on the phase chase material used in memory element 100 .
- Using a suitable adhesive material to bond with the phase change material may reduce any problems with peeling. In the absence of material 220 , the phase change material may directly contact insulating material 210 and may not bond sufficiently to insulating material 210 .
- Material 220 may also serve an as a thermal ground plane to reduce thermal disturb problems between adjacent memory elements.
- Thermal disturb problems may arise when a target or selected memory element is repeatedly heated during programming to place the phase change material of the memory element in, for example, an amorphous state. Due to scaling of memory devices where the distance between memory elements is reduced, during heating of the target memory element, unselected memory elements adjacent to the target memory element may also be heated. Over time, this inadvertent heating of the adjacent unselected memory elements may cause the unselected memory elements to change states erroneously.
- thermal disturb problems may be reduced by providing material 220 at an appropriate thickness to serve as a thermal ground plane. Increasing the thickness of material 220 may improve thermal dissipation, thereby improving the thermal isolation between adjacent memory elements.
- Examples of material 220 may include materials comprising polysilicon or titanium, although the scope of the claimed subject matter is not limited in this respect.
- the thickness and the technique used to formed material 220 may be selected depending on the desired characteristics of memory element 100 .
- material 220 may have a thickness ranging from about 200 angstroms to about 2,500 angstroms, although the scope of the present invention is not limited in this respect.
- material 220 may be formed using a physical vapor deposition (PVD), LPCVD, or a PECVD process.
- PVD physical vapor deposition
- LPCVD LPCVD
- PECVD PECVD
- FIG. 7 illustrates the structure of FIG. 6 after removal of portions of materials 180 , 210 , and 220 .
- a portion of the material 220 , a portion of the insulating material 210 , and a portion of electrode material 180 may form a substantially planar surface 250 .
- the structure shown in FIG. 6 may be subjected to a planarization process such as, for example, a CMP process, that removes portions of electrode material 180 , insulating material 210 , and material 220 .
- FIG. 7 portions of materials 180 , 210 , and 220 may be removed to expose a portion of electrode material 180 .
- FIG. 8 what is shown is a top view of memory element 100 at the stage of manufacture illustrated in FIG. 7.
- material 220 may surround an upper portion of electrode material 180 and may be separated from electrode material 180 by insulating material 210 .
- insulating material 210 may surround and contact an upper portion of the sidewalls of electrode material 180 .
- FIG. 9 illustrates the structure shown in FIG. 7 after forming a programmable material such as, for example, a phase change material 300 on planar surface 250 .
- phase change material 300 may overlie and contact a portion of material 220 , a portion of insulating material 210 , and a portion of electrode material 180 .
- phase change material 300 may include, but are not limited to, chalcogenide element(s) compositions of the class of tellurium-germanium-antimony (TexGeySbz) material or GeSbTe alloys, although the scope of the present invention is not limited to just these.
- another phase change material may be used whose electrical properties (e.g. resistance) may be changed through the application of energy such as, for example, light, heat, or electrical current.
- phase change material 300 may have a thickness ranging from about 150 angstroms to about 1,500 angstroms, although the scope of the present invention is not limited in this respect.
- phase change material 300 may be formed using a PVD process.
- a barrier material 310 may be formed overlying phase change material 300 and a conductive material 320 may be formed overlying barrier material 310 .
- Barrier material 310 may serve, in one aspect, to prevent any chemical reaction between phase change material 300 and conductive material 320 .
- barrier material 310 may be titanium, titanium nitride, or carbon
- conductive material 320 may comprise, for example, aluminum.
- Barrier material 310 is an optional layer.
- conductive material 320 may be formed overlying phase change material 300 .
- Conductive material 320 may serve as an address line to address and program phase change material 300 of memory element 100 .
- Conductive material 320 may be referred to as a bitline or column line.
- Reducer material 120 may also serve as an address line to program phase change material 300 and may be referred to as a wordline or row line.
- electrode material 180 may be coupled to an access device such as, for example, a diode or transistor, via reducer material 120 .
- the access device may also be referred to as an isolation device, a select device, or a switching device.
- phase change material 300 may be accomplished by applying voltage potentials to conductive material 320 and reducer material 120 .
- a voltage potential applied to reducer material 120 may be transferred to electrode material 180 via conductive plug 130 .
- a voltage potential difference of about five volts may be applied across the phase change material 300 and a bottom portion of electrode 180 by applying about five volts to conductive material 320 and about zero volts to the bottom portion of electrode material 180 .
- a current may flow through phase change material 300 and electrode 180 in response to the applied voltage potentials, and may result in heating of phase change material 300 . This heating and subsequent cooling may alter the memory state or phase of phase change material 300 .
- insulating materials 140 and 210 may provide electrical and thermal isolation and material 220 may serve as a thermal ground plane as discussed above.
- Memory element 100 shown in FIG. 9 may be referred to as a vertical phase change memory structure since current may flow vertically through phase change material 300 between upper and lower electrodes. It should be noted that memory element 100 may also be referred to as a memory cell and may be used in a phase change memory array having a plurality of memory elements 100 for storing information.
- memory element 100 may be arranged differently and include additional layers and structures. For example, it may be desirable to form isolation structures, peripheral circuitry (e.g., addressing circuitry), etc. It should be understood that the absence of these elements is not a limitation of the scope of the present invention.
- the embodiment of memory element 100 illustrated in FIG. 9 provides a self-aligned adhesive layer offset from a raised bottom electrode by an insulating spacer.
- FIG. 10 illustrates the structure of FIG. 5 at a later stage of fabrication in accordance with another embodiment for manufacturing memory element 100 .
- insulating material 210 may be patterned using, for example, etching techniques, to form spacers 210 A along the sidewalls of electrode material 180 .
- material 220 may be formed overlying insulating material 140 , spacers 210 A, and the top surface of electrode material 180 .
- FIG. 11 illustrates the structure of FIG. 10 after the removal of portions of materials 180 , 210 A, and 220 .
- a portion of the material 220 , a portion of spacers 210 A, and a portion of electrode material 180 may form a planar surface 250 .
- the structure shown in FIG. 10 may be subjected to a planarization process such as, for example, a CMP process, that removes portions of electrode material 180 , spacers 210 A, and material 220 .
- an etching process may be used to form planar surface 250 .
- a phase change material may be disposed on planer surface 250 .
- FIG. 12 illustrates the structure shown in FIG. 11 after forming a programmable material such as, for example, a phase change material 300 on planar surface 250 .
- phase change material 300 may overlie and contact a portion of material 220 , a portion of spacers 210 A, and a portion of electrode material 180 .
- a barrier material 310 may be formed overlying phase change material 300 and a conductive material 320 may be formed overlying barrier material 310 .
- System 500 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly.
- PDA personal digital assistant
- System 500 may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a cellular network, although the scope of the present invention is not limited in this respect.
- WLAN wireless local area network
- WPAN wireless personal area network
- cellular network although the scope of the present invention is not limited in this respect.
- System 500 may include a controller 510 , an input/output (I/O) device 520 (e.g. a keypad, display), a memory 530 , and a wireless interface 540 coupled to each other via a bus 550 . It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.
- I/O input/output
- Controller 510 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like.
- Memory 530 may be used to store messages transmitted to or by system 500 .
- Memory 530 may also optionally be used to store instructions that are executed by controller 510 during the operation of system 500 , and may be used to store user data.
- Memory 530 may be provided by one or more different types of memory.
- memory 530 may comprise a volatile memory (any type of random access memory), a non-volatile memory such as a flash memory and/or a phase change memory that includes a memory element such as, for example, memory element 100 illustrated in FIG. 9 or 12 .
- I/O device 520 may be used by a user to generate a message.
- System 500 may use wireless interface 540 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal.
- RF radio frequency
- Examples of wireless interface 540 may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.
- system 500 may use one of the following communication air interface protocols to transmit and receive messages: Code Division Multiple Access (CDMA), cellular radiotelephone communication systems, Global System for Mobile Communications (GSM) cellular radiotelephone systems, North American Digital Cellular (NADC) cellular radiotelephone systems, Time Division Multiple Access (TDMA) systems, Extended-TDMA (E-TDMA) cellular radiotelephone systems, third generation (3G) systems like Wide-band CDMA (WCDMA), CDMA-2000, or the like.
- CDMA Code Division Multiple Access
- GSM Global System for Mobile Communications
- NADC North American Digital Cellular
- TDMA Time Division Multiple Access
- E-TDMA Extended-TDMA
- 3G third generation
- WCDMA Wide-band CDMA
- CDMA-2000 Code Division Multiple Access-2000
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Abstract
Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include an electrode, an adhesive material, an insulating material between the electrode and the adhesive material, wherein a portion of the adhesive material, a portion of the insulating material, and a portion of the electrode form a substantially planar surface. The phase change memory may further include a phase change material on the substantially planar surface and contacting the electrode, the adhesive material, and the insulating material.
Description
- Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states.
- Typical materials suitable for such application include those utilizing various chalcogenide elements. The state of the phase change materials are also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reset as that value represents a phase or physical state of the material (e.g., crystalline or amorphous).
- A phase change memory cell may comprise a phase change material disposed on a dielectric material. However, some dielectric materials and phase change materials may not chemically bond well together. As a result, the layer of phase change material may peel during subsequent manufacturing of the phase change device, which in turn, may affect the yield or reliability of the device.
- Thus, there is a continuing need for alternate ways to manufacture phase change memory devices.
- The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The present invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
- FIG. 1 is a cross-sectional view of a portion of a memory element during fabrication in accordance with an embodiment of the present invention;
- FIG. 2 is a cross-sectional view of the structure of FIG. 1 at a later stage of fabrication in accordance with an embodiment of the present invention;
- FIG. 3 is a cross-sectional view of the structure of FIG. 2 at a later stage of fabrication;
- FIG. 4 is a cross-sectional view of the structure of FIG. 3 at a later stage of fabrication;
- FIG. 5 is a cross-sectional view of the structure of FIG. 4 at a later stage of fabrication;
- FIG. 6 is a cross-sectional view of the structure of FIG. 5 at a later stage of fabrication; FIG. 7 is a cross-sectional view of the structure of FIG. 6 at a later stage of fabrication;
- FIG. 8 is a top view of the structure of FIG. 7 at the stage of fabrication illustrated in FIG. 7;
- FIG. 9 is a cross-sectional view of the structure of FIG. 7 at a later stage of fabrication;
- FIG. 10 is a cross-sectional view of the structure of FIG. 5 at a later stage of fabrication in accordance with another embodiment of the present invention;
- FIG. 11 is a cross-sectional view of the structure of FIG. 10 at a later stage of fabrication;
- FIG. 12 is a cross-sectional view of the structure of FIG. 11 at a later stage of fabrication in accordance with another embodiment of the present invention; and
- FIG. 13 is a block diagram illustrating a portion of a system in accordance with an embodiment of the present invention.
- It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.
- In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
- In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
- FIGS.1-9 may be used to illustrate one embodiment of the fabrication of a
memory element 100 and FIGS. 10 and 11 may be used to illustrate another embodiment to manufacturememory element 100. What is shown in FIG. 1 is asubstrate 110 such as, for example, a semiconductor substrate (e.g., a silicon substrate), although the scope of the present invention is not limited in this respect. Other suitable substrates may be, but are not limited to, substrates that contain ceramic material, organic material, or a glass material. - A
reducer material 120 of, in one embodiment, a refractory metal silicide such as, for example, a cobalt silicide (CoSi2) may be formed over a portion ofsubstrate 110.Reducer material 120 may be formed on top of either a P+ or N+ doped junction that either could be part of a diode or a source/drain region of a MOS transistor. - In the embodiment illustrated in FIG. 1,
reducer material 120 may be formed over aP+ region 101, which may be formed over aN region 102.Regions -
P+ region 101 may be formed by introducing a P-type dopant such as, for example, boron, insubstrate 110. In one example, a suitable concentration of a P-type dopant is on the order of above about 5×1018 to about 1×1020 atoms per cubic centimeters (atoms/cm3), which may be represented as P+.N region 102 may be a CMOS N-well on a P-substrate wafer, an N-well of a N-substrate wafer, or a buried N-well/word line (e.g., BWL in a diode matrix array). -
Reducer material 120, in one aspect, may serve as a relatively low resistance material in the fabrication of peripheral circuitry, e.g., addressing circuitry (not shown in FIG. 1).Reducer material 120 is not required in terms of forming a memory element as described, however,reducer material 120 may be included inmemory element 100 between a phase change material (not shown in FIG. 1) and an isolation device or switching device such as, for example, a diode, or a transistor (not shown in FIG.1).Reducer material 120 may be formed by introducing a refractory metal (e.g., cobalt) into a portion ofsubstrate 110. -
Memory element 100 may also include shallow trench isolation (STI)structures 125.STI structures 125 may serve to isolate individual memory elements from one another as well as associated circuit elements (e.g., transistor devices) formed in and on the substrate. In one embodiment,STI structure 125 may be an oxide or silicon dioxide, although the scope of the present invention is not limited in this respect. - A
conductive plug 130 may be formedoverlying reducer material 120.Conductive plug 130 may serve as a relatively low resistance path to provide current to a programmable material, such as a phase change material (not shown in FIG. 1).Conductive plug 130 may include an outerU-shaped barrier material 135 and an innerconductive material 136. Although the scope of the present invention is not limited in this respect,barrier material 135 may be a conductive material.Barrier material 135 may be titanium nitride (TiN) or tantalum nitride (TaN).Conductive material 136 may be tungsten (W) or copper (Cu). - A layer of insulating
material 129 may be formed oversubstrate 110. An opening (not shown in FIG. 1) may be formed in insulatingmaterial 129, andconductive plug 130 may be formed in this opening, wherein insulatingmaterial 129 surroundsconductive plug 130. Examples of insulatingmaterial 129 may include an oxide, nitride, or a low K dielectric material, although the scope of the present invention is not limited in this respect. - A layer of insulating
material 140 may be formed overlying insulatingmaterial 129 and a portion ofconductive plug 130. Insulatingmaterial 140 may be an electrically insulating material. Insulatingmaterial 140 may also be a thermally insulating material. Examples ofinsulating material 140 may include an oxide, nitride, or a low K dielectric material, although the scope of the present invention is not limited in this respect. Insulatingmaterial 140 may have a thickness ranging from about 500 angstroms (Å) to about 3,000 angstroms, although the scope of the present invention is not limited in this respect. - Turning to FIG. 2, a hole or
opening 150 having sidewalls 155 may be formed by etching insulatingmaterial 140. Opening 150 may be a via or a trench, although the scope of the present invention is not limited in this respect. - In one embodiment, opening150 may be formed using photolithographic and etch techniques. As an example, opening 150 may be formed by applying a layer of photoresist material (not shown) on insulating
material 140 and exposing this photoresist material to light. A mask (not shown) may be used to expose selected areas of the photoresist material, which defines areas to be removed, i.e., etched. The etch may be a chemical etch, which may be referred to as a wet etch. Or, the etch may be an electrolytic or plasma (ion bombardment) etch, which may be referred to as a dry etch. In one embodiment, the etch may be an anisotropic etch using a dry plasma etch, although the scope oft the present invention is not limited in this respect. If opening 150 is formed using photolithographic techniques, the diameter or width ofopening 150 may be at least one feature size. - The feature size of a structure may refer to the minimum dimension achievable using photolithography. For example, the feature size may refer to a width of a material or spacing of materials in a structure. As is understood, photolithography refers to a process of transferring a pattern or image from one medium to another, e.g., as from a mask to a wafer, using ultra-violet (UV) light. The minimum feature size of the transferred pattern may be limited by the limitations of the UV light. Distances, sizes, or dimensions less than the feature size may be referred to as sub-lithographic distances, sizes, or dimensions. For example, some structures may have feature sizes of about 2500 angstroms. In this example, a sub-lithographic distance may refer to a feature having a width of less than about 2500 angstroms.
- Several techniques may be used to achieve sub-lithographic dimensions. Although the scope of the present invention is not limited in this respect, phase shift mask, electron beam lithography, or x-ray lithography may be used to achieve sub-lithographic dimensions. Electron beam lithography may refer to a direct-write lithography technique using a beam of electrons to expose resist on a wafer. X-ray lithography may refer to a lithographic process for transferring patterns to a silicon wafer in which the electromagnetic radiation used is X-ray, rather than visible radiation. The shorter wavelength for X-rays (e.g., about 10-50 angstroms, versus about 2000-3000 angstroms for ultra-violet radiation) may reduce diffraction, and may be used to achieve feature sizes of about 1000 angstroms. Also, sidewall spacers may be used to achieve sub-lithographic dimensions. FIG. 2 may be used to illustrate the use of
sidewall spacers 160 to achieve sub-lithographic dimensions. - FIG. 2 depicts the structure of FIG. 1, through the same cross-sectional view, after forming
optional sidewall spacers 160. In one embodiment,sidewall spacers 160 may be formed along sidewalls 175 of ahard mask material 170. The distance betweensidewalls 175 may be one feature size and may be formed using photolithographic and etch techniques.Sidewall spacers 160 may be formed by depositing a layer of material in the space betweensidewalls 175 and patterning this material using a dry etch such as, for example, an anisotropic etch. - The distance between
sidewall spacers 160 may be sub-lithographic. Aftersidewall spacers 160 are formed, in one embodiment, another anisotropic etch may be used to form anopening 150 having a sub-lithographic diameter. For example, in one embodiment, insulatingmaterial 140 may be anisotropically etched using an etching agent that is selective such that the etching agent stops at, or preserves,conductive plug 130. As shown in FIG. 2, the etching operation exposes a portion ofconductive plug 130 throughopening 150. In one aspect,sidewall spacers 160 may serve to reduce the quantity of electrode material (180 shown in FIG. 3) formed inopening 150. In one embodiment, the diameter ofopening 150 may be less than about 1000 angstroms, although the scope of the present invention is not limited in this respect. - Although the scope of the present invention is not limited in this respect,
hard mask material 170 may be polycrystalline silicon, amorphous silicon, or silicon nitride.Hard mask material 170 may have a thickness ranging from about 1,000 angstroms to about 3,000 angstroms, although the scope of the present invention is not limited in this respect.Sidewall spacers 160 may be formed from a variety of materials such as, for example, poly or amorphous silicon, silicon nitride oxide, or oxide nitride. - It should be pointed out that the use of
sidewall spacers 160 to form opening 150 is not a limitation of the present invention. Other sub-lithographic methods, as mentioned above, may be used to form opening 150, wherein opening 150 may have a sub-lithographic diameter. Or, in alternate embodiments, opening 150 may be formed using photolithographic techniques and may therefore, have a diameter of greater than or equal to about one feature size. - FIG. 3 illustrates
memory element 100 after the conformal deposition of anelectrode material 180 over insulatingmaterial 140 and in opening 150 (FIG. 2). FIG. 3 has been simplified by illustratingmemory element 100 without eithersidewall spacers 160 orhard mask material 170 or subsequent to the removal ofmaterials Spacers 160 orhard mask material 170 may be selectively removed using, for example, an etch or a chemical-mechanical polish (CMP). As discussed above, some embodiments may usesidewall spacers 160 to form opening 150 (FIG. 2), and other embodiments may not use sidewall spacers to form opening 150. - In one embodiment,
electrode material 180 may be a layer of carbon or a semi-metal such as a transition metal, including but not limited to titanium, tungsten, titanium nitride (TiN), titanium aluminum nitride (TiAlN), or titanium silicon nitride (TiSiN). As an example,electrode material 180 may be formed with a chemical vapor deposition (CVD) process, however, the scope of the present invention is not limited by the particular process used to formelectrode material 180. It should also be understood that alternative processes may be used to formelectrode material 180. - Following introduction of
electrode material 180, the structure shown in FIG. 3 may be subjected to a planarization that removes a portion ofelectrode material 180 and possibly a portion of insulatinglayer 140. Suitable planarization techniques may include a chemical or chemical-mechanical polish (CMP) technique. - FIG. 4 illustrates the structure shown in FIG. 3 after removal of a portion of
electrode material 180. A portion ofelectrode material 180 may be removed by patterning or segmentingmaterial 180. In one embodiment, a portion ofmaterial 180 may be removed using, for example, a CMP process. It should also be understood that alternative processes may be used to remove a portion ofelectrode material 180. For example, a blanket etch may be used to remove portions ofelectrode material 180. - FIG. 5 illustrates
memory element 100 after the removal of portions of insulatingmaterial 140. In one embodiment, insulatinglayer 140 may be recessed or etched back to expose a portion of the sidewalls ofelectrode material 180. In one embodiment, approximately 1000 to about 3000 angstroms of insulatinglayer 140 may be removed using a wet or selective etch back, e.g., a selective oxide etch diluted with hydrofluoric acid (HF). Alternatively, a dry etch may also be used.Electrode material 180 at this stage of processing may be referred to as a lance structure or a pillar structure and may serve as a lower electrode ofmemory element 100. - FIG. 6 illustrates the structure of FIG. 5 at a later stage of fabrication. FIG. 6 illustrates
memory element 100 after the conformal forming of an insulatingmaterial 210 on a top surface of insulatingmaterial 140, along the sidewalls ofelectrode material 180, and on a top surface ofelectrode material 180. In other words, insulatingmaterial 210 may be formed surrounding and contacting an upper portion ofelectrode material 180. - Insulating
material 210 may be a electrically and/or thermally insulating material such as, for example, an oxide, a nitride, a low K dielectric material, any other relatively low thermally conductive material, or any other relatively low electrically conductive material. Insulatingmaterial 210 may be used to provide electrical and/or thermal isolation formemory element 100. Using an insulating material to surroundelectrode 180 may increase the efficiency ofmemory element 100 during programming. Further, using an insulating material that has relatively high thermal insulating properties may increase heating efficiency (e.g., reduce heat loss) and may reduce the amount of electrical current used during programming ofmemory element 100. - The thickness and the technique used to formed insulating
layer 210 may be selected depending on the desired characteristics ofmemory element 100. In one embodiment, insulatingmaterial 210 may have a thickness ranging from about 500 angstroms to about 2,500 angstroms, although the scope of the present invention is not limited in this respect. In one embodiment, insulatingmaterial 210 may be formed using a low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) process. - A layer of a
material 220 may be formed overlying insulatinglayer 210.Material 220 may be an electrically conductive or a thermally conductive material.Material 220 may serve as an adhesive material suitable for adhering to a phase change material (e.g.,phase change material 300 in FIG. 9), and may be referred to as an adhesive material, adhesive layer, or a glue layer in such applications. In this example wherematerial 220 serves as an adhesive layer, the type of material used may be selected depending on the phase chase material used inmemory element 100. Using a suitable adhesive material to bond with the phase change material may reduce any problems with peeling. In the absence ofmaterial 220, the phase change material may directly contact insulatingmaterial 210 and may not bond sufficiently to insulatingmaterial 210. -
Material 220 may also serve an as a thermal ground plane to reduce thermal disturb problems between adjacent memory elements. Thermal disturb problems may arise when a target or selected memory element is repeatedly heated during programming to place the phase change material of the memory element in, for example, an amorphous state. Due to scaling of memory devices where the distance between memory elements is reduced, during heating of the target memory element, unselected memory elements adjacent to the target memory element may also be heated. Over time, this inadvertent heating of the adjacent unselected memory elements may cause the unselected memory elements to change states erroneously. As stated above, thermal disturb problems may be reduced by providingmaterial 220 at an appropriate thickness to serve as a thermal ground plane. Increasing the thickness ofmaterial 220 may improve thermal dissipation, thereby improving the thermal isolation between adjacent memory elements. - Examples of
material 220 may include materials comprising polysilicon or titanium, although the scope of the claimed subject matter is not limited in this respect. The thickness and the technique used to formedmaterial 220 may be selected depending on the desired characteristics ofmemory element 100. In one embodiment,material 220 may have a thickness ranging from about 200 angstroms to about 2,500 angstroms, although the scope of the present invention is not limited in this respect. In one embodiment,material 220 may be formed using a physical vapor deposition (PVD), LPCVD, or a PECVD process. - FIG. 7 illustrates the structure of FIG. 6 after removal of portions of
materials material 220, a portion of the insulatingmaterial 210, and a portion ofelectrode material 180 may form a substantiallyplanar surface 250. In one embodiment, the structure shown in FIG. 6 may be subjected to a planarization process such as, for example, a CMP process, that removes portions ofelectrode material 180, insulatingmaterial 210, andmaterial 220. - As is seen in FIG. 7, portions of
materials electrode material 180. Turning briefly to FIG. 8, what is shown is a top view ofmemory element 100 at the stage of manufacture illustrated in FIG. 7. In the embodiment illustrated in FIGS. 7 and 8,material 220 may surround an upper portion ofelectrode material 180 and may be separated fromelectrode material 180 by insulatingmaterial 210. In addition, insulatingmaterial 210 may surround and contact an upper portion of the sidewalls ofelectrode material 180. - FIG. 9 illustrates the structure shown in FIG. 7 after forming a programmable material such as, for example, a
phase change material 300 onplanar surface 250. As is illustrated in FIG. 9,phase change material 300 may overlie and contact a portion ofmaterial 220, a portion of insulatingmaterial 210, and a portion ofelectrode material 180. - Examples of
phase change material 300 may include, but are not limited to, chalcogenide element(s) compositions of the class of tellurium-germanium-antimony (TexGeySbz) material or GeSbTe alloys, although the scope of the present invention is not limited to just these. Alternatively, another phase change material may be used whose electrical properties (e.g. resistance) may be changed through the application of energy such as, for example, light, heat, or electrical current. In one embodiment,phase change material 300 may have a thickness ranging from about 150 angstroms to about 1,500 angstroms, although the scope of the present invention is not limited in this respect. In one embodiment,phase change material 300 may be formed using a PVD process. - After forming
phase change material 300, abarrier material 310 may be formed overlyingphase change material 300 and aconductive material 320 may be formedoverlying barrier material 310.Barrier material 310 may serve, in one aspect, to prevent any chemical reaction betweenphase change material 300 andconductive material 320. Although the scope of the present invention is not limited in this respect,barrier material 310 may be titanium, titanium nitride, or carbon, andconductive material 320 may comprise, for example, aluminum.Barrier material 310 is an optional layer. In alternate embodiments,conductive material 320 may be formed overlyingphase change material 300. -
Conductive material 320 may serve as an address line to address and programphase change material 300 ofmemory element 100.Conductive material 320 may be referred to as a bitline or column line.Reducer material 120 may also serve as an address line to programphase change material 300 and may be referred to as a wordline or row line. Although not shown,electrode material 180 may be coupled to an access device such as, for example, a diode or transistor, viareducer material 120. The access device may also be referred to as an isolation device, a select device, or a switching device. - Programming of
phase change material 300 to alter the state or phase of the material may be accomplished by applying voltage potentials toconductive material 320 andreducer material 120. A voltage potential applied toreducer material 120 may be transferred toelectrode material 180 viaconductive plug 130. For example, a voltage potential difference of about five volts may be applied across thephase change material 300 and a bottom portion ofelectrode 180 by applying about five volts toconductive material 320 and about zero volts to the bottom portion ofelectrode material 180. A current may flow throughphase change material 300 andelectrode 180 in response to the applied voltage potentials, and may result in heating ofphase change material 300. This heating and subsequent cooling may alter the memory state or phase ofphase change material 300. - During programming, insulating
materials material 220 may serve as a thermal ground plane as discussed above. -
Memory element 100 shown in FIG. 9 may be referred to as a vertical phase change memory structure since current may flow vertically throughphase change material 300 between upper and lower electrodes. It should be noted thatmemory element 100 may also be referred to as a memory cell and may be used in a phase change memory array having a plurality ofmemory elements 100 for storing information. - In other embodiments,
memory element 100 may be arranged differently and include additional layers and structures. For example, it may be desirable to form isolation structures, peripheral circuitry (e.g., addressing circuitry), etc. It should be understood that the absence of these elements is not a limitation of the scope of the present invention. - The embodiment of
memory element 100 illustrated in FIG. 9 provides a self-aligned adhesive layer offset from a raised bottom electrode by an insulating spacer. - FIG. 10 illustrates the structure of FIG. 5 at a later stage of fabrication in accordance with another embodiment for
manufacturing memory element 100. In this embodiment, insulatingmaterial 210 may be patterned using, for example, etching techniques, to formspacers 210A along the sidewalls ofelectrode material 180. After formingspacers 210A,material 220 may be formed overlying insulatingmaterial 140, spacers 210A, and the top surface ofelectrode material 180. - FIG. 11 illustrates the structure of FIG. 10 after the removal of portions of
materials material 220, a portion ofspacers 210A, and a portion ofelectrode material 180 may form aplanar surface 250. In one embodiment, the structure shown in FIG. 10 may be subjected to a planarization process such as, for example, a CMP process, that removes portions ofelectrode material 180, spacers 210A, andmaterial 220. In another embodiment, an etching process may be used to formplanar surface 250. After formingplanar surface 250, a phase change material may be disposed onplaner surface 250. - FIG. 12 illustrates the structure shown in FIG. 11 after forming a programmable material such as, for example, a
phase change material 300 onplanar surface 250. As is illustrated in FIG. 12,phase change material 300 may overlie and contact a portion ofmaterial 220, a portion ofspacers 210A, and a portion ofelectrode material 180. After formingphase change material 300, abarrier material 310 may be formed overlyingphase change material 300 and aconductive material 320 may be formedoverlying barrier material 310. - Turning to FIG. 13, a portion of a
system 500 in accordance with an embodiment of the present invention is described.System 500 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly.System 500 may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a cellular network, although the scope of the present invention is not limited in this respect. -
System 500 may include acontroller 510, an input/output (I/O) device 520 (e.g. a keypad, display), amemory 530, and awireless interface 540 coupled to each other via abus 550. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components. -
Controller 510 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like.Memory 530 may be used to store messages transmitted to or bysystem 500.Memory 530 may also optionally be used to store instructions that are executed bycontroller 510 during the operation ofsystem 500, and may be used to store user data.Memory 530 may be provided by one or more different types of memory. For example,memory 530 may comprise a volatile memory (any type of random access memory), a non-volatile memory such as a flash memory and/or a phase change memory that includes a memory element such as, for example,memory element 100 illustrated in FIG. 9 or 12. - I/
O device 520 may be used by a user to generate a message.System 500 may usewireless interface 540 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples ofwireless interface 540 may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect. - Although the scope of the present invention is not limited in this respect,
system 500 may use one of the following communication air interface protocols to transmit and receive messages: Code Division Multiple Access (CDMA), cellular radiotelephone communication systems, Global System for Mobile Communications (GSM) cellular radiotelephone systems, North American Digital Cellular (NADC) cellular radiotelephone systems, Time Division Multiple Access (TDMA) systems, Extended-TDMA (E-TDMA) cellular radiotelephone systems, third generation (3G) systems like Wide-band CDMA (WCDMA), CDMA-2000, or the like. - While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Claims (26)
1. An apparatus, comprising:
an electrode;
an adhesive material;
a dielectric material between the electrode and the adhesive material, wherein a portion of the adhesive material, a portion of the dielectric material, and a portion of the electrode form a substantially planar surface; and
a phase change material on the substantially planar surface and contacting the electrode, the adhesive material, and the dielectric material.
2. The apparatus of claim 1 , wherein the dielectric material contacts a portion of a sidewall of the electrode.
3. The apparatus of claim 2 , wherein the adhesive material surrounds a portion of the electrode and is separated from the electrode by the dielectric material.
4. The apparatus of claim 1 ,
wherein the adhesive material comprises polysilicon or titanium;
wherein the electrode comprises titanium, tungsten, titanium nitride (TiN), titanium aluminum nitride (TiAIN), or titanium silicon nitride (TiSiN); and
wherein the dielectric material comprises an oxide, a nitride, or a low k dielectric material.
5. The apparatus of claim 1 , wherein the phase change material comprises a chalcogenide material.
6. The apparatus of claim 1 , wherein the electrode is coupled to an address line.
7. The apparatus of claim 1 , further comprising a conductive material over the phase change material.
8. The apparatus of claim 7 , wherein the conductive material comprises aluminum.
9. An apparatus, comprising:
an electrode material;
a conductive material;
an insulating material between the electrode material and the conductive material, wherein a portion of the conductive material, a portion of the insulating material, and a portion of the electrode material form a substantially planar surface; and
a programmable material on the substantially planar surface and contacting the electrode material, the conductive material, and the insulating material.
10. The apparatus of claim 9 , wherein the conductive material comprises polysilicon or titanium.
11. The apparatus of claim 9 , wherein the programmable material is a phase change material.
12. The apparatus of claim 9 , wherein the conductive material serves as a thermal ground plane.
13. The apparatus of claim 9 , wherein the insulating material surrounds and contacts an upper portion of the electrode material.
14. The apparatus of claim 9 , wherein the insulating material contacts a portion of a sidewall of the electrode material.
15. The apparatus of claim 9 , wherein the conductive material surrounds an upper portion of the electrode material and is separated from the electrode material by the insulating material.
16. A method, comprising:
forming an adhesive material surrounding a portion of an electrode;
removing a portion of the adhesive material and a portion of the electrode to expose a portion of the electrode; and
forming a phase change material overlying the adhesive material and the electrode.
17. The method of claim 16 , further comprising forming an insulating material between the adhesive material and the electrode and wherein forming a phase change material includes forming the phase change material overlying the insulating material.
18. The method of claim 17 , wherein removing further comprising removing a portion of the insulating material.
19. The method of claim 18 , wherein removing includes using a chemical-mechanical polish (CMP) to remove portions of the adhesive material, the insulating material and the electrode.
20. The method of claim 18 , further comprising etching the insulating material to form a spacer prior to removing a portion of the insulating material.
21. The method of claim 17 , wherein removing includes removing portions of the adhesive material, the electrode, and the insulating material to form a substantially planar surface and wherein forming a phase change material includes forming the phase change material on the substantially planar surface.
22. The method of claim 17 , further comprising:
forming an opening in a dielectric material;
forming the electrode in the opening; and
removing a portion of the dielectric material so that a top surface of the electrode is above a top surface of the dielectric material.
23. The method of claim 17 , wherein forming the insulating material further includes forming the insulating material over a top surface of the electrode and on a portion of a sidewall of the electrode and wherein forming an adhesive material includes forming the adhesive material overlying the insulating material, wherein the adhesive material is separated from the electrode by the insulating material.
24. A system, comprising:
a processor;
a wireless interface coupled to the processor; and
a memory coupled to the processor, the memory including:
an electrode;
an adhesive material;
a dielectric material between the electrode and the adhesive material,
wherein a portion of the adhesive material, a portion of the dielectric material, and a portion of the electrode form a substantially planar surface; and
a phase change material on the substantially planar surface and contacting the electrode, the adhesive material, and the dielectric material.
25. The system of claim 24 , wherein the dielectric material contacts a portion of a sidewall of the electrode.
26. The system of claim 25 , wherein the adhesive material surrounds an upper portion of the electrode and is separated from the electrode by the dielectric material.
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DE60308726T DE60308726T2 (en) | 2002-12-13 | 2003-06-09 | PHASE CHANGING MEMBERS AND THEIR MANUFACTURING PROCESS |
AU2003239249A AU2003239249A1 (en) | 2002-12-13 | 2003-06-09 | Phase change memory and manufacturing method therefor |
EP03734545A EP1570532B1 (en) | 2002-12-13 | 2003-06-09 | Phase change memory and manufacturing method therefor |
PCT/US2003/018374 WO2004055916A2 (en) | 2002-12-13 | 2003-06-09 | Phase change memory and manufacturing method therefor |
AT03734545T ATE341101T1 (en) | 2002-12-13 | 2003-06-09 | PHASE CHANGE MEMORY AND ITS PRODUCTION PROCESS |
TW092115846A TWI236730B (en) | 2002-12-13 | 2003-06-11 | Phase change apparatus, system, and method |
SG200304816-2A SG133402A1 (en) | 2002-12-13 | 2003-08-08 | Phase change memory and method therefor |
CNB031546846A CN100401546C (en) | 2002-12-13 | 2003-08-25 | Phase change memory and producing method thereof |
DE10339061A DE10339061A1 (en) | 2002-12-13 | 2003-08-26 | Phase change memory and manufacturing process |
KR10-2003-0076797A KR100520926B1 (en) | 2002-12-13 | 2003-10-31 | Phase change memory and method therefor |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040178402A1 (en) * | 2003-03-10 | 2004-09-16 | Ovshinsky Stanford R. | Multi-terminal device having logic functional |
US20050019975A1 (en) * | 2003-07-23 | 2005-01-27 | Se-Ho Lee | Phase change memory devices having phase change area in porous dielectric layer and methods for manufacturing the same |
US20050152208A1 (en) * | 2002-02-20 | 2005-07-14 | Stmicroelectronics S.R.L. | Phase change memory cell and manufacturing method thereof using minitrenches |
US20050205964A1 (en) * | 2004-03-17 | 2005-09-22 | Chen Yi C | Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method |
US20060084227A1 (en) * | 2004-10-14 | 2006-04-20 | Paola Besana | Increasing adherence of dielectrics to phase change materials |
US20060133174A1 (en) * | 2004-12-16 | 2006-06-22 | Korea Institute Of Science And Technology | Phase-change RAM containing AIN thermal dissipation layer and TiN electrode |
US20060223268A1 (en) * | 2005-03-30 | 2006-10-05 | Renesas Technology Corp. | Phase-change random access memory and process for producing same |
US20080258125A1 (en) * | 2007-04-17 | 2008-10-23 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
EP2017906A1 (en) * | 2007-07-17 | 2009-01-21 | STMicroelectronics S.r.l. | Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element |
US20090250680A1 (en) * | 2003-05-22 | 2009-10-08 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US20100163817A1 (en) * | 2008-12-30 | 2010-07-01 | Stmicroelectronics, S.R.L. | Self-heating phase change memory cell architecture |
US20110298087A1 (en) * | 2006-01-20 | 2011-12-08 | Stmicroelectronics S.R.L. | Electrical fuse device based on a phase-change memory element and corresponding programming method |
US20120287707A1 (en) * | 2005-08-23 | 2012-11-15 | International Business Machines Corporation | Optoelectronic memory devices |
US11430954B2 (en) | 2020-11-30 | 2022-08-30 | International Business Machines Corporation | Resistance drift mitigation in non-volatile memory cell |
Families Citing this family (206)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7247876B2 (en) * | 2000-06-30 | 2007-07-24 | Intel Corporation | Three dimensional programmable device and method for fabricating the same |
US6864503B2 (en) * | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US20050029504A1 (en) * | 2003-08-04 | 2005-02-10 | Karpov Ilya V. | Reducing parasitic conductive paths in phase change memories |
US20050032269A1 (en) * | 2003-08-04 | 2005-02-10 | Daniel Xu | Forming planarized semiconductor structures |
WO2005112118A1 (en) * | 2004-05-14 | 2005-11-24 | Renesas Technology Corp. | Semiconductor memory |
US20050263801A1 (en) * | 2004-05-27 | 2005-12-01 | Jae-Hyun Park | Phase-change memory device having a barrier layer and manufacturing method |
US7482616B2 (en) * | 2004-05-27 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
US7411208B2 (en) * | 2004-05-27 | 2008-08-12 | Samsung Electronics Co., Ltd. | Phase-change memory device having a barrier layer and manufacturing method |
KR100655796B1 (en) | 2004-08-17 | 2006-12-11 | 삼성전자주식회사 | Phase-changeable memory device and method of manufacturing the same |
US7687830B2 (en) * | 2004-09-17 | 2010-03-30 | Ovonyx, Inc. | Phase change memory with ovonic threshold switch |
US7135727B2 (en) * | 2004-11-10 | 2006-11-14 | Macronix International Co., Ltd. | I-shaped and L-shaped contact structures and their fabrication methods |
US7608503B2 (en) * | 2004-11-22 | 2009-10-27 | Macronix International Co., Ltd. | Side wall active pin memory and manufacturing method |
US7220983B2 (en) * | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
DE102004059428A1 (en) | 2004-12-09 | 2006-06-22 | Infineon Technologies Ag | Manufacturing method for a microelectronic electrode structure, in particular for a PCM memory element, and corresponding microelectronic electrode structure |
EP1677372B1 (en) | 2004-12-30 | 2008-05-14 | STMicroelectronics S.r.l. | Phase change memory and manufacturing method thereof |
US7709334B2 (en) | 2005-12-09 | 2010-05-04 | Macronix International Co., Ltd. | Stacked non-volatile memory device and methods for fabricating the same |
TWI261915B (en) * | 2005-01-07 | 2006-09-11 | Ind Tech Res Inst | Phase change memory and fabricating method thereof |
DE602005018744D1 (en) | 2005-04-08 | 2010-02-25 | St Microelectronics Srl | Lateral phase change memory |
US20060249724A1 (en) * | 2005-05-06 | 2006-11-09 | International Business Machines Corporation | Method and structure for Peltier-controlled phase change memory |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7514367B2 (en) * | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Method for manufacturing a narrow structure on an integrated circuit |
US7534647B2 (en) | 2005-06-17 | 2009-05-19 | Macronix International Co., Ltd. | Damascene phase change RAM and manufacturing method |
US7598512B2 (en) * | 2005-06-17 | 2009-10-06 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation layer and manufacturing method |
US7514288B2 (en) * | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Manufacturing methods for thin film fuse phase change ram |
US7238994B2 (en) * | 2005-06-17 | 2007-07-03 | Macronix International Co., Ltd. | Thin film plate phase change ram circuit and manufacturing method |
US8237140B2 (en) * | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7321130B2 (en) * | 2005-06-17 | 2008-01-22 | Macronix International Co., Ltd. | Thin film fuse phase change RAM and manufacturing method |
TWI273703B (en) * | 2005-08-19 | 2007-02-11 | Ind Tech Res Inst | A manufacture method and structure for improving the characteristics of phase change memory |
US7582413B2 (en) * | 2005-09-26 | 2009-09-01 | Asml Netherlands B.V. | Substrate, method of exposing a substrate, machine readable medium |
US20070111429A1 (en) * | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US7397060B2 (en) * | 2005-11-14 | 2008-07-08 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US7450411B2 (en) | 2005-11-15 | 2008-11-11 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7635855B2 (en) | 2005-11-15 | 2009-12-22 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US7394088B2 (en) * | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7786460B2 (en) * | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7414258B2 (en) | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
US7479649B2 (en) * | 2005-11-21 | 2009-01-20 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US7449710B2 (en) | 2005-11-21 | 2008-11-11 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7829876B2 (en) * | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
CN100524878C (en) | 2005-11-21 | 2009-08-05 | 旺宏电子股份有限公司 | Programmable resistor material storage array with air insulating unit |
US7507986B2 (en) | 2005-11-21 | 2009-03-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US7459717B2 (en) | 2005-11-28 | 2008-12-02 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
TWI291745B (en) * | 2005-11-30 | 2007-12-21 | Ind Tech Res Inst | Lateral phase change memory with spacer electrodes and method of manufacturing the same |
US7521364B2 (en) | 2005-12-02 | 2009-04-21 | Macronix Internation Co., Ltd. | Surface topology improvement method for plug surface areas |
US7605079B2 (en) * | 2005-12-05 | 2009-10-20 | Macronix International Co., Ltd. | Manufacturing method for phase change RAM with electrode layer process |
US7642539B2 (en) * | 2005-12-13 | 2010-01-05 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation pad and manufacturing method |
US7531825B2 (en) | 2005-12-27 | 2009-05-12 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US8062833B2 (en) * | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US7560337B2 (en) | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7741636B2 (en) | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7595218B2 (en) * | 2006-01-09 | 2009-09-29 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US20070158632A1 (en) * | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method for Fabricating a Pillar-Shaped Phase Change Memory Element |
US7825396B2 (en) * | 2006-01-11 | 2010-11-02 | Macronix International Co., Ltd. | Self-align planerized bottom electrode phase change memory and manufacturing method |
US7432206B2 (en) * | 2006-01-24 | 2008-10-07 | Macronix International Co., Ltd. | Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram |
US7456421B2 (en) * | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
US7897061B2 (en) * | 2006-02-01 | 2011-03-01 | Cabot Microelectronics Corporation | Compositions and methods for CMP of phase change alloys |
US7956358B2 (en) * | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
KR100718156B1 (en) | 2006-02-27 | 2007-05-14 | 삼성전자주식회사 | Phase change random access memory and method of manufacturing the same |
US7456420B2 (en) * | 2006-03-07 | 2008-11-25 | International Business Machines Corporation | Electrode for phase change memory device and method |
US7910907B2 (en) * | 2006-03-15 | 2011-03-22 | Macronix International Co., Ltd. | Manufacturing method for pipe-shaped electrode phase change memory |
US7345899B2 (en) * | 2006-04-07 | 2008-03-18 | Infineon Technologies Ag | Memory having storage locations within a common volume of phase change material |
US7554144B2 (en) * | 2006-04-17 | 2009-06-30 | Macronix International Co., Ltd. | Memory device and manufacturing method |
US7928421B2 (en) | 2006-04-21 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell with vacuum spacer |
US8129706B2 (en) * | 2006-05-05 | 2012-03-06 | Macronix International Co., Ltd. | Structures and methods of a bistable resistive random access memory |
US7608848B2 (en) * | 2006-05-09 | 2009-10-27 | Macronix International Co., Ltd. | Bridge resistance random access memory device with a singular contact structure |
US7423300B2 (en) | 2006-05-24 | 2008-09-09 | Macronix International Co., Ltd. | Single-mask phase change memory element |
US7820997B2 (en) * | 2006-05-30 | 2010-10-26 | Macronix International Co., Ltd. | Resistor random access memory cell with reduced active area and reduced contact areas |
US7732800B2 (en) * | 2006-05-30 | 2010-06-08 | Macronix International Co., Ltd. | Resistor random access memory cell with L-shaped electrode |
CN100423232C (en) * | 2006-06-02 | 2008-10-01 | 中国科学院上海微系统与信息技术研究所 | Method for preparing nanoelectronic memory by electron beam exposure and mechanochemical polishing process |
US7696506B2 (en) | 2006-06-27 | 2010-04-13 | Macronix International Co., Ltd. | Memory cell with memory material insulation and manufacturing method |
US7785920B2 (en) * | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7442603B2 (en) * | 2006-08-16 | 2008-10-28 | Macronix International Co., Ltd. | Self-aligned structure and method for confining a melting point in a resistor random access memory |
US7772581B2 (en) * | 2006-09-11 | 2010-08-10 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
KR100873878B1 (en) | 2006-09-27 | 2008-12-15 | 삼성전자주식회사 | Manufacturing method of phase change memory unit and manufacturing method of phase change memory device using same |
KR100766504B1 (en) | 2006-09-29 | 2007-10-15 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
US7504653B2 (en) | 2006-10-04 | 2009-03-17 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US20080090324A1 (en) * | 2006-10-12 | 2008-04-17 | Lee Jong-Won S | Forming sublithographic heaters for phase change memories |
US7510929B2 (en) * | 2006-10-18 | 2009-03-31 | Macronix International Co., Ltd. | Method for making memory cell device |
KR100766499B1 (en) * | 2006-10-20 | 2007-10-15 | 삼성전자주식회사 | Phase change memory device and method of forming the same |
US7388771B2 (en) | 2006-10-24 | 2008-06-17 | Macronix International Co., Ltd. | Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states |
US7863655B2 (en) | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
US7527985B2 (en) * | 2006-10-24 | 2009-05-05 | Macronix International Co., Ltd. | Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas |
US20080094885A1 (en) * | 2006-10-24 | 2008-04-24 | Macronix International Co., Ltd. | Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States |
KR100827661B1 (en) * | 2006-10-31 | 2008-05-07 | 삼성전자주식회사 | Phase change memory devices having dual lower electrodes and methods fabricating the same |
KR100780964B1 (en) | 2006-11-13 | 2007-12-03 | 삼성전자주식회사 | Phase change memory device having cell diode and method of fabricating the same |
US8067762B2 (en) | 2006-11-16 | 2011-11-29 | Macronix International Co., Ltd. | Resistance random access memory structure for enhanced retention |
WO2008061194A1 (en) * | 2006-11-16 | 2008-05-22 | Sandisk 3D Llc | Nonvolatile phase change memory cell having a reduced contact area and method of making |
US7728318B2 (en) * | 2006-11-16 | 2010-06-01 | Sandisk Corporation | Nonvolatile phase change memory cell having a reduced contact area |
US8163593B2 (en) | 2006-11-16 | 2012-04-24 | Sandisk Corporation | Method of making a nonvolatile phase change memory cell having a reduced contact area |
US20080137400A1 (en) * | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same |
US7476587B2 (en) * | 2006-12-06 | 2009-01-13 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7473576B2 (en) * | 2006-12-06 | 2009-01-06 | Macronix International Co., Ltd. | Method for making a self-converged void and bottom electrode for memory cell |
US7682868B2 (en) | 2006-12-06 | 2010-03-23 | Macronix International Co., Ltd. | Method for making a keyhole opening during the manufacture of a memory cell |
US7697316B2 (en) * | 2006-12-07 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level cell resistance random access memory with metal oxides |
US7903447B2 (en) * | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
US8344347B2 (en) * | 2006-12-15 | 2013-01-01 | Macronix International Co., Ltd. | Multi-layer electrode structure |
US7718989B2 (en) | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7515461B2 (en) * | 2007-01-05 | 2009-04-07 | Macronix International Co., Ltd. | Current compliant sensing architecture for multilevel phase change memory |
US7433226B2 (en) | 2007-01-09 | 2008-10-07 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell |
US7440315B2 (en) | 2007-01-09 | 2008-10-21 | Macronix International Co., Ltd. | Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell |
US7663135B2 (en) | 2007-01-31 | 2010-02-16 | Macronix International Co., Ltd. | Memory cell having a side electrode contact |
US7535756B2 (en) | 2007-01-31 | 2009-05-19 | Macronix International Co., Ltd. | Method to tighten set distribution for PCRAM |
US7619311B2 (en) | 2007-02-02 | 2009-11-17 | Macronix International Co., Ltd. | Memory cell device with coplanar electrode surface and method |
US7701759B2 (en) * | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7483292B2 (en) * | 2007-02-07 | 2009-01-27 | Macronix International Co., Ltd. | Memory cell with separate read and program paths |
US7463512B2 (en) * | 2007-02-08 | 2008-12-09 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
US8138028B2 (en) * | 2007-02-12 | 2012-03-20 | Macronix International Co., Ltd | Method for manufacturing a phase change memory device with pillar bottom electrode |
US7884343B2 (en) * | 2007-02-14 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory cell with filled sidewall memory element and method for fabricating the same |
US8008643B2 (en) * | 2007-02-21 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory cell with heater and method for fabricating the same |
US7619237B2 (en) * | 2007-02-21 | 2009-11-17 | Macronix International Co., Ltd. | Programmable resistive memory cell with self-forming gap |
US7956344B2 (en) * | 2007-02-27 | 2011-06-07 | Macronix International Co., Ltd. | Memory cell with memory element contacting ring-shaped upper end of bottom electrode |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US8610098B2 (en) | 2007-04-06 | 2013-12-17 | Macronix International Co., Ltd. | Phase change memory bridge cell with diode isolation device |
US7755076B2 (en) * | 2007-04-17 | 2010-07-13 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
US7483316B2 (en) * | 2007-04-24 | 2009-01-27 | Macronix International Co., Ltd. | Method and apparatus for refreshing programmable resistive memory |
US7593254B2 (en) | 2007-05-25 | 2009-09-22 | Micron Technology, Inc. | Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and methods of forming the same |
US8513637B2 (en) | 2007-07-13 | 2013-08-20 | Macronix International Co., Ltd. | 4F2 self align fin bottom electrodes FET drive phase change memory |
US7777215B2 (en) | 2007-07-20 | 2010-08-17 | Macronix International Co., Ltd. | Resistive memory structure with buffer layer |
US7884342B2 (en) * | 2007-07-31 | 2011-02-08 | Macronix International Co., Ltd. | Phase change memory bridge cell |
US7729161B2 (en) * | 2007-08-02 | 2010-06-01 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US9018615B2 (en) | 2007-08-03 | 2015-04-28 | Macronix International Co., Ltd. | Resistor random access memory structure having a defined small area of electrical contact |
US8178386B2 (en) | 2007-09-14 | 2012-05-15 | Macronix International Co., Ltd. | Phase change memory cell array with self-converged bottom electrode and method for manufacturing |
US7642125B2 (en) * | 2007-09-14 | 2010-01-05 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US7551473B2 (en) * | 2007-10-12 | 2009-06-23 | Macronix International Co., Ltd. | Programmable resistive memory with diode structure |
US7919766B2 (en) | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US7804083B2 (en) * | 2007-11-14 | 2010-09-28 | Macronix International Co., Ltd. | Phase change memory cell including a thermal protect bottom electrode and manufacturing methods |
US7646631B2 (en) * | 2007-12-07 | 2010-01-12 | Macronix International Co., Ltd. | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods |
US7639527B2 (en) | 2008-01-07 | 2009-12-29 | Macronix International Co., Ltd. | Phase change memory dynamic resistance test and manufacturing methods |
US7879643B2 (en) * | 2008-01-18 | 2011-02-01 | Macronix International Co., Ltd. | Memory cell with memory element contacting an inverted T-shaped bottom electrode |
US20090185411A1 (en) * | 2008-01-22 | 2009-07-23 | Thomas Happ | Integrated circuit including diode memory cells |
US7879645B2 (en) | 2008-01-28 | 2011-02-01 | Macronix International Co., Ltd. | Fill-in etching free pore device |
US8158965B2 (en) | 2008-02-05 | 2012-04-17 | Macronix International Co., Ltd. | Heating center PCRAM structure and methods for making |
US8084842B2 (en) | 2008-03-25 | 2011-12-27 | Macronix International Co., Ltd. | Thermally stabilized electrode structure |
US7729163B2 (en) * | 2008-03-26 | 2010-06-01 | Micron Technology, Inc. | Phase change memory |
US8030634B2 (en) | 2008-03-31 | 2011-10-04 | Macronix International Co., Ltd. | Memory array with diode driver and method for fabricating the same |
US7825398B2 (en) | 2008-04-07 | 2010-11-02 | Macronix International Co., Ltd. | Memory cell having improved mechanical stability |
US7791057B2 (en) | 2008-04-22 | 2010-09-07 | Macronix International Co., Ltd. | Memory cell having a buried phase change region and method for fabricating the same |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US7701750B2 (en) | 2008-05-08 | 2010-04-20 | Macronix International Co., Ltd. | Phase change device having two or more substantial amorphous regions in high resistance state |
US8415651B2 (en) | 2008-06-12 | 2013-04-09 | Macronix International Co., Ltd. | Phase change memory cell having top and bottom sidewall contacts |
US7759770B2 (en) * | 2008-06-23 | 2010-07-20 | Qimonda Ag | Integrated circuit including memory element with high speed low current phase change material |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US7903457B2 (en) | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7719913B2 (en) | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US7897954B2 (en) | 2008-10-10 | 2011-03-01 | Macronix International Co., Ltd. | Dielectric-sandwiched pillar memory device |
CN101728481B (en) * | 2008-10-24 | 2012-05-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing phase-change semiconductor device and phase-change semiconductor device |
US8036014B2 (en) * | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US8664689B2 (en) | 2008-11-07 | 2014-03-04 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions |
US8907316B2 (en) | 2008-11-07 | 2014-12-09 | Macronix International Co., Ltd. | Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions |
US7869270B2 (en) | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8107283B2 (en) | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8097871B2 (en) | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US7933139B2 (en) | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US8350316B2 (en) | 2009-05-22 | 2013-01-08 | Macronix International Co., Ltd. | Phase change memory cells having vertical channel access transistor and memory plane |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8536559B2 (en) | 2009-07-07 | 2013-09-17 | Macronix International Co., Ltd. | Phase change memory |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
TWI422084B (en) * | 2009-08-05 | 2014-01-01 | Macronix Int Co Ltd | Phase change memory |
US8283202B2 (en) * | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Single mask adder phase change memory element |
US8012790B2 (en) * | 2009-08-28 | 2011-09-06 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8283650B2 (en) * | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8278139B2 (en) | 2009-09-25 | 2012-10-02 | Applied Materials, Inc. | Passivating glue layer to improve amorphous carbon to metal adhesion |
US8551855B2 (en) * | 2009-10-23 | 2013-10-08 | Sandisk 3D Llc | Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8481396B2 (en) * | 2009-10-23 | 2013-07-09 | Sandisk 3D Llc | Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same |
US8129268B2 (en) | 2009-11-16 | 2012-03-06 | International Business Machines Corporation | Self-aligned lower bottom electrode |
US8233317B2 (en) * | 2009-11-16 | 2012-07-31 | International Business Machines Corporation | Phase change memory device suitable for high temperature operation |
US7943420B1 (en) * | 2009-11-25 | 2011-05-17 | International Business Machines Corporation | Single mask adder phase change memory element |
US8551850B2 (en) * | 2009-12-07 | 2013-10-08 | Sandisk 3D Llc | Methods of forming a reversible resistance-switching metal-insulator-metal structure |
US8017433B2 (en) * | 2010-02-09 | 2011-09-13 | International Business Machines Corporation | Post deposition method for regrowth of crystalline phase change material |
US8389375B2 (en) * | 2010-02-11 | 2013-03-05 | Sandisk 3D Llc | Memory cell formed using a recess and methods for forming the same |
US8237146B2 (en) * | 2010-02-24 | 2012-08-07 | Sandisk 3D Llc | Memory cell with silicon-containing carbon switching layer and methods for forming the same |
US20110210306A1 (en) * | 2010-02-26 | 2011-09-01 | Yubao Li | Memory cell that includes a carbon-based memory element and methods of forming the same |
US8471360B2 (en) | 2010-04-14 | 2013-06-25 | Sandisk 3D Llc | Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same |
CN102237492B (en) * | 2010-04-29 | 2013-04-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method for phase-change memory unit |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
CN102005466A (en) * | 2010-09-28 | 2011-04-06 | 中国科学院上海微系统与信息技术研究所 | Phase change memory structure with low-k medium heat insulating material and preparation method |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
CN102637820B (en) * | 2011-02-09 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory forming method |
US8987700B2 (en) | 2011-12-02 | 2015-03-24 | Macronix International Co., Ltd. | Thermally confined electrode for programmable resistance memory |
US8778211B2 (en) | 2012-07-17 | 2014-07-15 | Cabot Microelectronics Corporation | GST CMP slurries |
CN103151459B (en) * | 2013-03-28 | 2015-02-18 | 天津理工大学 | Hafnium-oxynitride-based low-power consumption resistive random access memory and preparation method for same |
JP5740443B2 (en) * | 2013-09-11 | 2015-06-24 | 株式会社東芝 | Transmission system |
US9336879B2 (en) | 2014-01-24 | 2016-05-10 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9159412B1 (en) | 2014-07-15 | 2015-10-13 | Macronix International Co., Ltd. | Staggered write and verify for phase change memory |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) * | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) * | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US5296716A (en) * | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5789758A (en) * | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5879955A (en) * | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5933365A (en) * | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5970336A (en) * | 1996-08-22 | 1999-10-19 | Micron Technology, Inc. | Method of making memory cell incorporating a chalcogenide element |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6085341A (en) * | 1996-12-31 | 2000-07-04 | Intel Corporation | Memory test mode for wordline resistive defects |
US6087674A (en) * | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US6141241A (en) * | 1998-06-23 | 2000-10-31 | Energy Conversion Devices, Inc. | Universal memory element with systems employing same and apparatus and method for reading, writing and programming same |
US6229157B1 (en) * | 1996-06-18 | 2001-05-08 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6420725B1 (en) * | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US6147395A (en) * | 1996-10-02 | 2000-11-14 | Micron Technology, Inc. | Method for fabricating a small area of contact between electrodes |
US6569705B2 (en) * | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
-
2002
- 2002-12-13 US US10/319,753 patent/US6744088B1/en not_active Expired - Lifetime
-
2003
- 2003-06-09 DE DE60308726T patent/DE60308726T2/en not_active Expired - Lifetime
- 2003-06-09 AU AU2003239249A patent/AU2003239249A1/en not_active Abandoned
- 2003-06-09 EP EP03734545A patent/EP1570532B1/en not_active Expired - Lifetime
- 2003-06-09 WO PCT/US2003/018374 patent/WO2004055916A2/en not_active Application Discontinuation
- 2003-06-09 AT AT03734545T patent/ATE341101T1/en not_active IP Right Cessation
- 2003-06-11 TW TW092115846A patent/TWI236730B/en not_active IP Right Cessation
- 2003-08-08 SG SG200304816-2A patent/SG133402A1/en unknown
- 2003-08-25 CN CNB031546846A patent/CN100401546C/en not_active Expired - Fee Related
- 2003-08-26 DE DE10339061A patent/DE10339061A1/en not_active Withdrawn
- 2003-10-31 KR KR10-2003-0076797A patent/KR100520926B1/en active IP Right Grant
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) * | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) * | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US5296716A (en) * | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5789758A (en) * | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5879955A (en) * | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5920788A (en) * | 1995-06-07 | 1999-07-06 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US6002140A (en) * | 1995-06-07 | 1999-12-14 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US6229157B1 (en) * | 1996-06-18 | 2001-05-08 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US5998244A (en) * | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US5970336A (en) * | 1996-08-22 | 1999-10-19 | Micron Technology, Inc. | Method of making memory cell incorporating a chalcogenide element |
US6153890A (en) * | 1996-08-22 | 2000-11-28 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element |
US6087674A (en) * | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US6085341A (en) * | 1996-12-31 | 2000-07-04 | Intel Corporation | Memory test mode for wordline resistive defects |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US5933365A (en) * | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US6141241A (en) * | 1998-06-23 | 2000-10-31 | Energy Conversion Devices, Inc. | Universal memory element with systems employing same and apparatus and method for reading, writing and programming same |
Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050152208A1 (en) * | 2002-02-20 | 2005-07-14 | Stmicroelectronics S.R.L. | Phase change memory cell and manufacturing method thereof using minitrenches |
US9876166B2 (en) | 2002-02-20 | 2018-01-23 | Micron Technology, Inc. | Phase change memory cell and manufacturing method thereof using minitrenches |
US20110237045A1 (en) * | 2002-02-20 | 2011-09-29 | Roberto Bez | Phase change memory cell and manufacturing method thereof using minitrenches |
US7993957B2 (en) * | 2002-02-20 | 2011-08-09 | Micron Technology, Inc. | Phase change memory cell and manufacturing method thereof using minitrenches |
US20040178402A1 (en) * | 2003-03-10 | 2004-09-16 | Ovshinsky Stanford R. | Multi-terminal device having logic functional |
US7186998B2 (en) * | 2003-03-10 | 2007-03-06 | Energy Conversion Devices, Inc. | Multi-terminal device having logic functional |
US8129707B2 (en) * | 2003-05-22 | 2012-03-06 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US20090250680A1 (en) * | 2003-05-22 | 2009-10-08 | Hitachi, Ltd. | Semiconductor integrated circuit device |
US7323708B2 (en) * | 2003-07-23 | 2008-01-29 | Samsung Electronics Co., Ltd. | Phase change memory devices having phase change area in porous dielectric layer |
US20050019975A1 (en) * | 2003-07-23 | 2005-01-27 | Se-Ho Lee | Phase change memory devices having phase change area in porous dielectric layer and methods for manufacturing the same |
US20060281218A1 (en) * | 2004-03-17 | 2006-12-14 | Macronix International Co., Ltd. | Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method |
US7112836B2 (en) * | 2004-03-17 | 2006-09-26 | Macronix International Co., Ltd. | Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method |
US20050205964A1 (en) * | 2004-03-17 | 2005-09-22 | Chen Yi C | Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method |
US7592617B2 (en) * | 2004-03-17 | 2009-09-22 | Macronix International Co., Ltd. | Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method |
US7338857B2 (en) * | 2004-10-14 | 2008-03-04 | Ovonyx, Inc. | Increasing adherence of dielectrics to phase change materials |
US20060084227A1 (en) * | 2004-10-14 | 2006-04-20 | Paola Besana | Increasing adherence of dielectrics to phase change materials |
US7307269B2 (en) * | 2004-12-16 | 2007-12-11 | Korea Institute Of Science And Technology | Phase-change RAM containing AIN thermal dissipation layer and TiN electrode |
US20060133174A1 (en) * | 2004-12-16 | 2006-06-22 | Korea Institute Of Science And Technology | Phase-change RAM containing AIN thermal dissipation layer and TiN electrode |
US20060223268A1 (en) * | 2005-03-30 | 2006-10-05 | Renesas Technology Corp. | Phase-change random access memory and process for producing same |
US20120287707A1 (en) * | 2005-08-23 | 2012-11-15 | International Business Machines Corporation | Optoelectronic memory devices |
US8410527B2 (en) * | 2006-01-20 | 2013-04-02 | Stmicroelectronics S.R.L. | Electrical fuse device based on a phase-change memory element and corresponding programming method |
US20110298087A1 (en) * | 2006-01-20 | 2011-12-08 | Stmicroelectronics S.R.L. | Electrical fuse device based on a phase-change memory element and corresponding programming method |
US20080258125A1 (en) * | 2007-04-17 | 2008-10-23 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
US7745231B2 (en) * | 2007-04-17 | 2010-06-29 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
US8193521B2 (en) | 2007-04-17 | 2012-06-05 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
US20100230654A1 (en) * | 2007-04-17 | 2010-09-16 | Jun Liu | Resistive memory cell fabrication methods and devices |
US8835893B2 (en) | 2007-04-17 | 2014-09-16 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
US9172040B2 (en) | 2007-04-17 | 2015-10-27 | Micron Technology, Inc. | Resistive memory cell fabrication methods and devices |
US8222627B2 (en) | 2007-07-17 | 2012-07-17 | Stmicroelectronics S.R.L | Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element |
EP2017906A1 (en) * | 2007-07-17 | 2009-01-21 | STMicroelectronics S.r.l. | Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element |
US20090050872A1 (en) * | 2007-07-17 | 2009-02-26 | Stmicroelectronics S.R.L. | Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element |
US20100163817A1 (en) * | 2008-12-30 | 2010-07-01 | Stmicroelectronics, S.R.L. | Self-heating phase change memory cell architecture |
US8377741B2 (en) * | 2008-12-30 | 2013-02-19 | Stmicroelectronics S.R.L. | Self-heating phase change memory cell architecture |
US11430954B2 (en) | 2020-11-30 | 2022-08-30 | International Business Machines Corporation | Resistance drift mitigation in non-volatile memory cell |
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DE10339061A1 (en) | 2004-07-15 |
EP1570532A2 (en) | 2005-09-07 |
KR100520926B1 (en) | 2005-10-17 |
DE60308726D1 (en) | 2006-11-09 |
TWI236730B (en) | 2005-07-21 |
SG133402A1 (en) | 2007-07-30 |
DE60308726T2 (en) | 2007-08-02 |
KR20040053769A (en) | 2004-06-24 |
AU2003239249A1 (en) | 2004-07-09 |
AU2003239249A8 (en) | 2004-07-09 |
WO2004055916A2 (en) | 2004-07-01 |
ATE341101T1 (en) | 2006-10-15 |
WO2004055916A3 (en) | 2004-08-12 |
TW200410367A (en) | 2004-06-16 |
CN100401546C (en) | 2008-07-09 |
US6744088B1 (en) | 2004-06-01 |
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