US20040111539A1 - Method and system for expanding the i/o on i/o limited devices - Google Patents
Method and system for expanding the i/o on i/o limited devices Download PDFInfo
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- US20040111539A1 US20040111539A1 US10/065,982 US6598202A US2004111539A1 US 20040111539 A1 US20040111539 A1 US 20040111539A1 US 6598202 A US6598202 A US 6598202A US 2004111539 A1 US2004111539 A1 US 2004111539A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
Definitions
- the present invention relates generally to circuit design, and more particularly, to electric-based designs with distributed input/output modules.
- a serial communication device is typically used to interface to the remote I/O (Input/Output) modules or nodes.
- I/O modules are often based on readily available standard products from a number of different companies, as is well known.
- a problem is often encountered, however, when the number of required Digital Inputs and/or Digital Outputs exceeds the number of available I/O in a standard device. This necessitates inundating a module with multiple I/O devices, specifying a more expensive high I/O count device, or designing a custom circuit.
- a method for expanding the Digital I/O capabilities for such a standard device is required.
- a standard Digital I/O device has a limited number of I/O lines, it may also generate READ and WRITE control lines in conjunction with a bidirectional data bus to interface with external write latches and READ buffers.
- One common method for I/O data transfer is to add more I/O modules. Such a solution, however, is very costly.
- an I/O system includes a Digital Device used in an application where multiple digital I/O are needed.
- the system further includes a Digital I/O Expansion Mechanism, electrically coupled to the Digital Device, including a first input bank, a FIFO, and an I/O line.
- the Digital I/O Expansion Mechanism is adapted to sample a first value of an initialized first input bank and detect a change in the input bank.
- the Digital I/O Expansion Mechanism is further adapted to store the state of a data bit of the input bank and a bank identifier in the FIFO, sample thus the data bit via a first READ cycle, drive the digital device a next data entry from the FIFO, and sample substantially all digital inputs.
- the Digital I/O Expansion Mechanism is adapted to store any detected changes in the FIFO and transmit all values in the FIFO to the Digital Device during subsequent READ cycles.
- the Digital I/O Expansion Mechanism is adapted to transmit a last value read to the Digital Device, change a digital output when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set, and write an entire bank in response to a bit change.
- the Digital I/O Expansion Mechanism is then adapted to decode and latch the digital output until the digital output is overwritten via a second WRITE command to the output bank from the Digital Device.
- a method for I/O data transfer includes sampling a first value of a first initialized input bank.
- the FIFO stores a state of a data bit of the input bank and a bank identifier.
- An expansion mechanism I/O line is sampled via a first READ cycle, and the I/O line is driven with a changed data entry from the FIFO.
- Substantially all digital inputs are sampled and the FIFO stores any detected changes. All values in the FIFO are transmitted to a Digital Device during a second READ cycle, and a last value read is also transmitted to the Digital Device.
- a digital output is changed when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set. An entire bank is written in response to a bit change. The expansion mechanism digital output is then decoded and latched until the expansion mechanism digital output is overwritten via a subsequent WRITE command to the input bank from the Digital Device.
- FIG. 1 is a distributed control arrangement system 1 wherein the present invention may be used to advantage;
- FIG. 2 is a block diagram of an I/O system in accordance with another embodiment of the present invention.
- FIG. 3 is a logic flow diagram of a Multiplexed Digital Input (MDI) description in accordance with another aspect of the present invention.
- FIG. 4 is a logic flow diagram of a De-Multiplexed Digital Output (DDO) description in accordance with another aspect of the present invention.
- DDO De-Multiplexed Digital Output
- the present invention is illustrated with respect to an I/O system, particularly suited to the medical field.
- the present invention is, however, applicable to various other uses that may require I/O data transfer, as will be understood by one skilled in the art.
- a distributed control arrangement system 1 includes remote I/O (Input/Output) lines interfaced with a serial communication device or distributed I/O circuit 11 , which is electrically coupled to a control unit 4 through a communication bus 6 , as will be understood by one skilled in the art.
- the present invention is implemented as part of the distributed I/O circuit 11 .
- the present invention includes embodiments having multiple implementations of the system 1 for expanding the I/O on I/O limited devices in, for example, a network connected by a communication bus.
- an I/O system 10 includes a distributed I/O circuit 11 including a Digital I/O Expansion Mechanism 12 , a clock 26 and a Digital I/O Device 28 (Digital Device).
- the system 10 is alternately embodied as including numerous variations and combinations to the disclosed invention that one skilled in the art would realize.
- the Digital I/O Expansion Mechanism 12 includes at least one of each of a multiplexer 14 , a demultiplexer 15 , a latch 16 , a memory device (e.g. a Random Access Memory 18 ), a change detector 20 , a First In First Out (FIFO 22 ), and an I/O Transmit and Receive Control 24 .
- the Digital I/O Expansion Mechanism 12 is synchronized through the clock 26 , which is coupled thereto.
- the multiplexer 15 is electrically coupled to the Random Access Memory 18 (RAM) and the change detector 20 , which are in turn electrically coupled to each other.
- the RAM 18 is also electrically coupled to the FIFO 22 , which is electrically coupled to the I/O Transmit and Receive Control 24 .
- the I/O Transmit and Receive Control 24 is electrically coupled to the Digital I/O Device 28 , the demultiplexer 15 , the change detector 20 , the RAM 18 and the FIFO 22 .
- the multiplexer 14 controls the transfer of data from a set of input busses 36 (multiplexer digital inputs from remote modules).
- the multiplexer 14 is embodied as a single component, however alternate embodiments include numerous components adapted to handle numerous sets of input busses.
- the RAM 18 receives multiplexer signals and I/O Transmit and Receive Control signals and exchanges data with the change detector 20 .
- the RAM 18 stores external signal data and can be read from and written into during normal system operation.
- the RAM 18 includes a first input bank and various other input banks as the system 10 requires.
- the RAM 18 resets and thereby clears a stored first value within the first input bank.
- the FIFO 22 receives RAM data signals and I/O Transmit and Receive Control signals and generates therefrom output signals.
- the FIFO 22 is a well known component in the art, which stores a series of data points and outputs the first inputted data point first.
- the I/O Transmit and Receive Control 24 receives the FIFO signals, control line signals and Data I/O Line signals from the Digital I/O Device 28 and generates therefrom control signals, which are received by the change detector 20 , the RAM 18 , the FIFO 22 , the demultiplexer 15 and the Digital I/O Device 28 through the Data I/O Lines 34 .
- the change detector 20 receives the signals from the I/O Transmit and Receive-Control 24 , the RAM 18 , and the multiplexer 14 and generates therefrom change signals.
- the change detector 20 is embodied as a typical change detector, which will be understood by one skilled in the art.
- the change detector detects a change between a first time and a second time and flags the aforementioned change, thereby generating the change signal.
- the demultiplexer 15 routes data from the I/O transmit and Receive Control signal to a plurality of Latch outputs.
- the multiplexer 14 is embodied as a single component, however alternate embodiments include numerous components adapted to handle numerous sets of input busses.
- the Latch 16 generates the demultiplexed digital outputs in response to the demultiplexer signals, as will be understood by one skilled in the art.
- the clock 26 synchronizes the components of the Digital I/O Expansion Mechanism 12 , as will be understood by one skilled in the art. Alternate embodiments, however, are asynchronous and do not include the clock 26 .
- the Digital I/O Device 28 includes an external communications I/O device 30 (for communicating with a system control device) and control lines 32 and Data I/O Lines 34 electrically coupled to the I/O Transmit and Receive Control 24 .
- the Digital I/O Expansion Mechanism, Digital I/O Device and clock are all included in the distributed I/O circuit 11 .
- the Digital I/O Device 28 generates control signals to indicate valid READ and WRITE cycles on the bidirectional data lines (Data I/O Lines 34 ).
- the Digital I/O Device 28 includes separate input and output lines.
- the timing of the data transmission at the input lines is managed by the Digital I/O Expansion Mechanism 12 such that Multiplexed Digital Input (MDI) data is driven at less than half the sampling data rate of the Digital I/O device 28 .
- MDI Multiplexed Digital Input
- DDOs De-Multiplexed Digital Outputs
- FIG. 3 a logic flow diagram 50 of a Multiplexed Digital Input (MDI) description is illustrated. Logic starts in operation block 52 where the Digital I/O Expansion Mechanism is first initialized (powered or reset), the stored value (in RAM) of each input bank is cleared.
- MDI Multiplexed Digital Input
- operation block 54 the value of each input bank is sampled and changes are detected.
- operation block 56 if a change is detected, the state of the input bank data bits, along with the bank identifier, is stored in a First In First Out memory device;! otherwise known as a FIFO.
- operation block 58 the digital input device samples the 8 Digital Device I/O lines via a READ cycle.
- operation block 60 the Digital I/O Expansion Mechanism drives the I/O lines with the next data entry from the FIFO.
- FIFO values are transmitted to the Digital Device. Once all values in the FIFO have been transmitted to the Digital Device during the READ cycles, in operation block 69 , the value subsequently transmitted to the Digital Device will be the last value read. In this way the Digital Device knows that no new digital inputs have changed. The size of the FIFO must be selected such that it will not overflow given the worst-case rate of change of the digital inputs at the READ duty cycle of the Digital I/O Device.
- FIG. 4 a logic flow diagram 70 of a De-Multiplexed Digital Output (DDO) description, in accordance with another embodiment of the present invention, is illustrated.
- Logic starts in operation block 72 , where the digital outputs are changed when a WRITE occurs and the Digital Device explicitly selects an output to be set.
- operation block 74 an entire bank (i.e. all the data bits in the bank) is written for any bit change.
- operation block 76 this data output value is decoded and latched until it is overwritten via another WRITE command to this bank from the Digital Device.
- a method for I/O data transfer includes clearing a stored value of a first input bank and sampling a first value of the first input bank. A change is detected in the input bank.
- the FIFO stores a state of a data bit of the input bank and a bank identifier.
- An I/O line is sampled via a first READ cycle, and the I/O line is driven with a next data entry from the FIFO. Substantially all digital inputs are sampled and the FIFO stores any detected changes. All values in the FIFO are transmitted to a Digital Device during subsequent READ cycles, and a last value read is also transmitted to the Digital Device.
- alternate embodiments of the present invention require as many READs as data banks in the FIFO are filled. For example, if the FIFO has “x” data banks, then approximately “x” READs are needed to obtain all the data.
- a digital output is changed when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set. An entire bank is written in response to a bit change. The digital output is then decoded and latched until the digital output is overwritten via a second WRITE command to the input bank from the, Digital Device.
- Alternate embodiments of the present invention are applicable to devices including numerous inputs and outputs, as will be understood by one skilled in the art.
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Abstract
Description
- The present invention relates generally to circuit design, and more particularly, to electric-based designs with distributed input/output modules.
- In a system including a distributed control arrangement, a serial communication device is typically used to interface to the remote I/O (Input/Output) modules or nodes. These I/O modules are often based on readily available standard products from a number of different companies, as is well known. A problem is often encountered, however, when the number of required Digital Inputs and/or Digital Outputs exceeds the number of available I/O in a standard device. This necessitates inundating a module with multiple I/O devices, specifying a more expensive high I/O count device, or designing a custom circuit. When the required rate of change of inputs in such a module is low compared to the rate at which the data can be transmitted to the consumer of the digital input data, a method for expanding the Digital I/O capabilities for such a standard device is required.
- A standard Digital I/O device has a limited number of I/O lines, it may also generate READ and WRITE control lines in conjunction with a bidirectional data bus to interface with external write latches and READ buffers. One common method for I/O data transfer is to add more I/O modules. Such a solution, however, is very costly.
- The disadvantages associated with current I/O systems have made it apparent that a new technique for expanding the I/O on I/O limited devices is needed. The new technique should substantially provide a low cost solution while maintaining efficient data transfer. The present invention is directed to these ends.
- In accordance with one aspect of the invention, an I/O system includes a Digital Device used in an application where multiple digital I/O are needed. The system further includes a Digital I/O Expansion Mechanism, electrically coupled to the Digital Device, including a first input bank, a FIFO, and an I/O line. The Digital I/O Expansion Mechanism is adapted to sample a first value of an initialized first input bank and detect a change in the input bank. The Digital I/O Expansion Mechanism is further adapted to store the state of a data bit of the input bank and a bank identifier in the FIFO, sample thus the data bit via a first READ cycle, drive the digital device a next data entry from the FIFO, and sample substantially all digital inputs. The Digital I/O Expansion Mechanism is adapted to store any detected changes in the FIFO and transmit all values in the FIFO to the Digital Device during subsequent READ cycles. The Digital I/O Expansion Mechanism is adapted to transmit a last value read to the Digital Device, change a digital output when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set, and write an entire bank in response to a bit change. The Digital I/O Expansion Mechanism is then adapted to decode and latch the digital output until the digital output is overwritten via a second WRITE command to the output bank from the Digital Device.
- In accordance with another aspect of the invention, a method for I/O data transfer includes sampling a first value of a first initialized input bank. When a change is detected, the FIFO stores a state of a data bit of the input bank and a bank identifier. An expansion mechanism I/O line is sampled via a first READ cycle, and the I/O line is driven with a changed data entry from the FIFO. Substantially all digital inputs are sampled and the FIFO stores any detected changes. All values in the FIFO are transmitted to a Digital Device during a second READ cycle, and a last value read is also transmitted to the Digital Device. A digital output is changed when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set. An entire bank is written in response to a bit change. The expansion mechanism digital output is then decoded and latched until the expansion mechanism digital output is overwritten via a subsequent WRITE command to the input bank from the Digital Device.
- The advantages of this application are that all the subsystem digital inputs and outputs can be consolidated to one Digital Device for efficient and cost effective performance. The method of expanding of a finite number of digital I/O lines eliminates the need to require multiple Digital I/O devices.
- Other objects and advantages of the present invention will become apparent upon the following detailed description and appended claims, and upon reference to the accompanying drawings.
- FIG. 1 is a distributed control arrangement system1 wherein the present invention may be used to advantage;
- FIG. 2 is a block diagram of an I/O system in accordance with another embodiment of the present invention;
- FIG. 3 is a logic flow diagram of a Multiplexed Digital Input (MDI) description in accordance with another aspect of the present invention; and
- FIG. 4 is a logic flow diagram of a De-Multiplexed Digital Output (DDO) description in accordance with another aspect of the present invention.
- The present invention is illustrated with respect to an I/O system, particularly suited to the medical field. The present invention is, however, applicable to various other uses that may require I/O data transfer, as will be understood by one skilled in the art.
- Referring to FIG. 1, a distributed control arrangement system1 includes remote I/O (Input/Output) lines interfaced with a serial communication device or distributed I/O circuit 11 , which is electrically coupled to a control unit 4 through a
communication bus 6, as will be understood by one skilled in the art. The present invention is implemented as part of the distributed I/O circuit 11. Important to note is that the present invention includes embodiments having multiple implementations of the system 1 for expanding the I/O on I/O limited devices in, for example, a network connected by a communication bus. - Referring to FIG. 2, an I/
O system 10 includes a distributed I/O circuit 11 including a Digital I/O Expansion Mechanism 12, aclock 26 and a Digital I/O Device 28 (Digital Device). Thesystem 10 is alternately embodied as including numerous variations and combinations to the disclosed invention that one skilled in the art would realize. - The Digital I/
O Expansion Mechanism 12 includes at least one of each of amultiplexer 14, ademultiplexer 15, alatch 16, a memory device (e.g. a Random Access Memory 18), a change detector 20, a First In First Out (FIFO 22), and an I/O Transmit andReceive Control 24. The Digital I/O Expansion Mechanism 12 is synchronized through theclock 26, which is coupled thereto. - The
multiplexer 15 is electrically coupled to the Random Access Memory 18 (RAM) and the change detector 20, which are in turn electrically coupled to each other. TheRAM 18 is also electrically coupled to the FIFO 22, which is electrically coupled to the I/O Transmit andReceive Control 24. The I/O Transmit and ReceiveControl 24 is electrically coupled to the Digital I/O Device 28, thedemultiplexer 15, the change detector 20, theRAM 18 and the FIFO 22. - The
multiplexer 14 controls the transfer of data from a set of input busses 36 (multiplexer digital inputs from remote modules). Themultiplexer 14 is embodied as a single component, however alternate embodiments include numerous components adapted to handle numerous sets of input busses. - The
RAM 18, or an alternate memory device used in place of theRAM 18, receives multiplexer signals and I/O Transmit and Receive Control signals and exchanges data with the change detector 20. TheRAM 18 stores external signal data and can be read from and written into during normal system operation. TheRAM 18 includes a first input bank and various other input banks as thesystem 10 requires. TheRAM 18 resets and thereby clears a stored first value within the first input bank. - The FIFO22 receives RAM data signals and I/O Transmit and Receive Control signals and generates therefrom output signals. The FIFO 22 is a well known component in the art, which stores a series of data points and outputs the first inputted data point first.
- The I/O Transmit and Receive Control24 receives the FIFO signals, control line signals and Data I/O Line signals from the Digital I/
O Device 28 and generates therefrom control signals, which are received by the change detector 20, theRAM 18, the FIFO 22, thedemultiplexer 15 and the Digital I/O Device 28 through the Data I/O Lines 34. - The change detector20 receives the signals from the I/O Transmit and Receive-
Control 24, theRAM 18, and themultiplexer 14 and generates therefrom change signals. The change detector 20 is embodied as a typical change detector, which will be understood by one skilled in the art. The change detector detects a change between a first time and a second time and flags the aforementioned change, thereby generating the change signal. - The
demultiplexer 15 routes data from the I/O transmit and Receive Control signal to a plurality of Latch outputs. Themultiplexer 14 is embodied as a single component, however alternate embodiments include numerous components adapted to handle numerous sets of input busses. - The
Latch 16 generates the demultiplexed digital outputs in response to the demultiplexer signals, as will be understood by one skilled in the art. - The
clock 26 synchronizes the components of the Digital I/O Expansion Mechanism 12, as will be understood by one skilled in the art. Alternate embodiments, however, are asynchronous and do not include theclock 26. - The Digital I/
O Device 28 includes an external communications I/O device 30 (for communicating with a system control device) andcontrol lines 32 and Data I/O Lines 34 electrically coupled to the I/O Transmit and ReceiveControl 24. The Digital I/O Expansion Mechanism, Digital I/O Device and clock are all included in the distributed I/O circuit 11. In the preferred embodiment of this invention, the Digital I/O Device 28 generates control signals to indicate valid READ and WRITE cycles on the bidirectional data lines (Data I/O Lines 34). In another embodiment of the design, the Digital I/O Device 28 includes separate input and output lines. The timing of the data transmission at the input lines, however, is managed by the Digital I/O Expansion Mechanism 12 such that Multiplexed Digital Input (MDI) data is driven at less than half the sampling data rate of the Digital I/O device 28. De-Multiplexed Digital Outputs (DDOs) are updated by the Digital I/O Expansion Mechanism when a change is detected on the Digital I/O Device output data lines 34. - In FIG. 3, a logic flow diagram50 of a Multiplexed Digital Input (MDI) description is illustrated. Logic starts in
operation block 52 where the Digital I/O Expansion Mechanism is first initialized (powered or reset), the stored value (in RAM) of each input bank is cleared. - In
operation block 54, the value of each input bank is sampled and changes are detected. Inoperation block 56, if a change is detected, the state of the input bank data bits, along with the bank identifier, is stored in a First In First Out memory device;! otherwise known as a FIFO. Inoperation block 58, the digital input device samples the 8 Digital Device I/O lines via a READ cycle. Inoperation block 60, the Digital I/O Expansion Mechanism drives the I/O lines with the next data entry from the FIFO. - In
operation block 64, completion of this READ cycle initiates another sampling of all digital inputs, with any detected changes stored in the FIFO inoperation block 66. - In
operation block 68, FIFO values are transmitted to the Digital Device. Once all values in the FIFO have been transmitted to the Digital Device during the READ cycles, inoperation block 69, the value subsequently transmitted to the Digital Device will be the last value read. In this way the Digital Device knows that no new digital inputs have changed. The size of the FIFO must be selected such that it will not overflow given the worst-case rate of change of the digital inputs at the READ duty cycle of the Digital I/O Device. - In FIG. 4, a logic flow diagram70 of a De-Multiplexed Digital Output (DDO) description, in accordance with another embodiment of the present invention, is illustrated. Logic starts in
operation block 72, where the digital outputs are changed when a WRITE occurs and the Digital Device explicitly selects an output to be set. Inoperation block 74, an entire bank (i.e. all the data bits in the bank) is written for any bit change. Inoperation block 76, this data output value is decoded and latched until it is overwritten via another WRITE command to this bank from the Digital Device. - In operation, a method for I/O data transfer includes clearing a stored value of a first input bank and sampling a first value of the first input bank. A change is detected in the input bank. The FIFO stores a state of a data bit of the input bank and a bank identifier. An I/O line is sampled via a first READ cycle, and the I/O line is driven with a next data entry from the FIFO. Substantially all digital inputs are sampled and the FIFO stores any detected changes. All values in the FIFO are transmitted to a Digital Device during subsequent READ cycles, and a last value read is also transmitted to the Digital Device. Important to note is that alternate embodiments of the present invention require as many READs as data banks in the FIFO are filled. For example, if the FIFO has “x” data banks, then approximately “x” READs are needed to obtain all the data. A digital output is changed when a first WRITE command occurs and the Digital Device explicitly selects the digital output to be set. An entire bank is written in response to a bit change. The digital output is then decoded and latched until the digital output is overwritten via a second WRITE command to the input bank from the, Digital Device. Alternate embodiments of the present invention are applicable to devices including numerous inputs and outputs, as will be understood by one skilled in the art.
- While the invention has been described in connection with one or more embodiments, it should be understood that the invention is not limited to those embodiments. On the contrary, the invention is intended to cover all alternatives, modifications, and equivalents, as may be included within the spirit and scope of the appended claims.
Claims (17)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105717342A (en) * | 2016-03-18 | 2016-06-29 | 浙江中控技术股份有限公司 | Analog quantity current input collecting system |
CN106200749A (en) * | 2016-09-26 | 2016-12-07 | 浙江中控技术股份有限公司 | A kind of IO control system |
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US4060849A (en) * | 1975-10-28 | 1977-11-29 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull | Data input and output controller |
US5261049A (en) * | 1991-07-22 | 1993-11-09 | International Business Machines Corporation | Video RAM architecture incorporating hardware decompression |
US5895978A (en) * | 1997-04-02 | 1999-04-20 | International Business Machines Corporation | High density signal multiplexing interposer |
US6492726B1 (en) * | 2000-09-22 | 2002-12-10 | Chartered Semiconductor Manufacturing Ltd. | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection |
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2002
- 2002-12-06 US US10/065,982 patent/US6751678B1/en not_active Expired - Fee Related
Patent Citations (4)
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US4060849A (en) * | 1975-10-28 | 1977-11-29 | Compagnie Internationale Pour L'informatique Cii-Honeywell Bull | Data input and output controller |
US5261049A (en) * | 1991-07-22 | 1993-11-09 | International Business Machines Corporation | Video RAM architecture incorporating hardware decompression |
US5895978A (en) * | 1997-04-02 | 1999-04-20 | International Business Machines Corporation | High density signal multiplexing interposer |
US6492726B1 (en) * | 2000-09-22 | 2002-12-10 | Chartered Semiconductor Manufacturing Ltd. | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105717342A (en) * | 2016-03-18 | 2016-06-29 | 浙江中控技术股份有限公司 | Analog quantity current input collecting system |
CN106200749A (en) * | 2016-09-26 | 2016-12-07 | 浙江中控技术股份有限公司 | A kind of IO control system |
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