US20040084708A1 - Method for fabricating a trench capacitor - Google Patents
Method for fabricating a trench capacitor Download PDFInfo
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- US20040084708A1 US20040084708A1 US10/283,483 US28348302A US2004084708A1 US 20040084708 A1 US20040084708 A1 US 20040084708A1 US 28348302 A US28348302 A US 28348302A US 2004084708 A1 US2004084708 A1 US 2004084708A1
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- trench
- collar
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- forming
- oxide
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- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 230000015654 memory Effects 0.000 claims abstract description 34
- 230000005684 electric field Effects 0.000 claims abstract description 11
- 238000004891 communication Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 7
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 210000004027 cell Anatomy 0.000 description 24
- 239000000463 material Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 210000000352 storage cell Anatomy 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66166—Resistors with PN junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
Definitions
- the present invention relates to a memory cell, and methods of forming same, where the memory cell includes a trench capacitor, an array FET, and a collar.
- Memory arrays such as dynamic random access memories (DRAMs), employ memory cell structures, where each memory cell stores one bit of information.
- a typical storage cell includes a single array transistor, e.g., a field effect transistor (FET), and a capacitor coupled from one of the source and drain of the FET to ground. The gate of the FET is connected to a word line and the other of the drain and source of the FET is connected to a bit line.
- FET field effect transistor
- FIG. 1 An example of such a conventional structure of a memory cell 10 is illustrated in FIG. 1.
- the memory cell 10 includes a trench capacitor 14 and a vertically aligned FET 16 .
- the trench capacitor 14 includes a polysilicon layer 18 and a buried plate 20 at a lower portion of the layer 18 .
- the FET 16 includes a gate portion 22 , a source portion 24 , a drain portion 26 , and a channel 28 .
- the drain portion 26 may include a buried strap coupled to an upper portion of the polysilicon layer 18 of the trench capacitor 14 .
- a collar 30 is disposed about the upper portion of the polysilicon layer 18 .
- the structure of the memory cell 10 of FIG. 1 is widely used in so-called trench capacitor design, it suffers from a significant disadvantage.
- a parasitic transistor is inherent in the memory cell 10 between the buried strap 26 and the buried plate 20 .
- This parasitic transistor permits a significant electric field between the buried strap 26 and the buried plate 20 , which also permits undesirable leakage along the trench from the buried plate 20 to the buried strap 26 .
- this undesirably affects the storage capabilities of the memory cell 10 , including significantly reducing any charge stored on the trench capacitor 14 .
- a memory cell includes a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.
- the re-entrant bend of the collar includes a substantially sharp distal edge. Further, it is preferred that the re-entrant bend of the collar is between about 200-300 nm in length.
- the collar is preferably formed of an oxide.
- the array FET may be vertically oriented or horizontally oriented.
- a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; etching the trench in an area substantially at an upper portion of the buried plate to form a re-entrant bend in a sidewall of the trench; and forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion of the trench.
- step of forming the re-entrant bend includes using NH 4 OH/HF etching cycles such that oxide consumption is less than about 60 angstroms.
- the re-entrant bend of the collar includes a substantially sharp distal edge.
- the method may further include forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge prior to forming the buried plate; forming an oxide in the trench after forming the buried plate that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; and removing a portion of the oxide from the trench that extends from the resist to the upper edge to form an exposed portion of the sidewall of the trench.
- the exposed portion of the sidewall is between about 200-300 nm in length.
- the sacrificial collar may be formed from one of nitride and a polysilicon.
- the step of forming a re-entrant bend in the sidewall of the trench includes etching the trench in the exposed area of the sidewall between the oxide and the sacrificial collar.
- the method may further include forming a trench capacitor by filling at least a portion of the trench with a silicon layer having an upper portion and a lower portion; and forming an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, wherein the buried strap is in communication with the upper portion of the trench silicon layer and the collar is between the buried strap and the buried plate such that the re-entrant bend thereof is operable to decrease an electric field between the buried strap and the buried plate.
- the silicon layer of the trench capacitor may be formed of polysilicon.
- a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; forming an oxide in the trench that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; removing a portion of the oxide from the trench that extends from the resist to the upper edge; removing the resist from the trench; etching the trench in the area between the lower edge of the sacrificial collar and the oxide to form a re-entrant bend in a sidewall of the trench; forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion
- FIG. 1 is a schematic cross-sectional view of a memory cell in accordance with the prior art
- FIG. 2 is a schematic cross-sectional view of a memory cell in accordance with one or more aspects of the present invention
- FIG. 3 is a schematic cross-sectional view of an alternative configuration of a memory cell employing one or more aspects of the present invention
- FIGS. 4 A-K are schematic cross-sectional views illustrating a process of making a memory cell in accordance with one or more aspects of the present invention.
- FIG. 5 is a schematic cross-sectional view of a further alternative configuration of a memory cell employing one or more aspects of the present invention.
- FIG. 2 a cross-sectional view of a memory cell 100 in accordance with one or more aspects of the present invention.
- the memory cell 100 includes a trench capacitor 104 and an array FET 106 , disposed in a vertical orientation.
- the trench capacitor 104 includes a trench silicon layer 108 having an upper portion and a lower portion.
- the trench silicon layer 108 is preferably formed from a polysilicon material.
- the trench capacitor 104 preferably further includes a buried plate 110 disposed about the lower portion of the trench silicon layer 108 .
- the array FET 106 preferably includes a gate portion 112 , a source portion 114 , a drain portion 116 , and a channel 118 .
- the drain portion 116 preferably includes a buried strap that is in communication with the upper portion of the trench silicon layer 108 .
- the vertically oriented array FET 106 is illustrated and described herein by way of example and not by way of limitation. Indeed, as discussed hereinbelow, a planar (horizontally oriented) array FET may also be employed without departing from the spirit and scope of the invention. Further, while a single sided buried strap is illustrated for discussion purposes, any of the known buried strap configurations may be employed without departing from the invention.
- the memory cell 100 preferably further includes a collar 120 disposed about at least the upper portion of the trench silicon layer 108 and between the buried strap 116 and the buried plate 110 .
- the collar 120 preferably includes a re-entrant bend 120 A that is operable to decrease an electric field between the buried strap 116 and the buried plate 110 .
- the re-entrant bend 120 A of the collar 120 includes a substantially sharp distal edge that is radially spaced away from sidewalls of the trench silicon layer 108 . It is most preferred that the re-entrant bend 120 A has an overall length (as opposed to a path length) of between about 200-300 nm.
- the overall length of the re-entrant bend 120 A is preferably measured in a substantially straight line from top to bottom as seen in the figures.
- the path length of the re-entrant bend 120 A is preferably measured along the path of the bend from top to bottom. Using these definitions, the path length of the re-entrant bend 120 A would be longer than the overall length thereof.
- the collar 120 is formed from an oxide, such as silicon dioxide.
- the collar 120 including the re-entrant bend 120 A, may be employed in an alternative memory cell structure 102 having a bottle-etched trench capacitor 104 A.
- the re-entrant bend 120 A is preferably disposed between the buried strap 116 and the buried plate 110 A such that any electric field between the buried strap 116 and the buried plate 110 A is reduced.
- the re-entrant bend 120 A of the collar 120 reduces the electric field between the buried strap 116 and the buried plate 110 , thereby reducing and/or eliminating the parasitic transistor between the buried strap 116 and the buried plate 110 . Further, leakage from the buried plate 110 to the buried strap 116 is significantly reduced, thereby improving the storage characteristics of the trench capacitor 104 . A further advantage is obtained in that a thickness of the collar 120 may be significantly reduced, therefore allowing a larger opening and a corresponding larger trench silicon layer 108 , which results in a lower series resistance.
- a trench 200 is etched into a substrate 102 , such as a P-type silicon substrate.
- a sacrificial collar 202 is preferably formed on an upper portion of the trench 200 , which sacrificial collar 200 preferably extends down to a lower edge 202 A.
- the sacrificial collar 202 A may be formed utilizing any of the known techniques, such as by forming a nitride, or utilizing a polysilicon material.
- the buried plate 110 is preferably formed by diffusing a dopant into the substrate 102 proximate to the lower portion of the trench 200 .
- a dopant may be diffused into the P-type substrate 102 to form the buried plate 110 .
- a bottle-etched trench capacitor 104 A is desired, a bottle-etch process would be performed prior to diffusing the dopant into the substrate 102 .
- an oxide 204 is preferably formed in the trench 200 proximate to the buried plate 110 .
- the oxide 204 may be formed utilizing any of the known techniques, such as a dry, rapid thermal oxidation (RTO) process. It is preferred that the oxide 204 is approximately sixty angstroms thick. As illustrated, the oxide 204 preferably extends up the trench 200 to an upper edge 204 A. It is most preferred that the upper edge 204 A of the oxide 204 extends to the lower edge 202 A of the sacrificial collar 202 .
- the trench 200 is preferably filled with resist 206 to a level below the upper edge 204 A of the oxide 204 .
- This may be achieved utilizing any of the known techniques, such as filling the trench 200 entirely with the resist 206 , and then recessing the resist 206 to the desired level. It is most preferred that the level of the resist 206 is between about 200-300 nm below the upper edge 204 A of the oxide 204 . Looking at it from another perspective, the level of the resist 206 is preferably 200-300 nm below the lower edge 202 A of the sacrificial collar 202 .
- a portion of the oxide 204 is preferably removed from the trench 200 . More particularly, the portion of the oxide 204 that extends from the resist 206 to the upper edge 204 A of the oxide 204 (or the lower edge 202 A of the sacrificial collar 202 ) is preferably removed.
- the resist 206 is preferably removed from the trench 202 utilizing any of the known techniques. Thereafter, the trench 200 is preferably etched in the area in which the oxide 204 was removed, namely, in the area between the lower edge 202 A of the sacrificial collar 202 and the oxide 204 (FIG. 4F). Preferably, this etching process produces a re-entrant bend 200 A in the sidewall of the trench 200 . While any of the appropriate etching processes may be employed, it is preferred that a number of cycles of targeted silicon etching utilizing a NH 4 OH/HF process is used. This advantageously etches the trench 200 to form the re-entrant bend 200 A in such a way that the consumption of the oxide 204 is less than about sixty angstroms.
- the sacrificial collar 202 is preferably removed, for example, utilizing an HF/EG process.
- a re-oxidation process is performed, at least in the lower portion of the trench 200 (e.g., proximate to the buried plate 110 .)
- a layer of silicon 208 is preferably formed in the trench 200 to a level below the re-entrant bend 200 A.
- the silicon layer 208 is formed by completely filling the trench 200 and then recessing the level of the silicon layer 208 to the desired level.
- an arsenic doped polysilicon material is preferred.
- a polysilicon divot fill sequence may then be performed.
- a collar 120 is preferably formed on the sidewall of the trench 200 , which collar 120 preferably covers the re-entrant bend 200 A (FIG. 4G) and at least a portion of the upper portion of the trench 200 .
- the collar 120 is preferably etched, and the array transistor 106 is preferably disposed in a vertical orientation above the trench capacitor 104 .
- the re-entrant bend 120 A of the collar 120 is advantageously disposed between the buried strap 116 and the buried plate 110 .
- the array FET 106 may be disposed in other orientations, such as in a planar (horizontal) orientation.
- the array FET may include a top oxide 150 disposed above the silicon layer 208 and adjacent to the buried strap 116 .
- a gate oxide 152 is disposed above the oxide 150 , which gate oxide 152 is disposed above the gate oxide 152 and is preferably formed from poly n-doped material.
- a source 156 (or drain) is disposed opposite to the buried strap and completes the major portions of the planar array FET.
Abstract
Description
- The present invention relates to a memory cell, and methods of forming same, where the memory cell includes a trench capacitor, an array FET, and a collar.
- Memory arrays, such as dynamic random access memories (DRAMs), employ memory cell structures, where each memory cell stores one bit of information. A typical storage cell includes a single array transistor, e.g., a field effect transistor (FET), and a capacitor coupled from one of the source and drain of the FET to ground. The gate of the FET is connected to a word line and the other of the drain and source of the FET is connected to a bit line.
- While the physical layout of a conventional memory cell may take on many forms, a popular configuration includes a trench capacitor and vertically aligned FET. An example of such a conventional structure of a
memory cell 10 is illustrated in FIG. 1. Thememory cell 10 includes atrench capacitor 14 and a vertically aligned FET 16. Thetrench capacitor 14 includes apolysilicon layer 18 and a buriedplate 20 at a lower portion of thelayer 18. The FET 16 includes agate portion 22, asource portion 24, adrain portion 26, and achannel 28. Thedrain portion 26 may include a buried strap coupled to an upper portion of thepolysilicon layer 18 of thetrench capacitor 14. Acollar 30 is disposed about the upper portion of thepolysilicon layer 18. - Although the structure of the
memory cell 10 of FIG. 1 is widely used in so-called trench capacitor design, it suffers from a significant disadvantage. In particular, a parasitic transistor is inherent in thememory cell 10 between the buriedstrap 26 and theburied plate 20. This parasitic transistor permits a significant electric field between the buriedstrap 26 and the buriedplate 20, which also permits undesirable leakage along the trench from the buriedplate 20 to the buriedstrap 26. Unfortunately, this undesirably affects the storage capabilities of thememory cell 10, including significantly reducing any charge stored on thetrench capacitor 14. - Accordingly, there are needs in the art for new memory cell configurations, and methods of making same, which significantly reduce or eliminate the parasitic transistor between a buried strap and a buried plate in a trench capacitor storage cell, thereby significantly reducing any leakage between the buried plate and the buried strap.
- In accordance with one or more aspects of the present invention, a memory cell includes a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.
- Preferably, the re-entrant bend of the collar includes a substantially sharp distal edge. Further, it is preferred that the re-entrant bend of the collar is between about 200-300 nm in length. The collar is preferably formed of an oxide.
- It is noted that the array FET may be vertically oriented or horizontally oriented.
- In accordance with one or more further aspects of the present invention, a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; etching the trench in an area substantially at an upper portion of the buried plate to form a re-entrant bend in a sidewall of the trench; and forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion of the trench.
- Preferably, step of forming the re-entrant bend includes using NH4OH/HF etching cycles such that oxide consumption is less than about 60 angstroms. Preferably, the re-entrant bend of the collar includes a substantially sharp distal edge.
- The method may further include forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge prior to forming the buried plate; forming an oxide in the trench after forming the buried plate that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; and removing a portion of the oxide from the trench that extends from the resist to the upper edge to form an exposed portion of the sidewall of the trench.
- It is preferred that the exposed portion of the sidewall is between about 200-300 nm in length. The sacrificial collar may be formed from one of nitride and a polysilicon. Preferably, the step of forming a re-entrant bend in the sidewall of the trench includes etching the trench in the exposed area of the sidewall between the oxide and the sacrificial collar.
- The method may further include forming a trench capacitor by filling at least a portion of the trench with a silicon layer having an upper portion and a lower portion; and forming an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, wherein the buried strap is in communication with the upper portion of the trench silicon layer and the collar is between the buried strap and the buried plate such that the re-entrant bend thereof is operable to decrease an electric field between the buried strap and the buried plate. The silicon layer of the trench capacitor may be formed of polysilicon.
- In accordance with one or more further aspects of the present invention, a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; forming an oxide in the trench that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; removing a portion of the oxide from the trench that extends from the resist to the upper edge; removing the resist from the trench; etching the trench in the area between the lower edge of the sacrificial collar and the oxide to form a re-entrant bend in a sidewall of the trench; forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion of the trench; filling at least a portion of the trench with a silicon layer having an upper portion and a lower portion; and forming an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, wherein the buried strap is in communication with the upper portion of the trench silicon layer and the collar is between the buried strap and the buried plate such that the re-entrant bend thereof is operable to decrease an electric field between the buried strap and the buried plate.
- Other aspects, features, advantages, etc. will become apparent to one skilled in the art in view of the description herein taken in conjunction with the accompanying drawings.
- For the purposes of illustrating the invention, there are shown in the drawings forms that are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and/or instrumentalities shown.
- FIG. 1 is a schematic cross-sectional view of a memory cell in accordance with the prior art;
- FIG. 2 is a schematic cross-sectional view of a memory cell in accordance with one or more aspects of the present invention;
- FIG. 3 is a schematic cross-sectional view of an alternative configuration of a memory cell employing one or more aspects of the present invention;
- FIGS.4A-K are schematic cross-sectional views illustrating a process of making a memory cell in accordance with one or more aspects of the present invention; and
- FIG. 5 is a schematic cross-sectional view of a further alternative configuration of a memory cell employing one or more aspects of the present invention.
- With reference to the drawings, wherein like numerals indicate like elements, there is shown in FIG. 2 a cross-sectional view of a
memory cell 100 in accordance with one or more aspects of the present invention. Thememory cell 100 includes atrench capacitor 104 and an array FET 106, disposed in a vertical orientation. Thetrench capacitor 104 includes atrench silicon layer 108 having an upper portion and a lower portion. Thetrench silicon layer 108 is preferably formed from a polysilicon material. Thetrench capacitor 104 preferably further includes a buriedplate 110 disposed about the lower portion of thetrench silicon layer 108. - The array FET106 preferably includes a
gate portion 112, asource portion 114, adrain portion 116, and achannel 118. Thedrain portion 116 preferably includes a buried strap that is in communication with the upper portion of thetrench silicon layer 108. It is noted that the vertically oriented array FET 106 is illustrated and described herein by way of example and not by way of limitation. Indeed, as discussed hereinbelow, a planar (horizontally oriented) array FET may also be employed without departing from the spirit and scope of the invention. Further, while a single sided buried strap is illustrated for discussion purposes, any of the known buried strap configurations may be employed without departing from the invention. - The
memory cell 100 preferably further includes acollar 120 disposed about at least the upper portion of thetrench silicon layer 108 and between the buriedstrap 116 and the buriedplate 110. Thecollar 120 preferably includes are-entrant bend 120A that is operable to decrease an electric field between the buriedstrap 116 and the buriedplate 110. Preferably, there-entrant bend 120A of thecollar 120 includes a substantially sharp distal edge that is radially spaced away from sidewalls of thetrench silicon layer 108. It is most preferred that there-entrant bend 120A has an overall length (as opposed to a path length) of between about 200-300 nm. As used herein, the overall length of there-entrant bend 120A is preferably measured in a substantially straight line from top to bottom as seen in the figures. The path length of there-entrant bend 120A is preferably measured along the path of the bend from top to bottom. Using these definitions, the path length of there-entrant bend 120A would be longer than the overall length thereof. Preferably, thecollar 120 is formed from an oxide, such as silicon dioxide. - With reference to FIG. 3, the
collar 120, including there-entrant bend 120A, may be employed in an alternativememory cell structure 102 having a bottle-etchedtrench capacitor 104A. There-entrant bend 120A is preferably disposed between the buriedstrap 116 and the buriedplate 110A such that any electric field between the buriedstrap 116 and the buriedplate 110A is reduced. - Advantageously, the
re-entrant bend 120A of thecollar 120, in accordance with the present invention, reduces the electric field between the buriedstrap 116 and the buriedplate 110, thereby reducing and/or eliminating the parasitic transistor between the buriedstrap 116 and the buriedplate 110. Further, leakage from the buriedplate 110 to the buriedstrap 116 is significantly reduced, thereby improving the storage characteristics of thetrench capacitor 104. A further advantage is obtained in that a thickness of thecollar 120 may be significantly reduced, therefore allowing a larger opening and a corresponding largertrench silicon layer 108, which results in a lower series resistance. - With reference to FIGS.4A-K, a method for forming the memory cell 100 (or 102) of the present invention will now be described. More particularly, with reference to FIG. 4A, a
trench 200 is etched into asubstrate 102, such as a P-type silicon substrate. Asacrificial collar 202 is preferably formed on an upper portion of thetrench 200, whichsacrificial collar 200 preferably extends down to alower edge 202A. Thesacrificial collar 202A may be formed utilizing any of the known techniques, such as by forming a nitride, or utilizing a polysilicon material. - The buried
plate 110 is preferably formed by diffusing a dopant into thesubstrate 102 proximate to the lower portion of thetrench 200. For example, an N-type dopant may be diffused into the P-type substrate 102 to form the buriedplate 110. (It is noted that, if a bottle-etchedtrench capacitor 104A is desired, a bottle-etch process would be performed prior to diffusing the dopant into thesubstrate 102.) - With reference to FIG. 4B, an
oxide 204 is preferably formed in thetrench 200 proximate to the buriedplate 110. Theoxide 204 may be formed utilizing any of the known techniques, such as a dry, rapid thermal oxidation (RTO) process. It is preferred that theoxide 204 is approximately sixty angstroms thick. As illustrated, theoxide 204 preferably extends up thetrench 200 to anupper edge 204A. It is most preferred that theupper edge 204A of theoxide 204 extends to thelower edge 202A of thesacrificial collar 202. - With reference to FIG. 4C, the
trench 200 is preferably filled with resist 206 to a level below theupper edge 204A of theoxide 204. This may be achieved utilizing any of the known techniques, such as filling thetrench 200 entirely with the resist 206, and then recessing the resist 206 to the desired level. It is most preferred that the level of the resist 206 is between about 200-300 nm below theupper edge 204A of theoxide 204. Looking at it from another perspective, the level of the resist 206 is preferably 200-300 nm below thelower edge 202A of thesacrificial collar 202. - With reference to FIG. 4D, a portion of the
oxide 204 is preferably removed from thetrench 200. More particularly, the portion of theoxide 204 that extends from the resist 206 to theupper edge 204A of the oxide 204 (or thelower edge 202A of the sacrificial collar 202) is preferably removed. - As best seen in FIG. 4E, the resist206 is preferably removed from the
trench 202 utilizing any of the known techniques. Thereafter, thetrench 200 is preferably etched in the area in which theoxide 204 was removed, namely, in the area between thelower edge 202A of thesacrificial collar 202 and the oxide 204 (FIG. 4F). Preferably, this etching process produces are-entrant bend 200A in the sidewall of thetrench 200. While any of the appropriate etching processes may be employed, it is preferred that a number of cycles of targeted silicon etching utilizing a NH4OH/HF process is used. This advantageously etches thetrench 200 to form there-entrant bend 200A in such a way that the consumption of theoxide 204 is less than about sixty angstroms. - With reference to FIG. 4G, the
sacrificial collar 202 is preferably removed, for example, utilizing an HF/EG process. - With reference to FIG. 4H, a re-oxidation process is performed, at least in the lower portion of the trench200 (e.g., proximate to the buried
plate 110.) A layer ofsilicon 208 is preferably formed in thetrench 200 to a level below there-entrant bend 200A. Although any of the known techniques may be utilized to achieve this result, it is preferred that thesilicon layer 208 is formed by completely filling thetrench 200 and then recessing the level of thesilicon layer 208 to the desired level. Although any of the suitable silicon materials may be employed, an arsenic doped polysilicon material is preferred. A polysilicon divot fill sequence may then be performed. Next, acollar 120 is preferably formed on the sidewall of thetrench 200, whichcollar 120 preferably covers there-entrant bend 200A (FIG. 4G) and at least a portion of the upper portion of thetrench 200. - As best seen in FIGS.41-K, the
collar 120 is preferably etched, and thearray transistor 106 is preferably disposed in a vertical orientation above thetrench capacitor 104. As discussed above, there-entrant bend 120A of thecollar 120 is advantageously disposed between the buriedstrap 116 and the buriedplate 110. - As discussed above, the
array FET 106 may be disposed in other orientations, such as in a planar (horizontal) orientation. As best seen in FIG. 5, the array FET may include atop oxide 150 disposed above thesilicon layer 208 and adjacent to the buriedstrap 116. Agate oxide 152 is disposed above theoxide 150, whichgate oxide 152 is disposed above thegate oxide 152 and is preferably formed from poly n-doped material. A source 156 (or drain) is disposed opposite to the buried strap and completes the major portions of the planar array FET. - Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (22)
Priority Applications (3)
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US10/283,483 US6759292B2 (en) | 2002-10-30 | 2002-10-30 | Method for fabricating a trench capacitor |
JP2003339550A JP4790977B2 (en) | 2002-10-30 | 2003-09-30 | Method for forming memory cell |
DE10350703A DE10350703B4 (en) | 2002-10-30 | 2003-10-30 | Method for forming a memory cell |
Applications Claiming Priority (1)
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US10/283,483 US6759292B2 (en) | 2002-10-30 | 2002-10-30 | Method for fabricating a trench capacitor |
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US20040084708A1 true US20040084708A1 (en) | 2004-05-06 |
US6759292B2 US6759292B2 (en) | 2004-07-06 |
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US10/283,483 Expired - Lifetime US6759292B2 (en) | 2002-10-30 | 2002-10-30 | Method for fabricating a trench capacitor |
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US (1) | US6759292B2 (en) |
JP (1) | JP4790977B2 (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040063277A1 (en) * | 2002-09-27 | 2004-04-01 | International Business Machines Corporation | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric |
US7265398B1 (en) * | 2003-05-15 | 2007-09-04 | Qspeed Semiconductor Inc. | Method and structure for composite trench fill |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10234735A1 (en) * | 2002-07-30 | 2004-02-12 | Infineon Technologies Ag | Structurization of process area inclined or perpendicular to substrate surface, used in trench in semiconductor, especially in capacitor production, involves depositing liner of uniform thickness from precursors only in upper part |
US7723201B2 (en) * | 2006-01-09 | 2010-05-25 | International Business Machines Corporation | Structure and method for making on-chip capacitors with various capacitances |
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US5482883A (en) * | 1993-12-01 | 1996-01-09 | International Business Machines Corporation | Method for fabricating low leakage substrate plate trench DRAM cells and devices formed thereby |
US6518616B2 (en) * | 2001-04-18 | 2003-02-11 | International Business Machines Corporation | Vertical gate top engineering for improved GC and CB process windows |
US6599798B2 (en) * | 2001-07-24 | 2003-07-29 | Infineon Technologies Ag | Method of preparing buried LOCOS collar in trench DRAMS |
US6605838B1 (en) * | 2002-09-30 | 2003-08-12 | International Business Machines Corporation | Process flow for thick isolation collar with reduced length |
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JPS63232459A (en) * | 1987-03-20 | 1988-09-28 | Nec Corp | Mos memory semiconductor device and manufacture thereof |
JPH1093046A (en) * | 1996-09-17 | 1998-04-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
JP3450682B2 (en) * | 1997-12-03 | 2003-09-29 | 株式会社東芝 | Semiconductor storage device and method of manufacturing the same |
US6373086B1 (en) * | 2000-06-29 | 2002-04-16 | International Business Machines Corporation | Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same |
JP4084005B2 (en) * | 2001-06-26 | 2008-04-30 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
-
2002
- 2002-10-30 US US10/283,483 patent/US6759292B2/en not_active Expired - Lifetime
-
2003
- 2003-09-30 JP JP2003339550A patent/JP4790977B2/en not_active Expired - Fee Related
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5482883A (en) * | 1993-12-01 | 1996-01-09 | International Business Machines Corporation | Method for fabricating low leakage substrate plate trench DRAM cells and devices formed thereby |
US6518616B2 (en) * | 2001-04-18 | 2003-02-11 | International Business Machines Corporation | Vertical gate top engineering for improved GC and CB process windows |
US6599798B2 (en) * | 2001-07-24 | 2003-07-29 | Infineon Technologies Ag | Method of preparing buried LOCOS collar in trench DRAMS |
US6605838B1 (en) * | 2002-09-30 | 2003-08-12 | International Business Machines Corporation | Process flow for thick isolation collar with reduced length |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040063277A1 (en) * | 2002-09-27 | 2004-04-01 | International Business Machines Corporation | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric |
US6936512B2 (en) | 2002-09-27 | 2005-08-30 | International Business Machines Corporation | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric |
US7265398B1 (en) * | 2003-05-15 | 2007-09-04 | Qspeed Semiconductor Inc. | Method and structure for composite trench fill |
Also Published As
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JP2004153250A (en) | 2004-05-27 |
JP4790977B2 (en) | 2011-10-12 |
US6759292B2 (en) | 2004-07-06 |
DE10350703A1 (en) | 2004-05-27 |
DE10350703B4 (en) | 2009-04-02 |
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