US20040046598A1 - I/o pad overvoltage protection circuitry - Google Patents

I/o pad overvoltage protection circuitry Download PDF

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US20040046598A1
US20040046598A1 US10/241,115 US24111502A US2004046598A1 US 20040046598 A1 US20040046598 A1 US 20040046598A1 US 24111502 A US24111502 A US 24111502A US 2004046598 A1 US2004046598 A1 US 2004046598A1
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Prior art keywords
transistor
pad
transmission gate
coupled
circuit
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US10/241,115
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US6700431B1 (en
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Bahram Fotouhi
Bahman Farzan
Saied Rafati
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Exar Corp
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Exar Corp
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Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.), EXAR CORPORATION, MAXLINEAR, INC.
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Definitions

  • the present invention relates generally to I/O circuits, and in particular to transmission gates with over-voltage protection.
  • the transmission gate is an integrated circuit which connects between an internal, core circuit and an I/O pad.
  • the transmission gate circuit acts as a low-impedance connection to the pad under normal conditions where the supply voltage Vdd is greater than the voltage at the pad, which is also greater than zero or ground.
  • Vdd the supply voltage
  • the I/O pad is subject to voltage spikes, or acts as an input, it is possible that its voltage may exceed that of the supply voltage.
  • a chip designed with a 3.3 volt power supply may be connected to another chip which uses 5-volt levels.
  • FIG. 1 illustrates a prior art transmission gate circuit.
  • NMOS transmission gate transistor M 10 and PMOS transmission gate transistor M 9 connect core circuitry 10 to an I/O pad 12 .
  • the P-well 14 of transistor M 10 is connected to ground, while the N-well 16 of transistor M 9 is connected to the power supply, V dd .
  • V pad which is greater than zero
  • the transmission gate is on. If the voltage at the pad should exceed the supply voltage by more than a threshold amount, the P-channel transistor M 10 is still on, effectively connecting pad terminal 12 to the internal core circuit. Thus, this circuit does not isolate the internal circuitry from the I/O pad when the pad voltage exceeds the supply voltage. If the voltage on the pad is greater than the supply voltage, the intrinsic PN diode between the source and the bulk (P-well 16 ) of transistor M 9 will turn on, shorting pad 12 to V dd . Alternately, the channel of PMOS transistor M 9 can simply turn on due to negative gate-to-source potential with the gate at zero and the source at a positive potential.
  • the present invention provides a protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad.
  • a biasing transistor is coupled to a gate of the NMOS transmission gate transistor to turn it on during normal operation.
  • a protection circuit will turn off the NMOS transmission gate transistor when the voltage at the pad exceeds the supply voltage by more than a threshold amount.
  • This protection circuit includes a first protection transistor coupled between the gate of the biasing transistor and the pad to turn the biasing transistor off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.
  • one or more NMOS protection transistors are coupled between the gate of the PMOS transmission gate transistor and ground, with the gate of the PMOS transmission gate transistor being connected to the first protection transistor.
  • an N-well biasing circuit is provided with a PMOS transistor coupled between the N-well and the pad, with the gate coupled to the supply voltage.
  • a second PMOS transistor is connected between the supply voltage V dd and the N-well, with its gate connected to the first protection transistor.
  • a second NMOS transmission gate transistor is added to limit the voltage drop across the first NMOS transmission gate transistor.
  • FIG. 1 is a diagram of a prior art transmission gate circuit.
  • FIG. 2 is a circuit diagram of one embodiment of the invention.
  • FIG. 2 is a circuit diagram of an embodiment of the invention.
  • transmission gates M 9 and M 10 connect between core circuitry 10 and I/O pad 12 as in FIG. 1.
  • a second NMOS transmission gate transistor M 3 is added in one embodiment of the invention, to limit the voltage drop across transistor M 10 during an over-voltage condition.
  • NMOS transmission gate transistor M 10 is controlled by a signal GATEN, which is connected between a transistor M 1 and a resistor R 1 .
  • R 1 connects to ground, while M 1 connects to the supply voltage, Vdd.
  • the gate of PMOS transmission gate transistor M 9 is controlled by a signal OVERVOLT, which is connected to a protection transistor M 6 .
  • the protection transistor M 6 is connected between the output pad 12 and the OVERVOLT line 19 , with its gate connected to the supply voltage, Vdd.
  • Transistor M 6 is normally off, but turns on when the pad voltage 12 exceeds Vdd.
  • a second transistor M 3 may be added, with its gate connected to the supply voltage Vdd. This is particularly useful for small geometry transistors.
  • Transistors M 7 and M 2 bias the N-well of the PMOS transistors. This N-well is indicated by BULK line 20 . Under an overvoltage condition, transistor M 7 will turn on, pulling the N-well BULK line 20 to the pad voltage. M 2 maintains the N-well at Vdd during normal operation.
  • Transistors M 4 and M 5 connect the gate of PMOS transmission gate transistor M 9 to ground.
  • node 18 OVERVOLT
  • OVERVOLT node 18
  • N-channel transistors M 3 and M 10 reduces their gate-to-source and drain-to-source voltages, protecting them from the excess voltage at the pad and thus preventing gate rupture.
  • Devices M 4 and M 5 are long-channel devices, that together with M 6 form a ratioed logic when V PAD >V dd >0, and allow M 6 to pull up node OVERVOLT 18 to the pad voltage. Under normal conditions of V pad ⁇ V dd , OVERVOLT 18 is pulled to ground, turning M 9 on. M 1 is also turned on, pulling the gate of M 10 to Vdd and turning it on. This connects the core to the pad under normal conditions.
  • transistor M 3 is optional, and could be left out if transistor M 10 is of a sufficient size to handle the overvoltage.
  • the protection circuitry of the invention could be implemented at the core circuit level, rather than at the transmission gate. However, by implementing at the transmission gate, only a single circuit is needed for each pad. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gates of the biasing transistors and the pad to turn the biasing transistors off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • This application is related to co-pending application “CMOS Transmission Gate with High Impedance at Power-Off”, application Ser. No. 10/119,101, filed Apr. 8, 2002, and “Input Termination with High Impedance at Power Off”, application Ser. No. 10/093,227, filed Mar. 5, 2002.[0001]
    • BACKGROUND OF THE INVENTION
  • The present invention relates generally to I/O circuits, and in particular to transmission gates with over-voltage protection. [0002]
  • The transmission gate is an integrated circuit which connects between an internal, core circuit and an I/O pad. The transmission gate circuit acts as a low-impedance connection to the pad under normal conditions where the supply voltage Vdd is greater than the voltage at the pad, which is also greater than zero or ground. However, when the I/O pad is subject to voltage spikes, or acts as an input, it is possible that its voltage may exceed that of the supply voltage. For example, a chip designed with a 3.3 volt power supply may be connected to another chip which uses 5-volt levels. [0003]
  • FIG. 1 illustrates a prior art transmission gate circuit. NMOS transmission gate transistor M[0004] 10 and PMOS transmission gate transistor M9 connect core circuitry 10 to an I/O pad 12. The P-well 14 of transistor M10 is connected to ground, while the N-well 16 of transistor M9 is connected to the power supply, Vdd.
  • During normal conditions, when V[0005] dd is greater than the voltage at the pad, Vpad, which is greater than zero, the transmission gate is on. If the voltage at the pad should exceed the supply voltage by more than a threshold amount, the P-channel transistor M10 is still on, effectively connecting pad terminal 12 to the internal core circuit. Thus, this circuit does not isolate the internal circuitry from the I/O pad when the pad voltage exceeds the supply voltage. If the voltage on the pad is greater than the supply voltage, the intrinsic PN diode between the source and the bulk (P-well 16) of transistor M9 will turn on, shorting pad 12 to Vdd. Alternately, the channel of PMOS transistor M9 can simply turn on due to negative gate-to-source potential with the gate at zero and the source at a positive potential.
    • BRIEF SUMMARY OF THE INVENTION
  • The present invention provides a protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. A biasing transistor is coupled to a gate of the NMOS transmission gate transistor to turn it on during normal operation. A protection circuit will turn off the NMOS transmission gate transistor when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gate of the biasing transistor and the pad to turn the biasing transistor off when the voltage on the pad exceeds the supply voltage by more than the threshold amount. [0006]
  • In one embodiment, one or more NMOS protection transistors are coupled between the gate of the PMOS transmission gate transistor and ground, with the gate of the PMOS transmission gate transistor being connected to the first protection transistor. In addition, an N-well biasing circuit is provided with a PMOS transistor coupled between the N-well and the pad, with the gate coupled to the supply voltage. Additionally, a second PMOS transistor is connected between the supply voltage V[0007] dd and the N-well, with its gate connected to the first protection transistor.
  • In one embodiment, a second NMOS transmission gate transistor is added to limit the voltage drop across the first NMOS transmission gate transistor. [0008]
  • For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.[0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram of a prior art transmission gate circuit. [0010]
  • FIG. 2 is a circuit diagram of one embodiment of the invention.[0011]
    • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 2 is a circuit diagram of an embodiment of the invention. As can be seen, transmission gates M[0012] 9 and M10 connect between core circuitry 10 and I/O pad 12 as in FIG. 1. A second NMOS transmission gate transistor M3 is added in one embodiment of the invention, to limit the voltage drop across transistor M10 during an over-voltage condition.
  • The gate of NMOS transmission gate transistor M[0013] 10 is controlled by a signal GATEN, which is connected between a transistor M1 and a resistor R1. R1 connects to ground, while M1 connects to the supply voltage, Vdd. The gate of PMOS transmission gate transistor M9 is controlled by a signal OVERVOLT, which is connected to a protection transistor M6. The protection transistor M6 is connected between the output pad 12 and the OVERVOLT line 19, with its gate connected to the supply voltage, Vdd. Transistor M6 is normally off, but turns on when the pad voltage 12 exceeds Vdd. This will cause it to turn on, connecting the OVERVOLT line 18 to the pad 12, turning off transistor M1, thus allowing resistor R1 to pull the gate of transistor M10 to ground. This ensures that transistor M10 is shut off, causing a high impedance between pad 12 and core circuitry 10. In order to limit this voltage drop so that it is not all across transistor M10, a second transistor M3 may be added, with its gate connected to the supply voltage Vdd. This is particularly useful for small geometry transistors.
  • Transistors M[0014] 7 and M2 bias the N-well of the PMOS transistors. This N-well is indicated by BULK line 20. Under an overvoltage condition, transistor M7 will turn on, pulling the N-well BULK line 20 to the pad voltage. M2 maintains the N-well at Vdd during normal operation.
  • Transistors M[0015] 4 and M5 connect the gate of PMOS transmission gate transistor M9 to ground. When the pad voltage exceeds the supply voltage, node 18 (OVERVOLT) is connected to the pad voltage, ensuring that the PMOS transmission gate transistor M9 is also turned off, thus isolating the core.
  • The cascode connection of N-channel transistors M[0016] 3 and M10 reduces their gate-to-source and drain-to-source voltages, protecting them from the excess voltage at the pad and thus preventing gate rupture. Devices M4 and M5 are long-channel devices, that together with M6 form a ratioed logic when VPAD>Vdd>0, and allow M6 to pull up node OVERVOLT 18 to the pad voltage. Under normal conditions of Vpad<Vdd, OVERVOLT 18 is pulled to ground, turning M9 on. M1 is also turned on, pulling the gate of M10 to Vdd and turning it on. This connects the core to the pad under normal conditions.
  • As will be understood by those with skill in the art, the present invention may be embodied in other specific forms without departing from the essential characteristics thereof. For example, transistor M[0017] 3 is optional, and could be left out if transistor M10 is of a sufficient size to handle the overvoltage. Alternately, the protection circuitry of the invention could be implemented at the core circuit level, rather than at the transmission gate. However, by implementing at the transmission gate, only a single circuit is needed for each pad. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.

Claims (11)

What is claimed is:
1. A transmission gate circuit comprising:
a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad;
a biasing transistor coupled to a gate of said NMOS transistor to turn said NMOS transmission gate transistor on during normal operation; and
a protection circuit configured to turn off said NMOS transmission gate transistor when a voltage on said pad exceeds a supply voltage by more than a threshold amount, said protection circuit including
a first protection transistor coupled between a gate of said biasing transistor and said pad to turn said biasing transistor off when a voltage on said pad exceeds a supply voltage by more than a threshold amount.
2. The circuit of claim 1 wherein said protection circuit further comprises:
at least one NMOS protection transistor coupled between a gate of said PMOS transmission gate transistor and ground, wherein a gate of said PMOS transmission gate transistor is coupled to said first protection transistor.
3. The circuit of claim 1 further comprising:
a second NMOS transmission gate transistor coupled between said core circuit and said pad, and having a gate coupled to said supply voltage.
4. The circuit of claim 1 further comprising:
an n-well biasing circuit, including at least one n-well biasing PMOS transistor coupled between said n-well and said pad, and having a gate coupled to said supply voltage.
5. A transmission gate circuit comprising:
a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad;
a biasing transistor coupled to a gate of said NMOS transistor to turn said NMOS transmission gate transistor on during normal operation; and
a protection circuit configured to turn off said NMOS transmission gate transistor when a voltage on said pad exceeds a supply voltage by more than a threshold amount, said protection circuit including
a first protection transistor coupled between a gate of said biasing transistor and said pad to turn said biasing transistor off when a voltage on said pad exceeds a supply voltage by more than a threshold amount;
at least one NMOS protection transistor coupled between a gate of said PMOS transmission gate transistor and ground, wherein a gate of said PMOS transmission gate transistor is coupled to said first protection transistor; and
an n-well biasing circuit, including at least one n-well biasing PMOS transistor coupled between said n-well and said pad, and having a gate coupled to said supply voltage.
6. The circuit of claim 5 wherein said n-well biasing circuit further comprises:
a second n-well biasing PMOS transistor coupled between said supply voltage and said n-well, and having a gate coupled to said first protection transistor, such that said first protection transistor will turn said second n-well biasing PMOS transistor off when a voltage on said pad exceeds said supply voltage by more than said threshold amount.
7. The circuit of claim 5 further comprising:
a resistor coupled between said biasing transistor and ground.
8. The circuit of claim 5 further comprising:
a second NMOS transmission gate transistor coupled between said core circuit and said pad, and having a gate coupled to said supply voltage.
9. A method for protecting against overvoltage on a pad in a transmission gate circuit having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad, comprising:
turning said NMOS transmission gate transistor on during normal operation; and
turning off said NMOS transmission gate transistor when a voltage on said pad exceeds a supply voltage by more than a threshold amount, using a first protection transistor coupled between a gate of a biasing transistor for said NMOS transmission gate transistor and said pad to turn said biasing transistor off when a voltage on said pad exceeds a supply voltage by more than a threshold amount.
10. The method of claim 9 further comprising:
biasing an n-well of said PMOS transmission gate transistor using at least one n-well biasing PMOS transistor coupled between said n-well and said pad, and having a gate coupled to said supply voltage.
11. The method of claim 9 further comprising:
limiting a voltage drop across said PMOS transmission gate transistor with a second PMOS transmission gate transistor coupled between said core circuit and said pad.
US10/241,115 2002-09-10 2002-09-10 I/O pad overvoltage protection circuitry Expired - Lifetime US6700431B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070152722A1 (en) * 2003-04-09 2007-07-05 Yasuhide Shimizu Comparator, Sample-and-Hold Circuit, Differential Amplifier, Two-Stage Amplifier, and Analog-to-Digital Converter
US20100085080A1 (en) * 2007-03-28 2010-04-08 Nxp, B.V. Electronic device with a high voltage tolerant unit
EP2586127A1 (en) * 2010-06-28 2013-05-01 Freescale Semiconductor, Inc. Transmission gate circuitry for high voltage terminal

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704431B1 (en) * 1998-09-04 2004-03-09 Nippon Telegraph And Telephone Corporation Method and apparatus for digital watermarking
US7012794B2 (en) * 2003-01-17 2006-03-14 Exar Corporation CMOS analog switch with auto over-voltage turn-off
ATE556487T1 (en) * 2003-10-23 2012-05-15 Nxp Bv SWITCH
US7855862B1 (en) * 2006-03-28 2010-12-21 Cypress Semiconductor Corporation Electrostatic discharge (ESD) circuit and method that includes P-channel device in signal path
US8154270B2 (en) * 2009-02-13 2012-04-10 Standard Microsystems Corporation Power-up control for very low-power systems
TWI343706B (en) * 2009-07-13 2011-06-11 Ind Tech Res Inst Isolation circuit
US10601216B2 (en) 2016-12-15 2020-03-24 International Business Machines Corporation Distributed environment analog multiplexor with high-voltage protection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563540A (en) * 1993-09-17 1996-10-08 International Business Machines Corporation Electronic switch having programmable means to reduce noise coupling
US5617055A (en) * 1994-07-29 1997-04-01 Sgs-Thomson Microelectronics S.R.L. Electronic switch having reduced body effect

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19628270C2 (en) 1996-07-12 2000-06-21 Ericsson Telefon Ab L M Interference-free interface circuit
US5914627A (en) 1997-10-09 1999-06-22 Exar Corporation Isolation circuit for I/O terminal
US6037828A (en) 1997-10-09 2000-03-14 Exar Corporation Transmission line driver with high output impedance at power off
US5926056A (en) 1998-01-12 1999-07-20 Lucent Technologies Inc. Voltage tolerant output buffer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563540A (en) * 1993-09-17 1996-10-08 International Business Machines Corporation Electronic switch having programmable means to reduce noise coupling
US5617055A (en) * 1994-07-29 1997-04-01 Sgs-Thomson Microelectronics S.R.L. Electronic switch having reduced body effect

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070152722A1 (en) * 2003-04-09 2007-07-05 Yasuhide Shimizu Comparator, Sample-and-Hold Circuit, Differential Amplifier, Two-Stage Amplifier, and Analog-to-Digital Converter
US8120388B2 (en) * 2003-04-09 2012-02-21 Sony Corporation Comparator, sample-and-hold circuit, differential amplifier, two-stage amplifier, and analog-to-digital converter
US20100085080A1 (en) * 2007-03-28 2010-04-08 Nxp, B.V. Electronic device with a high voltage tolerant unit
US8330491B2 (en) * 2007-03-28 2012-12-11 Synopsys, Inc. Electronic device with a high voltage tolerant unit
EP2586127A1 (en) * 2010-06-28 2013-05-01 Freescale Semiconductor, Inc. Transmission gate circuitry for high voltage terminal
EP2586127A4 (en) * 2010-06-28 2014-02-12 Freescale Semiconductor Inc Transmission gate circuitry for high voltage terminal

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