US20030193363A1 - Sequencing circuit for applying a highest voltage source to a chip - Google Patents
Sequencing circuit for applying a highest voltage source to a chip Download PDFInfo
- Publication number
- US20030193363A1 US20030193363A1 US10/122,994 US12299402A US2003193363A1 US 20030193363 A1 US20030193363 A1 US 20030193363A1 US 12299402 A US12299402 A US 12299402A US 2003193363 A1 US2003193363 A1 US 2003193363A1
- Authority
- US
- United States
- Prior art keywords
- power supply
- transistor
- chip
- voltage
- system power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/08—Three-wire systems; Systems having more than three wires
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/08—Three-wire systems; Systems having more than three wires
- H02J1/082—Plural DC voltage, e.g. DC supply voltage with at least two different DC voltage levels
Definitions
- the present invention relates generally to power supply circuitry and more particularly, relates to a sequencing circuit for applying a highest voltage source to a chip.
- one chip may have a voltage power rail Vdd connected to a 5 volt power supply and include components and input/output (I/O) that use a 3.3 volt power supply.
- Vdd voltage power rail
- I/O input/output
- a system power supply does not instantly provide the correct supply voltages during startup or power down of an electronic system, such as a computer system.
- Known power supplies have a startup delay when the system is powered on and also a bring down delay when the when the system is powered off.
- This sequencing problem required that the voltage power rail Vdd be maintained as the highest voltage to the chip during power up and power down of the system.
- a second technique for accommodating this sequencing problem uses in line switches, such as field effect transistors (FETs), to switch the 3.3 volt supply on after the +5 volt supply is powered up. Then the in line switches or FETs switch the 3.3 volt supply off before the +5 volt supply is powered down.
- FETs field effect transistors
- This method requires that all chips running off the 3.3 volt supply that are coupled to I/O of the system chips also need to be switched, so that the I/O voltages are also controlled.
- This method would require a very large switch; for example, a switch rated for 20 Amps or more may be required. It also would sequence other chips in the system in a way that may cause other problems.
- a principal object of the present invention is to provide a sequencing circuit for applying a highest one of system voltage supplies to a chip.
- Other important objects of the present invention are to provide such sequencing circuit for applying a highest one of system voltage supplies to a chip substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
- a sequencing circuit and sequencing method are provided for applying a highest applying a highest voltage of first and second system supplies to a chip.
- the sequencing circuit includes a first transistor coupled between the first system power supply and a power supply input to the chip and a second transistor coupled between the second system power supply and a power supply input to the chip.
- the sequencing circuit includes a comparator for sensing a highest voltage of the first and second system power supplies. The first transistor and second transistor are coupled to an output of the comparator. When the comparator senses that the first power supply voltage is higher than the second power supply voltage, then the first transistor is turned on and couples the first power supply voltage to the power supply input to the chip. Alternately, when the comparator senses that the second power supply voltage is higher than the first power supply voltage, then the second transistor is turned on and couples the second power supply voltage to the power supply input to the chip.
- the single drawing figure is a schematic and block diagram representation of a sequencing circuit in accordance with the preferred embodiment.
- Sequencing circuit 100 satisfies the requirement that a chip power supply input labeled Vdd is the highest voltage to a chip 120 at any time. Sequencing circuit 100 connects the chip power supply input Vdd to the highest of the two voltages that the chip 120 receives or has on a chip input/output (I/O).
- I/O chip input/output
- Sequencing circuit 100 includes a first transistor 102 coupled between a first system power supply labeled VOLTAGE SUPPLY 1 (3.3V) and the chip power supply input VDD to the chip 120 and a second transistor 104 coupled between a second system power supply labeled VOLTAGE SUPPLY 2 (5V) and the power supply input VDD to the chip 120 .
- the first transistor 102 and second transistor 104 of the preferred embodiment are field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs).
- Sequencing circuit 100 includes a comparator 106 for sensing a highest voltage of the first and second system power supplies.
- a first biasing resistor 108 is coupled between a non-inverting input of the comparator 106 and the first system power supply VOLTAGE SUPPLY 1.
- a second biasing resistor 110 is coupled between an inverting input of the comparator 106 and the second system power supply VOLTAGE SUPPLY 2.
- Sequencing circuit 100 includes two bias voltages labeled +5 VCS and +12 VCS.
- a third biasing resistor 112 is coupled between the reference or bias voltage source +5 VCS and an output of the comparator 106 .
- the first transistor 102 and second transistor 104 have a gate input operatively controlled by the comparator 106 .
- An output of the comparator 106 is applied to the gate of the first transistor 102 .
- a third transistor 114 includes a gate connected to the output of the comparator 106 .
- the source and drain of the third transistor 114 are connected between a biasing resistor 116 connected to the reference supply 12 VCS and the second system power supply VOLTAGE SUPPLY 2.
- the second transistor 104 has its gate input operatively controlled by the comparator 106 via the third transistor 114 .
- the bias voltage source +5 VCS coupled to the comparator 106 and the bias voltage source +12 VCS coupled to the third transistor are powered up before the first system power supply VOLTAGE SUPPLY 1 and the second system power supply VOLTAGE SUPPLY 2 are powered up.
- the bias voltages +5 VCS and +12 VCS remain powered up until the first system power supply and the second system power supply are powered down to zero volts.
- the first transistor 102 is turned on and couples the first power supply voltage VOLTAGE SUPPLY 1 (3.3V) to the power supply input VDD to the chip 120 .
- the second transistor 104 is turned on and couples the second power supply voltage VOLTAGE SUPPLY 2 (5V) to the power supply input to the chip.
- the first transistor 102 , second transistor 104 and third transistor 114 are P-channel MOSFETs; however it should be understood that other switching devices, such as N-channel MOSFETs or N-channel or P-channel bipolar transistors could be employed.
- the current draw on the power supply input VDD to the chip 120 can be, for example, about 100 ma, so that very small FETs 102 and 104 advantageously are used in the sequencing circuit 100 .
- Sequencing circuit 100 only changes the sequencing to the particular chips 120 that require such sequencing, rather than all chips of an overall system of prior art arrangements.
- Sequencing circuit 100 is used with chips 120 that require the supply input VDD to be the highest voltage applied to the chip and requires reduced board size as compared to prior art arrangements. Sequencing circuit 100 has no effect on the other chips in a system.
Abstract
Description
- The present invention relates generally to power supply circuitry and more particularly, relates to a sequencing circuit for applying a highest voltage source to a chip.
- In known electronic systems, various DC voltage levels often are required that may be provided by multiple different DC supplies. For example, one chip may have a voltage power rail Vdd connected to a 5 volt power supply and include components and input/output (I/O) that use a 3.3 volt power supply. Typically, a system power supply does not instantly provide the correct supply voltages during startup or power down of an electronic system, such as a computer system. Known power supplies have a startup delay when the system is powered on and also a bring down delay when the when the system is powered off.
- A sequencing problem exists with some chips included in such known electronic systems. For example, one chip has a voltage power rail Vdd connected to the +5 volts of the system, and this chip also used 3.3 volts and had I/O pins that were also pulled up or wired to other chips that also used the 3.3 volt supply. This chip would latch up if at any time the voltage power rail Vdd is less than any other voltage that was used by this chip. This sequencing problem required that the voltage power rail Vdd be maintained as the highest voltage to the chip during power up and power down of the system.
- One way that this sequencing problem has been dealt with in the past is to require the power systems to sequence up the +5 volt supply of the system first and then to power up the 3.3 volt supply next. Then the opposite sequence has been required during power down with the 3.3 volt supply powered down first, then the +5 volts of the system is powered down. This required sequencing of multiple power supplies adds complexity and cost to the power systems and this sequencing of the power supplies may result in other problems with other chips in the system.
- A second technique for accommodating this sequencing problem uses in line switches, such as field effect transistors (FETs), to switch the 3.3 volt supply on after the +5 volt supply is powered up. Then the in line switches or FETs switch the 3.3 volt supply off before the +5 volt supply is powered down. This method requires that all chips running off the 3.3 volt supply that are coupled to I/O of the system chips also need to be switched, so that the I/O voltages are also controlled. This method would require a very large switch; for example, a switch rated for 20 Amps or more may be required. It also would sequence other chips in the system in a way that may cause other problems.
- A principal object of the present invention is to provide a sequencing circuit for applying a highest one of system voltage supplies to a chip. Other important objects of the present invention are to provide such sequencing circuit for applying a highest one of system voltage supplies to a chip substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
- In brief, a sequencing circuit and sequencing method are provided for applying a highest applying a highest voltage of first and second system supplies to a chip. The sequencing circuit includes a first transistor coupled between the first system power supply and a power supply input to the chip and a second transistor coupled between the second system power supply and a power supply input to the chip. The sequencing circuit includes a comparator for sensing a highest voltage of the first and second system power supplies. The first transistor and second transistor are coupled to an output of the comparator. When the comparator senses that the first power supply voltage is higher than the second power supply voltage, then the first transistor is turned on and couples the first power supply voltage to the power supply input to the chip. Alternately, when the comparator senses that the second power supply voltage is higher than the first power supply voltage, then the second transistor is turned on and couples the second power supply voltage to the power supply input to the chip.
- The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
- The single drawing figure is a schematic and block diagram representation of a sequencing circuit in accordance with the preferred embodiment.
- Having reference now to the drawings, there is shown an exemplary sequencing circuit in accordance with the preferred embodiment generally designated by the
reference character 100.Sequencing circuit 100 satisfies the requirement that a chip power supply input labeled Vdd is the highest voltage to achip 120 at any time.Sequencing circuit 100 connects the chip power supply input Vdd to the highest of the two voltages that thechip 120 receives or has on a chip input/output (I/O). -
Sequencing circuit 100 includes a first transistor 102 coupled between a first system power supply labeled VOLTAGE SUPPLY 1 (3.3V) and the chip power supply input VDD to thechip 120 and asecond transistor 104 coupled between a second system power supply labeled VOLTAGE SUPPLY 2 (5V) and the power supply input VDD to thechip 120. The first transistor 102 andsecond transistor 104 of the preferred embodiment are field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs). -
Sequencing circuit 100 includes acomparator 106 for sensing a highest voltage of the first and second system power supplies. Afirst biasing resistor 108 is coupled between a non-inverting input of thecomparator 106 and the first system power supply VOLTAGE SUPPLY 1. Asecond biasing resistor 110 is coupled between an inverting input of thecomparator 106 and the second system power supply VOLTAGE SUPPLY 2.Sequencing circuit 100 includes two bias voltages labeled +5 VCS and +12 VCS. Athird biasing resistor 112 is coupled between the reference or bias voltage source +5 VCS and an output of thecomparator 106. The first transistor 102 andsecond transistor 104 have a gate input operatively controlled by thecomparator 106. An output of thecomparator 106 is applied to the gate of the first transistor 102. Athird transistor 114 includes a gate connected to the output of thecomparator 106. The source and drain of thethird transistor 114 are connected between abiasing resistor 116 connected to the reference supply 12 VCS and the second system power supply VOLTAGE SUPPLY 2. Thesecond transistor 104 has its gate input operatively controlled by thecomparator 106 via thethird transistor 114. - The bias voltage source +5 VCS coupled to the
comparator 106 and the bias voltage source +12 VCS coupled to the third transistor are powered up before the first system power supply VOLTAGE SUPPLY 1 and the second system power supply VOLTAGE SUPPLY 2 are powered up. The bias voltages +5 VCS and +12 VCS remain powered up until the first system power supply and the second system power supply are powered down to zero volts. - In operation, when the
comparator 106 senses that the first power supply voltage is higher than the second power supply voltage, the first transistor 102 is turned on and couples the first power supply voltage VOLTAGE SUPPLY 1 (3.3V) to the power supply input VDD to thechip 120. Alternately, when the comparator 102 senses that the second power supply voltage is higher than the first power supply voltage, thesecond transistor 104 is turned on and couples the second power supply voltage VOLTAGE SUPPLY 2 (5V) to the power supply input to the chip. - As shown in the drawing, the first transistor102,
second transistor 104 andthird transistor 114 are P-channel MOSFETs; however it should be understood that other switching devices, such as N-channel MOSFETs or N-channel or P-channel bipolar transistors could be employed. - For a particular application of
sequencing circuit 100, the current draw on the power supply input VDD to thechip 120 can be, for example, about 100 ma, so that verysmall FETs 102 and 104 advantageously are used in thesequencing circuit 100.Sequencing circuit 100 only changes the sequencing to theparticular chips 120 that require such sequencing, rather than all chips of an overall system of prior art arrangements.Sequencing circuit 100 is used withchips 120 that require the supply input VDD to be the highest voltage applied to the chip and requires reduced board size as compared to prior art arrangements.Sequencing circuit 100 has no effect on the other chips in a system. - While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/122,994 US6642750B1 (en) | 2002-04-15 | 2002-04-15 | Sequencing circuit for applying a highest voltage source to a chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/122,994 US6642750B1 (en) | 2002-04-15 | 2002-04-15 | Sequencing circuit for applying a highest voltage source to a chip |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030193363A1 true US20030193363A1 (en) | 2003-10-16 |
US6642750B1 US6642750B1 (en) | 2003-11-04 |
Family
ID=28790665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/122,994 Expired - Fee Related US6642750B1 (en) | 2002-04-15 | 2002-04-15 | Sequencing circuit for applying a highest voltage source to a chip |
Country Status (1)
Country | Link |
---|---|
US (1) | US6642750B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1650856A2 (en) * | 2004-10-22 | 2006-04-26 | Samsung Electronics Co.,Ltd. | Power supply apparatus |
US20060244512A1 (en) * | 2005-04-29 | 2006-11-02 | Ati Technologies, Inc. | Apparatus and methods for balancing supply voltages |
US20140139029A1 (en) * | 2012-11-21 | 2014-05-22 | Stmicroelectronics S.R.L. | Dual input single output regulator for an inertial sensor |
CN103889785A (en) * | 2011-10-27 | 2014-06-25 | 飞思卡尔半导体公司 | Power safety circuit, integrated circuit device and safety critical system |
EP2530809A3 (en) * | 2011-05-30 | 2014-07-30 | Endress + Hauser Process Solutions AG | Electric supply circuit and method for providing a supply voltage |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6753722B1 (en) * | 2003-01-30 | 2004-06-22 | Xilinx, Inc. | Method and apparatus for voltage regulation within an integrated circuit |
US6970032B1 (en) * | 2003-03-25 | 2005-11-29 | Cypress Semiconductor Corporation | Power supply detecting input receiver circuit and method |
US6909204B2 (en) * | 2003-04-01 | 2005-06-21 | Agilent Technologies, Inc. | System for sequencing a first node voltage and a second node voltage |
US6841980B2 (en) * | 2003-06-10 | 2005-01-11 | Bae Systems, Information And Electronic Systems Integration, Inc. | Apparatus for controlling voltage sequencing for a power supply having multiple switching regulators |
US6995599B2 (en) * | 2003-08-26 | 2006-02-07 | Texas Instruments Incorporated | Cross-conduction blocked power selection comparison/control circuitry with NTC (negative temperature coefficient) trip voltage |
JP2007523586A (en) * | 2004-02-17 | 2007-08-16 | アギア システムズ インコーポレーテッド | Switching power supply controller with built-in power supply switching |
US7663426B2 (en) * | 2004-12-03 | 2010-02-16 | Ati Technologies Ulc | Method and apparatus for biasing circuits in response to power up conditions |
TW200722968A (en) * | 2005-12-14 | 2007-06-16 | Kye Systems Corp | Wireless computer peripheral device and its power supply method |
CN101295975B (en) * | 2007-04-24 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | CMOS driving circuit |
US7768756B2 (en) * | 2007-04-27 | 2010-08-03 | Hewlett-Packard Development Company, L.P. | Leakage current protection circuit |
KR101041365B1 (en) * | 2007-05-14 | 2011-06-14 | 주식회사 코아로직 | Voltage selection circuit and dc/dc converter comprising it |
US7973595B2 (en) * | 2009-09-21 | 2011-07-05 | Freescale Semiconductor, Inc. | Power switch circuit |
CN102063171B (en) * | 2010-12-20 | 2016-03-30 | 南京博兰得电子科技有限公司 | A kind of device and method improving Power supply for computer efficiency |
EP2511791B1 (en) * | 2011-04-13 | 2018-06-06 | Dialog Semiconductor GmbH | Dual input RTC supply generation with replica power path and autonomous mode of operation from the system supply |
CN204360323U (en) * | 2013-10-14 | 2015-05-27 | 苹果公司 | For enabling the control circuit of the connection of primary power, computing system and device |
CN104038207B (en) * | 2014-05-30 | 2017-10-17 | 华为技术有限公司 | A kind of switching circuit and electronic equipment |
JP6441619B2 (en) * | 2014-09-03 | 2018-12-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
CN111030291B (en) * | 2019-12-31 | 2021-06-08 | 珠海全志科技股份有限公司 | Power supply path management circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4617473A (en) * | 1984-01-03 | 1986-10-14 | Intersil, Inc. | CMOS backup power switching circuit |
US5272393A (en) * | 1987-11-24 | 1993-12-21 | Hitachi, Ltd. | Voltage converter of semiconductor device |
JP2733796B2 (en) * | 1990-02-13 | 1998-03-30 | セイコーインスツルメンツ株式会社 | Switch circuit |
US5426386A (en) * | 1992-04-21 | 1995-06-20 | Benchmarq Microelectronics, Inc. | Low-power semiconductor voltage comparator with hysteresis |
US5341034A (en) * | 1993-02-11 | 1994-08-23 | Benchmarq Microelectronics, Inc. | Backup battery power controller having channel regions of transistors being biased by power supply or battery |
JPH08289483A (en) * | 1995-04-18 | 1996-11-01 | Rohm Co Ltd | Power supply |
FR2755316B1 (en) * | 1996-10-25 | 1999-01-15 | Sgs Thomson Microelectronics | VOLTAGE REGULATOR WITH AUTOMATIC SELECTION OF THE HIGHEST SUPPLY VOLTAGE |
US5886561A (en) * | 1996-11-18 | 1999-03-23 | Waferscale Integration, Inc. | Backup battery switch |
US5841724A (en) * | 1997-06-12 | 1998-11-24 | Enable Semiconductor, Inc. | Voltage source and memory-voltage switch in a memory chip |
US6040718A (en) * | 1997-12-15 | 2000-03-21 | National Semiconductor Corporation | Median reference voltage selection circuit |
US6118188A (en) * | 1998-12-21 | 2000-09-12 | Stmicroelectronics, Inc. | Apparatus and method for switching between two power supplies of an integrated circuit |
-
2002
- 2002-04-15 US US10/122,994 patent/US6642750B1/en not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1650856A2 (en) * | 2004-10-22 | 2006-04-26 | Samsung Electronics Co.,Ltd. | Power supply apparatus |
US20060090089A1 (en) * | 2004-10-22 | 2006-04-27 | Samsung Electronics Co., Ltd. | Apparatus for supplying power to controller |
EP1650856A3 (en) * | 2004-10-22 | 2006-07-12 | Samsung Electronics Co.,Ltd. | Power supply apparatus |
US7516337B2 (en) | 2004-10-22 | 2009-04-07 | Samsung Electronics Co., Ltd. | Apparatus for supplying power to controller |
US20060244512A1 (en) * | 2005-04-29 | 2006-11-02 | Ati Technologies, Inc. | Apparatus and methods for balancing supply voltages |
US8618866B2 (en) * | 2005-04-29 | 2013-12-31 | Ati Technologies Ulc | Apparatus and methods for balancing supply voltages |
EP2530809A3 (en) * | 2011-05-30 | 2014-07-30 | Endress + Hauser Process Solutions AG | Electric supply circuit and method for providing a supply voltage |
US9577470B2 (en) | 2011-05-30 | 2017-02-21 | Endress + Hauser Process Solutions Ag | Electrical and/or electronic supply circuit and method for providing a supply voltage |
CN103889785A (en) * | 2011-10-27 | 2014-06-25 | 飞思卡尔半导体公司 | Power safety circuit, integrated circuit device and safety critical system |
US9620992B2 (en) | 2011-10-27 | 2017-04-11 | Nxp Usa, Inc. | Power safety circuit, integrated circuit device and safety critical system |
US20140139029A1 (en) * | 2012-11-21 | 2014-05-22 | Stmicroelectronics S.R.L. | Dual input single output regulator for an inertial sensor |
US9329649B2 (en) * | 2012-11-21 | 2016-05-03 | Stmicroelectronics S.R.L. | Dual input single output regulator for an inertial sensor |
Also Published As
Publication number | Publication date |
---|---|
US6642750B1 (en) | 2003-11-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6642750B1 (en) | Sequencing circuit for applying a highest voltage source to a chip | |
US7116153B2 (en) | Circuit for driving a depletion-type JFET | |
US4617473A (en) | CMOS backup power switching circuit | |
US6329874B1 (en) | Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode | |
US10168363B1 (en) | Current sensor with extended voltage range | |
KR19980080221A (en) | Integrated circuits running on low voltage technology | |
KR950020744A (en) | High Voltage Switches and their Regulators in Electronic Erasable Programmable Read-Only Memory Integrated Circuits (EEPROM ICs) | |
US6930517B2 (en) | Differential transistor and method therefor | |
US5686824A (en) | Voltage regulator with virtually zero power dissipation | |
US7683693B2 (en) | Hot swap controller with zero loaded charge pump | |
US7286005B2 (en) | Supply voltage switching circuit | |
US7400188B2 (en) | Voltage providing circuit | |
US20040032701A1 (en) | Current limiting circuit and output circuit including the same | |
US7432754B2 (en) | Voltage control circuit having a power switch | |
US6310497B1 (en) | Power supply loss detector method and apparatus | |
US20100100753A1 (en) | Power control circuit | |
US10411687B2 (en) | Near zero quiescent current circuit for selecting a maximum supply voltage | |
JPH02105722A (en) | Current switching type driver circuit | |
USRE41982E1 (en) | Circuitry to provide a low power input buffer | |
US6677810B2 (en) | Reference voltage circuit | |
US10291163B2 (en) | Cascode structure for linear regulators and clamps | |
US6426857B1 (en) | Protective circuit for a power field-effect transistor | |
US6703883B2 (en) | Low current clock sensor | |
US11196421B2 (en) | Logic circuit and circuit chip | |
US7928793B2 (en) | Voltage selection circuitry |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:EGAN, PATRICK KEVIN;REEL/FRAME:012815/0284 Effective date: 20020415 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: GOOGLE INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:026664/0866 Effective date: 20110503 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20151104 |
|
AS | Assignment |
Owner name: GOOGLE LLC, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:GOOGLE INC.;REEL/FRAME:044142/0357 Effective date: 20170929 |