US20030117163A1 - Testing apparatus and method of measuring operation timing of semiconductor device - Google Patents
Testing apparatus and method of measuring operation timing of semiconductor device Download PDFInfo
- Publication number
- US20030117163A1 US20030117163A1 US10/197,871 US19787102A US2003117163A1 US 20030117163 A1 US20030117163 A1 US 20030117163A1 US 19787102 A US19787102 A US 19787102A US 2003117163 A1 US2003117163 A1 US 2003117163A1
- Authority
- US
- United States
- Prior art keywords
- operation timing
- semiconductor device
- measuring
- circuit simulation
- storage means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31937—Timing aspects, e.g. measuring propagation delay
Definitions
- the present invention relates to a testing apparatus and method of testing operation timing of a semiconductor device.
- the present invention relates to a testing apparatus and method which perform a circuit simulation using parameters to check operation timing of a semiconductor device and test operation timing of the semiconductor device using a result of the circuit simulation.
- the present invention has been achieved in view of the above problems, and an object of the invention is therefore to provide a testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer as the lot or wafer of a DUT to obtain transistor parameters for a Spice circuit simulation and which can prevent an error of the above kind by measuring high-speed operation timing of the DUT using the transistor parameters thus obtained.
- a testing apparatus for measuring operation timing of a semiconductor device, comprising: measuring means for measuring transistor characteristics of a circuit for transistor characteristics extraction that is formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storage means for storing measurement values of the measuring means as parameters; circuit simulation means for performing a circuit simulation on a measurement system using the parameters stored in the storage means, and for storing resulting operation timing in the storage means; actual measurement means for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that is obtained by the circuit simulation and is stored in the storage means; and a CPU for controlling the measuring means, the storage means, the circuit simulation means, and the actual measurement means.
- a testing method of measuring operation timing of a semiconductor device wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation is detected by the testing apparatus according to the present testing apparatus of claim 1 or 2.
- a testing method of measuring operation timing of a semiconductor device comprising the steps of: measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storing measurement values of the transistor characteristics as parameters; performing a circuit simulation on a measurement system using the parameters, and storing resulting operation timing; and actually measuring operation timing of the subject semiconductor device, comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation, and modifying a test program for operation timing measurement when the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a predetermined value.
- FIG. 1 is a block diagram showing a configuration of the first embodiment.
- FIG. 2 is a test flowchart for explaining an operation timing measurement and evaluation procedure according to the first embodiment
- FIGS. 3 (A) to 3 (C) show specific examples of the above-described actual measurement of a DUT access time.
- FIGS. 4 (A) and 4 (B) show an example of measuring an input pulse width.
- FIGS. 5 (A) to 5 (C) relate to exemplary switching tests.
- FIGS. 6 (A) and 6 (B) show an example of measuring an output pulse width.
- FIG. 7 is a block diagram showing a configuration of the second embodiment.
- FIG. 1 is a block diagram showing a configuration of the embodiment.
- a tester 10 has a central processing unit (hereinafter referred to as “CPU”) 11 , an actual measurement device 12 for actually measuring operation timing, for example, an access time, of a DUT under a control of the CPU 11 , and a storage device 13 for storing parameters (described later) and a circuit simulation result.
- CPU central processing unit
- an actual measurement device 12 for actually measuring operation timing, for example, an access time, of a DUT under a control of the CPU 11
- storage device 13 for storing parameters (described later) and a circuit simulation result.
- a parameter measuring device 20 measures parameters of a transistor under a control of the CPU 11 , and stores the measured parameters in the storage device 13 .
- a circuit simulation device 30 performs a circuit simulation on a measurement system using the parameters stored in the storage device 13 , and stores a result of the circuit simulation in the storage device 13 .
- step S 1 the CPU 11 of the tester 10 starts the parameter measuring device 20 and causes it to measure characteristic values of a circuit for transistor characteristics extraction (not shown) that was formed in advance and belongs to the same lot or wafer as the lot or wafer of a DUT (not shown) and to store the measured characteristic values in the storage device 13 as parameters.
- the CPU 11 starts the circuit simulation device 30 and causes it to perform a circuit simulation on a measurement system using the parameters stored in the storage device 13 and to store, in the storage device 13 , a simulation result (access time tSA) that is a propagation delay value of a certain path of the DUT (temporary storage).
- a simulation result access time tSA
- step S 3 the actual measurement device 12 of the tester 10 actually measures an access time tMA of the DUT. Specific examples of the actual measurement will be described later.
- step S 4 the access time tSA as the simulation result is compared with the actually measured access time tMA and it is checked whether the difference is larger than or equal to a prescribed value ⁇ t. If the difference is smaller than ⁇ t, the process is finished with a judgment that there are no problems. If the difference is larger than or equal to ⁇ t, the process goes to step S 4 .
- step S 4 an analysis is made to determine a reason for the large difference and a circuit simulation is performed again, or the parameters or a test program for measurement of a DUT access time is modified or some other proper measure is taken so that a difference smaller than ⁇ t will be obtained.
- FIGS. 3 (A) to 3 (C) to FIGS. 6 (A) to 6 (B) show specific examples of the above-described actual measurement of a DUT access time.
- FIGS. 3 (A) to 3 (C) and FIGS. 4 (A) and 4 (B) relate to exemplary time tests. More specifically, FIGS. 3 (A) to 3 (C) show an example of measuring a input setup time and a hold time.
- a reference clock signal shown in FIG. 3(A) is input externally to the data input terminal of the DUT with timing that is prescribed by a product specification, and H data shown in FIG. 3(B) and L data shown in FIG. 3(C) are input to the DUT.
- a setup time tsu and a hold time th are obtained as times between a time point of a prescribed level VOH in a specification of the reference clock signal and time points when each input signal crosses an input judgment level (VIH or VIL) that is prescribed by the product specification.
- VIP input judgment level
- a judgment to the effect that the operation is normal is made if the measured setup times tsu and hold times th are shorter than or equal to product specification tsu and th, respectively, that are prescribed in the product specification.
- FIGS. 4 (A) and 4 (B) show an example of measuring an input pulse width.
- H data and L data shown in FIGS. 4 (A) and 4 (B), respectively, are input to the DUT.
- a pulse width tw is obtained as a time between time points when each input signal crosses an input judgment level (VIH or VIL) that is prescribed by the product specification.
- VIP input judgment level
- a judgment to the effect that the operation is normal is made if the measured pulse widths tw are shorter than or equal to a product specification tw that is prescribed by the product specification.
- FIGS. 5 (A) to 5 (C) and FIGS. 6 (A) and 6 (B) relate to exemplary switching tests.
- a reference clock signal shown in FIG. 5(A) is input to the DUT and H data shown in FIG. 5(B) and L data shown in FIG. 5(C) are output from the DUT.
- a delay time td and a data valid time tv are obtained as times between time points of a level VOH of the reference clock signal and time points when each output signal crosses an output judgment level (VOH or VOL) that is prescribed by the product specification.
- a judgment to the effect that the operation is normal is made if it is shorter than or equal to a product specification td that is prescribed by the product specification.
- a judgment to the effect that the operation is normal is made if it is longer than or equal to a product specification tv that is prescribed by the product specification.
- FIGS. 6 (A) and 6 (B) show an example of measuring an output pulse width.
- a pulse width tw is obtained as a time between time points when each of H data shown in FIG. 6(A) and L data shown in FIG. 6(B) that are output from the DUT crosses an output judgment level (VOH or VOL) that is prescribed by the product specification.
- VH or VOL output judgment level
- a judgment to the effect that the operation is normal is made if the measured pulse widths tw are longer than or equal to a product specification tw that is prescribed by the product specification.
- FIG. 7 is a block diagram showing a configuration of the second embodiment. Components in FIG. 7 having the same or corresponding components in FIG. 1 are given the same reference numerals as the latter and will not be described.
- the second embodiment is different from the first embodiment of FIG. 1 in that three CPUs, that is, a first CPU 11 A, a second CPU 11 B, and a third CPU 11 C, are provided. The three CPUs 11 A- 11 C share the control functions.
- the first CPU 11 A controls the actual measurement device 12 and the storage device 13
- the second CPU 11 B controls the parameter measuring device 20 and the storage device 13
- the third CPU 11 C controls the circuit simulation device 30 and the storage device 13 .
- the measurement operation of the second embodiment is the same as that of the first embodiment and hence will not be described.
- the CPU may comprise a first CPU for controlling operation of the actual measurement means and the storage means, a second CPU for controlling operation of the measuring means and the storage means, and a third CPU for controlling operation of the circuit simulation means and the storage means.
- a testing method of measuring operation timing of a semiconductor device wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation may be detected by the testing apparatus according to the above testing apparatus.
- the above testing method may further comprise the step of modifying a test program for operation timing measurement if the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a prescribed value. This makes it possible to perform a timing measurement with even higher accuracy.
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer, and can measure high-speed operation timing in a high precision.
The testing apparatus comprises measuring means 20 for measuring transistor characteristics of a circuit for transistor characteristics extraction that is formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device, storage means 13 for storing measurement values of the measuring means as parameters, circuit simulation means 30 for performing a circuit simulation on a measurement system using the parameters stored in the storage means, and for storing resulting operation timing in the storage means, actual measurement means 12 for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that is obtained by the circuit simulation and is stored in the storage means, and a CPU 11 for controlling of the above means.
Description
- 1. Field of the Invention
- The present invention relates to a testing apparatus and method of testing operation timing of a semiconductor device. In particular, the present invention relates to a testing apparatus and method which perform a circuit simulation using parameters to check operation timing of a semiconductor device and test operation timing of the semiconductor device using a result of the circuit simulation.
- 2. Description of Related Art
- With advances of the semiconductor wafer process technology and the circuit technology, the operation speeds of large-capacity semiconductor devices are becoming higher increasingly. In this connection, the technology of testing such devices, in particular, the technology of measuring operation timing such as an access time of a high-speed device with high accuracy, is becoming important.
- Conventionally, as for high-accuracy access time measurement, not only is a subject device (hereinafter referred to as “DUT”) measured with a tester but also the following measure is taken. Electrical characteristics of a measurement jig, the driver and the comparator of a tester, and the output buffer circuit of the DUT are modeled. An electrical characteristic simulation is performed in advance with Spice (a circuit simulator), for example, by using the modeled electrical characteristics. Operation timing obtained as a simulation result is compared with operation timing as a result of an actual measurement on the DUT, to increase the measurement accuracy.
- Specifically, a reason for a difference between a circuit simulation value and an actual measurement value is investigated, influences of the reason are recognized quantitatively, and problems of the measurement system are improved.
- Conventionally, since an operation timing of a semiconductor device is judged in the above-described manner, the characteristics of the output buffer transistor of a DUT tend to be influenced more by a wafer process variation as the operation speed of the DUT increases, which is a factor in causing a difference between a circuit simulation result and a DUT actual measurement value. A largest factor in causing such a difference is thought to be employing, as characteristics of the output buffer circuit of a DUT that is incorporated in a circuit simulation, transistor parameters obtained by measuring a wafer of a different lot from the lot of the DUT. Where timing measurement on a DUT and measurement of transistor parameters to be used for a circuit simulation are performed separately, the circuit simulation may not be accurate enough to cover the actual measurement. As a result, there may occur a case that erroneous Spice transistor parameters (due to a difference between wafer process lots) are used as they are in the circuit simulation, to produce an erroneous measurement result. It is expected that such an error will become more noticeable as the operation speed of a device increases.
- The present invention has been achieved in view of the above problems, and an object of the invention is therefore to provide a testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer as the lot or wafer of a DUT to obtain transistor parameters for a Spice circuit simulation and which can prevent an error of the above kind by measuring high-speed operation timing of the DUT using the transistor parameters thus obtained.
- According to a first aspect of the present invention, there is provided a testing apparatus for measuring operation timing of a semiconductor device, comprising: measuring means for measuring transistor characteristics of a circuit for transistor characteristics extraction that is formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storage means for storing measurement values of the measuring means as parameters; circuit simulation means for performing a circuit simulation on a measurement system using the parameters stored in the storage means, and for storing resulting operation timing in the storage means; actual measurement means for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that is obtained by the circuit simulation and is stored in the storage means; and a CPU for controlling the measuring means, the storage means, the circuit simulation means, and the actual measurement means.
- According to a second aspect of the present invention, there is provided a testing method of measuring operation timing of a semiconductor device, wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation is detected by the testing apparatus according to the present testing apparatus of claim 1 or 2.
- According to a third aspect of the present invention, there is provided a testing method of measuring operation timing of a semiconductor device, comprising the steps of: measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storing measurement values of the transistor characteristics as parameters; performing a circuit simulation on a measurement system using the parameters, and storing resulting operation timing; and actually measuring operation timing of the subject semiconductor device, comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation, and modifying a test program for operation timing measurement when the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a predetermined value.
- The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.
- FIG. 1 is a block diagram showing a configuration of the first embodiment.
- FIG. 2 is a test flowchart for explaining an operation timing measurement and evaluation procedure according to the first embodiment
- FIGS.3(A) to 3(C) show specific examples of the above-described actual measurement of a DUT access time.
- FIGS.4(A) and 4(B) show an example of measuring an input pulse width.
- FIGS.5(A) to 5(C) relate to exemplary switching tests.
- FIGS.6(A) and 6(B) show an example of measuring an output pulse width.
- FIG. 7 is a block diagram showing a configuration of the second embodiment.
- Embodiments of the present invention will be described below with reference to the accompanying drawings. It is noted that the same reference symbols in the drawings denote the same or corresponding components.
- First Embodiment
- A first embodiment of the present invention will be hereinafter described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the embodiment. As shown in FIG. 1, a
tester 10 has a central processing unit (hereinafter referred to as “CPU”) 11, anactual measurement device 12 for actually measuring operation timing, for example, an access time, of a DUT under a control of theCPU 11, and astorage device 13 for storing parameters (described later) and a circuit simulation result. - A parameter measuring
device 20 measures parameters of a transistor under a control of theCPU 11, and stores the measured parameters in thestorage device 13. Acircuit simulation device 30 performs a circuit simulation on a measurement system using the parameters stored in thestorage device 13, and stores a result of the circuit simulation in thestorage device 13. - Next, an operation timing measurement and evaluation procedure according to the embodiment will be described with reference to a test flowchart of FIG. 2. This flowchart outlines a device test program that is provided in the
tester 10 and shows a preprogrammed measurement procedure. First, at step S1, theCPU 11 of thetester 10 starts the parameter measuringdevice 20 and causes it to measure characteristic values of a circuit for transistor characteristics extraction (not shown) that was formed in advance and belongs to the same lot or wafer as the lot or wafer of a DUT (not shown) and to store the measured characteristic values in thestorage device 13 as parameters. - At step S2, the
CPU 11 starts thecircuit simulation device 30 and causes it to perform a circuit simulation on a measurement system using the parameters stored in thestorage device 13 and to store, in thestorage device 13, a simulation result (access time tSA) that is a propagation delay value of a certain path of the DUT (temporary storage). - At step S3, the
actual measurement device 12 of thetester 10 actually measures an access time tMA of the DUT. Specific examples of the actual measurement will be described later. - At step S4, the access time tSA as the simulation result is compared with the actually measured access time tMA and it is checked whether the difference is larger than or equal to a prescribed value Δt. If the difference is smaller than Δt, the process is finished with a judgment that there are no problems. If the difference is larger than or equal to Δt, the process goes to step S4. At step S4, an analysis is made to determine a reason for the large difference and a circuit simulation is performed again, or the parameters or a test program for measurement of a DUT access time is modified or some other proper measure is taken so that a difference smaller than Δt will be obtained.
- FIGS.3(A) to 3(C) to FIGS. 6(A) to 6(B) show specific examples of the above-described actual measurement of a DUT access time. Among those drawings, FIGS. 3(A) to 3(C) and FIGS. 4(A) and 4(B) relate to exemplary time tests. More specifically, FIGS. 3(A) to 3(C) show an example of measuring a input setup time and a hold time.
- A reference clock signal shown in FIG. 3(A) is input externally to the data input terminal of the DUT with timing that is prescribed by a product specification, and H data shown in FIG. 3(B) and L data shown in FIG. 3(C) are input to the DUT. A setup time tsu and a hold time th (see FIGS.3(B) and 3(C)) are obtained as times between a time point of a prescribed level VOH in a specification of the reference clock signal and time points when each input signal crosses an input judgment level (VIH or VIL) that is prescribed by the product specification. A judgment to the effect that the operation is normal is made if the measured setup times tsu and hold times th are shorter than or equal to product specification tsu and th, respectively, that are prescribed in the product specification.
- FIGS.4(A) and 4(B) show an example of measuring an input pulse width. H data and L data shown in FIGS. 4(A) and 4(B), respectively, are input to the DUT. A pulse width tw is obtained as a time between time points when each input signal crosses an input judgment level (VIH or VIL) that is prescribed by the product specification. A judgment to the effect that the operation is normal is made if the measured pulse widths tw are shorter than or equal to a product specification tw that is prescribed by the product specification.
- FIGS.5(A) to 5(C) and FIGS. 6(A) and 6(B) relate to exemplary switching tests. In the example of FIGS. 5(A) to 5(C), a reference clock signal shown in FIG. 5(A) is input to the DUT and H data shown in FIG. 5(B) and L data shown in FIG. 5(C) are output from the DUT. A delay time td and a data valid time tv (see FIGS. 5(B) and 5(C)) are obtained as times between time points of a level VOH of the reference clock signal and time points when each output signal crosses an output judgment level (VOH or VOL) that is prescribed by the product specification. As for the delay time td, a judgment to the effect that the operation is normal is made if it is shorter than or equal to a product specification td that is prescribed by the product specification. As for the data valid time tv, a judgment to the effect that the operation is normal is made if it is longer than or equal to a product specification tv that is prescribed by the product specification.
- FIGS.6(A) and 6(B) show an example of measuring an output pulse width. A pulse width tw is obtained as a time between time points when each of H data shown in FIG. 6(A) and L data shown in FIG. 6(B) that are output from the DUT crosses an output judgment level (VOH or VOL) that is prescribed by the product specification. A judgment to the effect that the operation is normal is made if the measured pulse widths tw are longer than or equal to a product specification tw that is prescribed by the product specification.
- Second Embodiment
- Next, a second embodiment of the invention will be described with reference to FIG. 7. FIG. 7 is a block diagram showing a configuration of the second embodiment. Components in FIG. 7 having the same or corresponding components in FIG. 1 are given the same reference numerals as the latter and will not be described. The second embodiment is different from the first embodiment of FIG. 1 in that three CPUs, that is, a
first CPU 11A, asecond CPU 11B, and a third CPU 11C, are provided. The threeCPUs 11A-11C share the control functions. Specifically, thefirst CPU 11A controls theactual measurement device 12 and thestorage device 13, thesecond CPU 11B controls theparameter measuring device 20 and thestorage device 13, and the third CPU 11C controls thecircuit simulation device 30 and thestorage device 13. The measurement operation of the second embodiment is the same as that of the first embodiment and hence will not be described. - A testing apparatus according to the invention for measuring operation timing of a semiconductor device may comprise measuring means for measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storage means for storing measurement values of the measuring means as parameters; circuit simulation means for performing a circuit simulation on a measurement system using the parameters stored in the storage means, and for storing resulting operation timing in the storage means; actual measurement means for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation and is stored in the storage means; and a CPU for controlling the measuring means, the storage means, the circuit simulation means, and the actual measurement means. Therefore, transistor characteristics of a wafer of the same lot or wafer as the lot or wafer of a DUT can easily be measured and evaluated on a tester, and high-speed operation timing of the DUT can be measured with high accuracy.
- In the above testing apparatus, the CPU may comprise a first CPU for controlling operation of the actual measurement means and the storage means, a second CPU for controlling operation of the measuring means and the storage means, and a third CPU for controlling operation of the circuit simulation means and the storage means. With this configuration, the load of each CPU is light and hence a high-accuracy measurement is enabled.
- A testing method of measuring operation timing of a semiconductor device, wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation may be detected by the testing apparatus according to the above testing apparatus.
- A testing method according to the present invention for measuring operation timing of a semiconductor device comprises the steps of measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device; storing measurement values of the transistor characteristics as parameters; performing a circuit simulation on a measurement system using the parameters, and storing resulting operation timing; and actually measuring operation timing of the subject semiconductor device, and comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation. Therefore, the measurement accuracy of high-speed operation timing in a tester can be increased.
- The above testing method may further comprise the step of modifying a test program for operation timing measurement if the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a prescribed value. This makes it possible to perform a timing measurement with even higher accuracy.
- The present invention has been described in detail with respect to various embodiments, and it will now be apparent from the foregoing to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and it is the invention, therefore, in the appended claims to cover all such changes and modifications as fall within the true spirit of the invention.
- The entire disclosure of Japanese Patent Application No. 2001-392324 filed on Dec. 25, 2001 including specification, claims, drawings and summary are incorporated herein by reference in its entirety.
Claims (5)
1. A testing apparatus for measuring operation timing of a semiconductor device, comprising:
measuring means for measuring transistor characteristics of a circuit for transistor characteristics extraction that is formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device;
storage means for storing measurement values of said measuring means as parameters;
circuit simulation means for performing a circuit simulation on a measurement system using the parameters stored in said storage means, and for storing resulting operation timing in said storage means;
actual measurement means for actually measuring operation timing of the subject semiconductor device, and for comparing a resulting actual measurement value with the operation timing that is obtained by the circuit simulation and is stored in said storage means; and
a CPU for controlling said measuring means, said storage means, said circuit simulation means, and said actual measurement means.
2. The testing apparatus according to claim 1 , wherein said CPU comprises:
a first CPU for controlling operation of said actual measurement means and said storage means;
a second CPU for controlling operation of said measuring means and said storage means; and
a third CPU for controlling operation of said circuit simulation means and said storage means.
3. A testing method of measuring operation timing of a semiconductor device, wherein a difference between an actual measurement value of operation timing of a subject semiconductor device and operation timing obtained by a circuit simulation is detected by the testing apparatus according to claim 1 .
4. The testing method according to claim 3 , further comprising the step of modifying a test program for operation timing measurement when the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a predetermined value.
5. A testing method of measuring operation timing of a semiconductor device, comprising the steps of:
measuring transistor characteristics of a circuit for transistor characteristics extraction that was formed in advance and belongs to the same lot or wafer as a lot or wafer of a subject semiconductor device;
storing measurement values of the transistor characteristics as parameters;
performing a circuit simulation on a measurement system using the parameters, and storing resulting operation timing;
actually measuring operation timing of the subject semiconductor device, and comparing a resulting actual measurement value with the operation timing that was obtained by the circuit simulation, and
modifying a test program for operation timing measurement when the difference between the actual measurement value of the operation timing of the subject semiconductor device and the operation timing obtained by the circuit simulation is greater than or equal to a predetermined value.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-392324 | 2001-12-25 | ||
JP2001392324A JP2003194885A (en) | 2001-12-25 | 2001-12-25 | Test device and test method of operation timing of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US6577150B1 US6577150B1 (en) | 2003-06-10 |
US20030117163A1 true US20030117163A1 (en) | 2003-06-26 |
Family
ID=19188614
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/197,871 Expired - Fee Related US6577150B1 (en) | 2001-12-25 | 2002-07-19 | Testing apparatus and method of measuring operation timing of semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US6577150B1 (en) |
JP (1) | JP2003194885A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050222798A1 (en) * | 2004-02-02 | 2005-10-06 | Waschura Thomas E | Method and apparatus for creating performance limits from parametric measurements |
US20080221854A1 (en) * | 2007-03-05 | 2008-09-11 | Fujitsu Limited | Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter |
US20090119542A1 (en) * | 2007-11-05 | 2009-05-07 | Advantest Corporation | System, method, and program product for simulating test equipment |
EP4306975A1 (en) * | 2022-07-13 | 2024-01-17 | MediaTek Inc. | Method and apparatus for performing die-level electrical parameter extraction through using estimated mapping relationship between electrical parameters of transistor types and measurement results of logic blocks |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007198836A (en) * | 2006-01-25 | 2007-08-09 | Agilent Technol Inc | Method and instrument for measuring characteristic of fet |
US7861116B2 (en) * | 2007-12-31 | 2010-12-28 | Intel Corporation | Device, system, and method for optimized concurrent error detection |
JP5262985B2 (en) * | 2009-05-19 | 2013-08-14 | 富士通株式会社 | Delay fault inspection program, delay fault inspection apparatus, and delay fault inspection method |
US11164551B2 (en) | 2019-02-28 | 2021-11-02 | Clifford W. Chase | Amplifier matching in a digital amplifier modeling system |
CN111931446B (en) * | 2020-09-24 | 2021-01-01 | 中天弘宇集成电路有限责任公司 | Modeling method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000357391A (en) * | 1999-06-14 | 2000-12-26 | Fujitsu Ltd | Semiconductor integrated circuit |
JP2002230998A (en) * | 2001-02-01 | 2002-08-16 | Mitsubishi Electric Corp | Semiconductor memory |
-
2001
- 2001-12-25 JP JP2001392324A patent/JP2003194885A/en not_active Withdrawn
-
2002
- 2002-07-19 US US10/197,871 patent/US6577150B1/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050222798A1 (en) * | 2004-02-02 | 2005-10-06 | Waschura Thomas E | Method and apparatus for creating performance limits from parametric measurements |
US7301325B2 (en) * | 2004-02-02 | 2007-11-27 | Synthesys Research, Inc. | Method and apparatus for creating performance limits from parametric measurements |
US20080221854A1 (en) * | 2007-03-05 | 2008-09-11 | Fujitsu Limited | Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter |
US8935146B2 (en) * | 2007-03-05 | 2015-01-13 | Fujitsu Semiconductor Limited | Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter |
US20090119542A1 (en) * | 2007-11-05 | 2009-05-07 | Advantest Corporation | System, method, and program product for simulating test equipment |
EP4306975A1 (en) * | 2022-07-13 | 2024-01-17 | MediaTek Inc. | Method and apparatus for performing die-level electrical parameter extraction through using estimated mapping relationship between electrical parameters of transistor types and measurement results of logic blocks |
Also Published As
Publication number | Publication date |
---|---|
US6577150B1 (en) | 2003-06-10 |
JP2003194885A (en) | 2003-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100506777B1 (en) | Glitch detection for semiconductor test system | |
US7539893B1 (en) | Systems and methods for speed binning of integrated circuits | |
US6853177B2 (en) | Semiconductor device with process monitor circuit and test method thereof | |
US7484166B2 (en) | Semiconductor integrated circuit verification method and test pattern preparation method | |
WO2008125998A1 (en) | Analog circuit testing and test pattern generation | |
US6577150B1 (en) | Testing apparatus and method of measuring operation timing of semiconductor device | |
US8185336B2 (en) | Test apparatus, test method, program, and recording medium reducing the influence of variations | |
US20080231297A1 (en) | Method for calibrating semiconductor device tester | |
US6128757A (en) | Low voltage screen for improving the fault coverage of integrated circuit production test programs | |
US20090105970A1 (en) | Semiconductor tester | |
US7404158B2 (en) | Inspection method and inspection apparatus for semiconductor integrated circuit | |
KR20180078897A (en) | The test method of semiconductor device and test system for performing the same | |
KR20140044270A (en) | Testing apparatus and acquiring method of testing condition | |
US6014033A (en) | Method of identifying the point at which an integrated circuit fails a functional test | |
US6966022B1 (en) | System and method for determining integrated circuit logic speed | |
JP2000009810A (en) | Device and method for processing data for testing semiconductor, and device for testing semiconductor | |
US7178071B2 (en) | Device for and method of examining the signal performance of semiconductor circuits | |
JP4125138B2 (en) | Semiconductor test equipment | |
JPH0252446A (en) | Testing apparatus for integrated circuit | |
JP2007192635A (en) | System and method for measuring circuit | |
JPH11101850A (en) | Ic tester | |
JP3398755B2 (en) | IC tester current measuring device | |
JP4129723B2 (en) | Integrated circuit test apparatus and analog waveform measurement method | |
KR100429629B1 (en) | Boundary Scan Test Chip Signal Delay Measuring System and Method for the Same | |
US10236074B1 (en) | Circuits for and methods of making measurements in a testing arrangement having a plurality of devices under test |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NISHIMURA, YASUMASA;REEL/FRAME:013124/0682 Effective date: 20020513 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20070610 |