US20030100184A1 - Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon - Google Patents

Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon Download PDF

Info

Publication number
US20030100184A1
US20030100184A1 US10/301,707 US30170702A US2003100184A1 US 20030100184 A1 US20030100184 A1 US 20030100184A1 US 30170702 A US30170702 A US 30170702A US 2003100184 A1 US2003100184 A1 US 2003100184A1
Authority
US
United States
Prior art keywords
layer
semiconductor device
wsi
range
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/301,707
Inventor
Hsiao-Che Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/301,707 priority Critical patent/US20030100184A1/en
Publication of US20030100184A1 publication Critical patent/US20030100184A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Definitions

  • the present invention relates to the field of semiconductor devices and methods of manufacture thereof.
  • gate structures of many semiconductor devices employ multiple layer gate and interconnect materials which maintain the properties of polycrystalline silicon but add a high-conductivity layer on top.
  • polysilicon and tungsten-silicide layers are commonly used for this purpose. That is, semiconductor devices that employ polycrystalline silicon (polysilicon) gates formed over a gate dielectric layer encounter increased resistance of the polysilicon as size is scaled down to achieve higher circuit density. Due to the resulting relatively high resistance values of the polysilicon layer, a tungsten silicide (WSi x ) layer is often formed in order to lower resistance along the polysilicon gate. Generally, the ratio of silicon to tungsten is approximately 2.6 to 1 within the tungsten silicide (WSi x ) layer. Initially, problems emerged with adhesion of the metal silicide to the polysilicon.
  • McPherson U.S. Pat. No. 4,816,425.
  • McPherson teaches a semiconductor device having a gate 11 comprising a multi-layer structure including a layer 11 a of polycrystalline silicon with an overlying layer of refractory metal silicide 11 b , such as MoSi2 or WSi2.
  • refractory metal silicide 11 b such as MoSi2 or WSi2.
  • the problem of adhesion of the metal silicide to the polysilicon is addressed by forming a thin silicon oxide coating 11 c on the polysilicon before sputtering the metal silicide layer.
  • the resulting multi-layer structure has low resistance but retains the advantages of polysilicon on silicon.
  • Chung U.S. Pat. No. 5,646,070 teaches a single process for creating a multi-layered semiconductor device that employs tungsten silicide but incorporates an intervening layer that prevents degradation of the electrical properties of the underlying silicide during the fabrication process. Since CVD-tungsten involves fluorine chemistry, such a protective layer prevents the interaction during fabrication of the vapor deposited by CVD-tungsten with the underlying silicide.
  • Neither of these multi-layer methods addresses modifying the WSi x layer itself to increase device density or speed. Further reducing semiconductor dimensions while maintaining or increasing performance is an on-going objective of semiconductor device design. Because of the large number of gates employed in semiconductor devices, a reduction in gate size can result in a substantial reduction in the overall dimensions of the semiconductor device accompanied by increased device density and even increased device speed.
  • the shrinkage of gate dimension increases resistivity and decreases speed.
  • the first approach decreases the x-ratio
  • the second approach increases the thickness of WSi x .
  • these two approaches increase the grain size of WSi x and result in a rough surface.
  • This increase in WSi x grain size results in increased surface roughness.
  • increased thin film grain size results in increased side-wall roughness after gate conductor (GC) etching as well as increased likelihood of gate conductor side-wall extension, thereby reducing realizable device density.
  • GC gate conductor
  • the lowering of the x-ratio is not feasible as an approach to achieving a decrease in WSi x thickness, because of these undesirable increases in surface and side-wall roughness.
  • the conventional structure of WSi x film employed in semiconductor devices is a single layer.
  • WSi x grains grow larger and aggregate in a single grain layer with the grain boundary reaching to the Poly/WSi x and WSi x /SiN interfaces. These larger grains introduce a WSi x surface with significant roughness, which results in semiconductor devices with reduced gate density.
  • the present invention provides a method of preparing small grain size WSi x structures in general, and in particular, of preparing gate conductors.
  • the present invention provides a method of decreasing resistivity but preventing larger grain size by introducing a multilayer structure of WSi x .
  • the present invention is directed to a method for manufacturing a WSi x film with smaller grains by providing a multi-layer WSi x structure.
  • the WSi x film is prepared with smaller grains after anneal by introducing a multi-layer WSi x structure prior to anneal.
  • the present invention introduces a multi-layer WSi x structure at deposition, so that a multi-layer WSi x grain structure with each layer having a smaller and more uniform grain size results after anneal.
  • FIG. 1 illustrates the rough surface of a single WSi x thin film grown according to the prior art.
  • FIG. 2 illustrates the actual surface roughness after anneal of a single layer WSi x film.
  • FIG. 3 illustrates actual reduced surface roughness after anneal of a multi-layer WSi x film according to the present invention.
  • FIG. 4 a illustrates the reduced grain size WSi x film resulting after anneal from a first embodiment of the present invention which is directed to an initial three-layer WSi x structure.
  • FIG. 4 b illustrates the reduced grain size WSi x film resulting after anneal from a second embodiment of the present invention which is directed to a five-layer WSi x structure.
  • FIG. 5 shows a semiconductor device with a multi-layered WSi x film formed on a semiconductor body, according to the present invention.
  • the method of the present invention achieves multi-layer uniform small grain WSi x films which result from depositing several thin WSi x layers separated by a single Si or W layer between each thin WSi x layer.
  • the nucleation site occurs at each WSi x /W or WSi x /Si interface of the multi-layer WSi x structure, resulting in a multi-layer WSi x grain structure after anneal (see FIG. 4 a ).
  • the thickness of the W or Si layer interposed between the WSi x layers is very thin, at anneal the nucleation site is in the W or Si layer, resulting in a multi-layer WSi x grain structure after anneal (see FIG. 4 b ).
  • the grain size of the multi-layer WSi x after anneal is smaller than the prior art single WSi x layer after anneal, so that after anneal the surface of the multi-layer WSi x film of the present invention is smoother than the prior art single layer WSi x after anneal.
  • a first embodiment of the present invention illustrated in FIG. 4 a , comprises two WSi x layers, i.e., base layer 2 deposited on the semiconductor device and layer 1 , with layers 1 and 2 being separated by a W or Si layer 3 , resulting in a three-layer structure.
  • the thickness of layer 3 , W (or Si) is in the range of about T/5 to T/2.
  • the x-ratio of the base layer 2 can be identical to or greater than the x-ratio of layer 1 and the thickness of the layers can vary.
  • the x-ratio of the base layer 2 is greater than that of layer 1 to prevent unstable gate electricity and the thickness of the base layer 2 is thinner to achieve reduced resistivity of the film.
  • the final two-layer grain structure following subsequent thermal processing or anneal (>1000° C.), has two WSi x layers of different thicknesses.
  • the WSi x layers have different grain sizes resulting from their different thicknesses, and within each WSi x layer, the grain sizes are uniform.
  • the thickness of the base layer 2 is thinner than the other WSi x layer 1 to reduce resistivity of the multi-layered film with fixed total thickness T.
  • the resulting two-layer grain structure contains two layers of uniform grains 4 of smaller size than the grains of the single WSi x layer of the prior art shown in FIG. 1.
  • the W (or Si) layer is of sufficient thickness so that nucleation occurs in the WSi x and W (or Si) interfaces.
  • FIG. 4 b A second embodiment of the present invention is illustrated in FIG. 4 b .
  • This second embodiment comprises a fixed total thickness T of at least three WSi x layers, i.e., layers 5 , 6 and base layer 7 .
  • the WSi x layers 5 and 6 are separated by a very thin W or Si layer 8
  • the WSi x layers 6 and 7 are separated by very thin W or Si layer 9 .
  • the thickness of each W or Si layer is in the range of about 10 ⁇ to 20 ⁇ .
  • This five-layer structure becomes a multi-layer structure after subsequent thermal processing (or annealing) and since the thickness of W or Si layer 8 , 9 is very thin, the nucleation occurs in each W or Si layer itself.
  • each layer of the resulting WSi x layers contains uniform grains 10 which are of smaller size than the grains of a comparable single WSi x layer of the prior art and which are of comparable size to the grains achieved by using the three-layer WSi x structure of the first embodiment.
  • the x-ratios and thicknesses of WSi x layers 5 , 6 and 7 may be the same or different, but in a preferred embodiment the x-ratio of the base layer 7 is higher than each of the other WSi x layers to prevent unstable gate electricity and the thickness of the base layer 7 is thinner than each of the other WSi x layers to reduce resistivity of this multi-layer film having a fixed total thickness T.
  • the total thickness of layers 1 - 3 - 2 is in the range of about 400-1200 ⁇ .
  • the total thickness of layers 5 - 8 - 6 - 9 - 7 is in the range of about 400-1200 ⁇ .
  • a process for producing a three-layer WSi x structure is (a) WSi x deposition by CVD, (b- 1 ) W deposition by CVD or (b- 2 ) Si deposition by thermal decomposition, and (c) WSi x deposition by CVD, each according to the following constraints, as applicable:
  • Si film is deposited by thermal decomposition of SiH or SiH 2 Cl 2 in the range of about 400 to 600 degrees C.
  • a high flow rate (e.g., 100-300 sccm) of SiH 2 Cl 2 is needed to ensure that the deposited film is WSi x and not W.
  • WSi 2 forms with excess Si collecting in the grain boundaries. Since an excess of silicon exists in such films, the chemical formula to denote them is given as WSi x .
  • FIG. 5 shows a semiconductor device including a multilayered WSi x film 11 formed on a polysilicon layer 12 provided on silicon semiconductor body 13 such as a gate dielectric layer.
  • WSi x film 11 is formed on the polysilicon layer by either the process of FIG. 4 a or FIG. 4 b as described above.
  • the semiconductor device is an integrated circuit structure including a semiconductor substrate on which any combination of active and/or passive devices have already been formed and over which a polysilicon layer 12 will be formed to provide contacts and/or interconnects with the underlying integrated circuit structure.
  • the tungsten silicide layer 11 is formed on the polysilicon layer according to a process as described above.

Abstract

A method of forming a semiconductor device with a polysilicon layer having a multi-layer tungsten-silicide (WSix) film formed on a surface thereof includes the steps of (1) forming a first layer of tungsten-silicide on the surface of the polysilicon layer; (2) forming a second layer of a material selected from tungsten and silicon on the first layer; (3) forming a third layer of tungsten-silicide on the second layer; and (4) thermally treating the multi-layer film resulting from steps (a)-(c) to form a multi-layer WSix film on the surface of the polysilicon layer, the multi-layer WSix film having a uniform small grain size. In various embodiments, steps (1)-(3) may be repeated one or more times. A semiconductor device includes a semiconductor body having a polysilicon layer formed on a surface thereof and a multilayered WSix film formed on a surface of the polysilicon layer by the process described above.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to the field of semiconductor devices and methods of manufacture thereof. [0002]
  • 2. Description of Related Art [0003]
  • In general, gate structures of many semiconductor devices employ multiple layer gate and interconnect materials which maintain the properties of polycrystalline silicon but add a high-conductivity layer on top. For example, polysilicon and tungsten-silicide layers (WSi[0004] x) are commonly used for this purpose. That is, semiconductor devices that employ polycrystalline silicon (polysilicon) gates formed over a gate dielectric layer encounter increased resistance of the polysilicon as size is scaled down to achieve higher circuit density. Due to the resulting relatively high resistance values of the polysilicon layer, a tungsten silicide (WSix) layer is often formed in order to lower resistance along the polysilicon gate. Generally, the ratio of silicon to tungsten is approximately 2.6 to 1 within the tungsten silicide (WSix) layer. Initially, problems emerged with adhesion of the metal silicide to the polysilicon.
  • One method for making semiconductor devices of higher density and improved performance is disclosed by McPherson (U.S. Pat. No. 4,816,425). McPherson teaches a semiconductor device having a [0005] gate 11 comprising a multi-layer structure including a layer 11 a of polycrystalline silicon with an overlying layer of refractory metal silicide 11 b, such as MoSi2 or WSi2. In McPherson, the problem of adhesion of the metal silicide to the polysilicon is addressed by forming a thin silicon oxide coating 11 c on the polysilicon before sputtering the metal silicide layer. The resulting multi-layer structure has low resistance but retains the advantages of polysilicon on silicon.
  • Chung (U.S. Pat. No. 5,646,070) teaches a single process for creating a multi-layered semiconductor device that employs tungsten silicide but incorporates an intervening layer that prevents degradation of the electrical properties of the underlying silicide during the fabrication process. Since CVD-tungsten involves fluorine chemistry, such a protective layer prevents the interaction during fabrication of the vapor deposited by CVD-tungsten with the underlying silicide. [0006]
  • Neither of these multi-layer methods addresses modifying the WSi[0007] x layer itself to increase device density or speed. Further reducing semiconductor dimensions while maintaining or increasing performance is an on-going objective of semiconductor device design. Because of the large number of gates employed in semiconductor devices, a reduction in gate size can result in a substantial reduction in the overall dimensions of the semiconductor device accompanied by increased device density and even increased device speed.
  • The shrinkage of gate dimension increases resistivity and decreases speed. There are two usual approaches for decreasing resistivity. The first approach decreases the x-ratio, and the second approach increases the thickness of WSi[0008] x. However, these two approaches increase the grain size of WSix and result in a rough surface. In particular, a decrease in x-ratio from x=2.3 to x=2.1 actually increases WSix grain size after anneal. This increase in WSix grain size results in increased surface roughness. Also, increased thin film grain size results in increased side-wall roughness after gate conductor (GC) etching as well as increased likelihood of gate conductor side-wall extension, thereby reducing realizable device density. The lowering of the x-ratio is not feasible as an approach to achieving a decrease in WSix thickness, because of these undesirable increases in surface and side-wall roughness.
  • The conventional structure of WSi[0009] x film employed in semiconductor devices is a single layer. After the anneal step of a typical semiconductor thin film fabrication process employing a single WSix layer, WSix grains grow larger and aggregate in a single grain layer with the grain boundary reaching to the Poly/WSix and WSix/SiN interfaces. These larger grains introduce a WSix surface with significant roughness, which results in semiconductor devices with reduced gate density. The roughness after anneal of a prior art WSix film with x-ratio of 2.59 and with a thickness of THK=598.6 nm is unacceptable.
    • SUMMARY OF THE INVENTION
  • The present invention provides a method of preparing small grain size WSi[0010] x structures in general, and in particular, of preparing gate conductors.
  • The present invention provides a method of decreasing resistivity but preventing larger grain size by introducing a multilayer structure of WSi[0011] x.
  • More particularly, the present invention is directed to a method for manufacturing a WSi[0012] x film with smaller grains by providing a multi-layer WSix structure. The WSix film is prepared with smaller grains after anneal by introducing a multi-layer WSix structure prior to anneal. Instead of the single WSix layer of the prior art, the present invention introduces a multi-layer WSix structure at deposition, so that a multi-layer WSix grain structure with each layer having a smaller and more uniform grain size results after anneal.
    •  BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates the rough surface of a single WSi[0013] x thin film grown according to the prior art.
  • FIG. 2 illustrates the actual surface roughness after anneal of a single layer WSi[0014] x film.
  • FIG. 3 illustrates actual reduced surface roughness after anneal of a multi-layer WSi[0015] x film according to the present invention.
  • FIG. 4[0016] a illustrates the reduced grain size WSix film resulting after anneal from a first embodiment of the present invention which is directed to an initial three-layer WSix structure.
  • FIG. 4[0017] b illustrates the reduced grain size WSix film resulting after anneal from a second embodiment of the present invention which is directed to a five-layer WSix structure.
  • FIG. 5 shows a semiconductor device with a multi-layered WSi[0018] x film formed on a semiconductor body, according to the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The method of the present invention achieves multi-layer uniform small grain WSi[0019] x films which result from depositing several thin WSix layers separated by a single Si or W layer between each thin WSix layer. In a first aspect of the present invention, at anneal the nucleation site occurs at each WSix/W or WSix/Si interface of the multi-layer WSix structure, resulting in a multi-layer WSix grain structure after anneal (see FIG. 4a). In a second aspect of the present invention, the thickness of the W or Si layer interposed between the WSix layers is very thin, at anneal the nucleation site is in the W or Si layer, resulting in a multi-layer WSix grain structure after anneal (see FIG. 4b). Further, the grain size of the multi-layer WSix after anneal is smaller than the prior art single WSix layer after anneal, so that after anneal the surface of the multi-layer WSix film of the present invention is smoother than the prior art single layer WSix after anneal.
  • FIG. 3 shows a multi-layer WSi[0020] x structure with an x-ratio of 1.98, THK (dimension shape thickness)=798.9 nm after anneal (830 degrees C/60 seconds and 1080 degrees C/94 seconds) according to the present invention. This structure, after anneal, is smoother than the single WSix structure shown in prior art FIG. 2 where the x-ratio=2.59, and THK=598.6 nm after anneal (830 degrees C/60 seconds and 1080 degrees C/94 seconds). As noted, the smoother two-layer WSix structure of FIG. 3 has a thickness of THK=798.9 nm, compared to a thickness of THK=598.9 nm of the single layer WSix film of the prior art, thereby demonstrating its smaller WSix grain size.
  • Preferred embodiments of the present invention employ multiple WSi[0021] x layers separated by W or Si layers. A first embodiment of the present invention, illustrated in FIG. 4a, comprises two WSix layers, i.e., base layer 2 deposited on the semiconductor device and layer 1, with layers 1 and 2 being separated by a W or Si layer 3, resulting in a three-layer structure. In this embodiment, if the total thickness of layers 1, 2 and 3 is T, the thickness of layer 3, W (or Si), is in the range of about T/5 to T/2. The x-ratio of the base layer 2 can be identical to or greater than the x-ratio of layer 1 and the thickness of the layers can vary. In a preferred embodiment, the x-ratio of the base layer 2 is greater than that of layer 1 to prevent unstable gate electricity and the thickness of the base layer 2 is thinner to achieve reduced resistivity of the film. Thus, in the preferred embodiment, the final two-layer grain structure, following subsequent thermal processing or anneal (>1000° C.), has two WSix layers of different thicknesses. The WSix layers have different grain sizes resulting from their different thicknesses, and within each WSix layer, the grain sizes are uniform. Also, in a preferred embodiment, the thickness of the base layer 2 is thinner than the other WSix layer 1 to reduce resistivity of the multi-layered film with fixed total thickness T. When the thicknesses of the two WSix layers 1 and 2 are equal, the resulting two-layer grain structure, as shown in FIG. 4a, contains two layers of uniform grains 4 of smaller size than the grains of the single WSix layer of the prior art shown in FIG. 1. The W (or Si) layer is of sufficient thickness so that nucleation occurs in the WSix and W (or Si) interfaces.
  • A second embodiment of the present invention is illustrated in FIG. 4[0022] b. This second embodiment comprises a fixed total thickness T of at least three WSix layers, i.e., layers 5, 6 and base layer 7. The WSix layers 5 and 6 are separated by a very thin W or Si layer 8, and the WSix layers 6 and 7 are separated by very thin W or Si layer 9. The thickness of each W or Si layer is in the range of about 10 Å to 20 Å. This five-layer structure becomes a multi-layer structure after subsequent thermal processing (or annealing) and since the thickness of W or Si layer 8, 9 is very thin, the nucleation occurs in each W or Si layer itself. The grain structure of each layer of the resulting WSix layers contains uniform grains 10 which are of smaller size than the grains of a comparable single WSix layer of the prior art and which are of comparable size to the grains achieved by using the three-layer WSix structure of the first embodiment. The x-ratios and thicknesses of WSix layers 5, 6 and 7 may be the same or different, but in a preferred embodiment the x-ratio of the base layer 7 is higher than each of the other WSix layers to prevent unstable gate electricity and the thickness of the base layer 7 is thinner than each of the other WSix layers to reduce resistivity of this multi-layer film having a fixed total thickness T.
  • It should be noted that in FIG. 4[0023] a, the total thickness of layers 1-3-2 is in the range of about 400-1200 Å. In FIG. 4b, the total thickness of layers 5-8-6-9-7 is in the range of about 400-1200 Å.
  • According to a preferred embodiment, a process for producing a three-layer WSi[0024] x structure is (a) WSix deposition by CVD, (b-1) W deposition by CVD or (b-2) Si deposition by thermal decomposition, and (c) WSix deposition by CVD, each according to the following constraints, as applicable:
  • WSi[0025] x
  • (1.5-5 sccm gas)WF[0026] 6+(60-200 sccm gas)SiH2Cl2; in a range of about 400-600 degrees C., for a total thickness of WSix of about 400-1200 Å; in a range of 1-1.7 Torr; it should be noted that process time depends upon thickness and recipe.
  • W [0027]
  • (100-140 sccm gas)WF[0028] 6+(60-200 sccm gas)H2; in a range of about 400-600 degrees C.; in a range of 30-90 Torr.
  • Si [0029]
  • Si film is deposited by thermal decomposition of SiH or SiH[0030] 2Cl2 in the range of about 400 to 600 degrees C.
  • A high flow rate (e.g., 100-300 sccm) of SiH[0031] 2Cl2 is needed to ensure that the deposited film is WSix and not W. During film deposition, WSi2 forms with excess Si collecting in the grain boundaries. Since an excess of silicon exists in such films, the chemical formula to denote them is given as WSix.
  • FIG. 5 shows a semiconductor device including a multilayered WSi[0032] x film 11 formed on a polysilicon layer 12 provided on silicon semiconductor body 13 such as a gate dielectric layer. WSix film 11 is formed on the polysilicon layer by either the process of FIG. 4a or FIG. 4b as described above. The semiconductor device is an integrated circuit structure including a semiconductor substrate on which any combination of active and/or passive devices have already been formed and over which a polysilicon layer 12 will be formed to provide contacts and/or interconnects with the underlying integrated circuit structure. The tungsten silicide layer 11 is formed on the polysilicon layer according to a process as described above.
  • From the foregoing, it will be apparent to those skilled in the art that, although the present invention has been fully described by way of examples with reference to the accompanying drawings, numerous modifications, substitutions and variations, as well as rearrangements and combinations, of the preceding illustrative embodiments can be made without departing from the spirit and scope of the novel aspects of the present invention. It is to be understood that no limitation of the scope of the present invention with respect to the specific embodiments illustrated is intended or should be inferred, but the scope of the present invention is to be defined solely by the attached claims. [0033]

Claims (26)

What is claimed is:
1. A method of forming a semiconductor device having a multi-layer tungsten-silicide (WSix) film formed on a surface thereof, said method comprising the steps of:
(a) providing a semiconductor substrate having a surface;
(b) forming a first layer of tungsten-silicide on the surface;
(c) forming a second layer of a material selected from tungsten and silicon on said first layer;
(d) forming a third layer of tungsten-silicide on said second layer; and
(e) thermally treating the multi-layer film resulting from steps (a)-(d) to form a WSix film having a plurality of layers, each layer of said plurality of layers having a uniform grain size.
2. A method according to claim 1, comprising repeating steps (c)-(d) one or more times.
3. A method according to claim 1, wherein steps (b) and (d) comprise chemical vapor deposition according to the chemical formula:
(1.5-5 sccm gas)WF6+(60-200 sccm gas)SiH2Cl2, at a temperature in the range of about 400-600 degrees C. and a pressure in the range of about 1-1.7 Torr.
4. A method according to claim 2, wherein step (b) comprises one of:
(i) depositing said tungsten layer by chemical vapor deposition according to the formula (100-140 sccm gas)WF6+(60-200 sccm gas)H2, at a temperature in the range of about 400-600 degrees C. and at a pressure in the range of about 30-90 Torr; and
(ii) depositing said silicon layer by thermal decomposition of one of SiH and SiH2Cl2 at a temperature in the range of about 400-600 degrees C.
5. A method according to claim 4, wherein a total thickness of said first layer deposited by step (b) and all repetitions of steps (c)-(d) is in a range of about 400-1200 Å.
6. A method according to claim 5, wherein step (e) comprises an annealing process at greater than about 1000 degrees C.
7. A method according to claim 4, wherein step (c) comprises one of depositing tungsten in a thickness in the range of about 10 Å to 20 Å and depositing silicon in a thickness in the range of about 10 Å to 20 Å.
8. A method according to claim 1, wherein a total thickness of said first, second and third layers is T, and said second layer is of thickness in a range of about T/5 to T/2.
9. A method according to claim 8, wherein a total thickness of said first, second and third layers is in a range of about 400-1200 Å.
10. A method according to claim 8, wherein step (d) comprises an annealing process at greater than 1000 degrees C.
11. A method according to claim 1, wherein said semiconductor device is provided with a polysilicon layer with said multi-layer tungsten-silicide (WSix) film formed on a surface of said polysilicon layer.
12. A method according to claim 1, wherein said first layer is disposed on said surface of said semiconductor device and said first layer is thinner and has a higher x-ratio than said third layer.
13. A method according to claim 2, wherein said layer formed by step (b) is thinner and has a higher x-ratio than each said layer formed by step (d).
14. A semiconductor device comprising a semiconductor body having a surface and a multilayered WSix film formed on said surface, said multilayered WSix film being formed on said surface by a process comprising the steps of:
(a) forming a first layer of tungsten-silicide on the surface of said surface;
(b) forming a second layer of a material selected from tungsten and silicon on said first layer;
(c) forming a third layer of tungsten-silicide on said second layer; and
(d) thermally treating the multi-layer film resulting from steps (a)-(c) to form WSix film having a plurality of layers, each layer of said plurality of layers having a uniform grain size.
15. A semiconductor device according to claim 14, comprising repeating steps (b)-(c) one or more times.
16. A semiconductor device according to claim 14, wherein steps (a) and (c) comprise chemical vapor deposition according to the chemical formula:
(1.5-5 sccm gas)WF6+(60-200 sccm gas)SiH2Cl2, at a temperature in the range of about 400-600 degrees C. and a pressure in the range of about 1-1.7 Torr.
17. A semiconductor device according to claim 15, wherein step (b) comprises one of:
(i) depositing said tungsten layer by chemical vapor deposition according to the formula (100-140 sccm gas)WF6 +(60-200 sccm gas)H2, at a temperature in the range of about 400-600 degrees C. and at a pressure in the range of about 30-90 Torr; and
(ii) depositing said silicon layer by thermal decomposition of one of SiH and SiH2Cl2 at a temperature in the range of about 400-600 degrees C.
18. A semiconductor device according to claim 17, wherein a total thickness of said first layer deposited by step (a) and layers provided by all repetitions of steps (b) (c) is in the range from 400-1200 Å.
19. A semiconductor device according to claim 18, wherein step (d) comprises an annealing process at greater than 1000 degrees C.
20. A semiconductor device according to claim 17, wherein step (b) comprises one of depositing tungsten in a thickness in the range of about 10 Å to 20 Å and depositing silicon in a thickness in the range of about 10 Å to 20 Å.
21. A semiconductor device according to claim 14, wherein a total thickness of said first, second and third layers is T, and said second layer is of thickness in a range of about T/5 to T/2.
22. A semiconductor device according to claim 21, wherein step (d) comprises an annealing process at greater than 1000 degrees C.
23. A semiconductor device according to claim 14, wherein a total thickness of said first, second and third layers is in the range from 400-1200 Å.
24. A semiconductor device according to claim 14, wherein said semiconductor device is provided with a polysilicon layer on a surface of said semiconductor device and said multi-layer tungsten-silicide (WSix) film is formed on a surface of said polysilicon layer.
25. A semiconductor device according to claim 14, wherein said first layer is disposed on said surface of said semiconductor device and said first layer is thinner and has a higher x-ratio than said third layer.
26. A semiconductor device according to claim 15, wherein said layer formed by step (a) is thinner and has a higher x-ratio than each said layer formed by step (c).
US10/301,707 2001-04-20 2002-11-22 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon Abandoned US20030100184A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/301,707 US20030100184A1 (en) 2001-04-20 2002-11-22 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW090109502A TW502337B (en) 2001-04-20 2001-04-20 Method for reducing WSix grain and its structure
TW90109502 2001-04-20
US09/909,816 US6551928B2 (en) 2001-04-20 2001-07-23 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure
US10/301,707 US20030100184A1 (en) 2001-04-20 2002-11-22 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/909,816 Division US6551928B2 (en) 2001-04-20 2001-07-23 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure

Publications (1)

Publication Number Publication Date
US20030100184A1 true US20030100184A1 (en) 2003-05-29

Family

ID=21678020

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/909,816 Expired - Lifetime US6551928B2 (en) 2001-04-20 2001-07-23 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure
US10/301,707 Abandoned US20030100184A1 (en) 2001-04-20 2002-11-22 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/909,816 Expired - Lifetime US6551928B2 (en) 2001-04-20 2001-07-23 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure

Country Status (3)

Country Link
US (2) US6551928B2 (en)
DE (1) DE10145960B4 (en)
TW (1) TW502337B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204285A (en) * 2017-07-07 2017-09-26 睿力集成电路有限公司 The grid conducting layer of film, its forming method and its formation

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541280B2 (en) * 2004-08-13 2009-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of foming a micromechanical structure
KR100671627B1 (en) * 2004-10-25 2007-01-19 주식회사 하이닉스반도체 Method of forming source contact in flash memory device
CN103811317A (en) * 2012-11-07 2014-05-21 上海华虹宏力半导体制造有限公司 Method for improving gate leakage of MOS tube
CN104241103A (en) * 2013-06-14 2014-12-24 无锡华润上华科技有限公司 Method for manufacturing WSI composite gate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631479A (en) * 1995-04-26 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with laminated refractory metal schottky barrier gate electrode

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816425A (en) 1981-11-19 1989-03-28 Texas Instruments Incorporated Polycide process for integrated circuits
EP0491433A3 (en) 1990-12-19 1992-09-02 N.V. Philips' Gloeilampenfabrieken Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region
US5643633A (en) * 1992-12-22 1997-07-01 Applied Materials, Inc. Uniform tungsten silicide films produced by chemical vapor depostiton
TW379374B (en) * 1998-06-19 2000-01-11 Siemens Ag Method to improve thermal stability of tungsten silicide
US6210813B1 (en) * 1998-09-02 2001-04-03 Micron Technology, Inc. Forming metal silicide resistant to subsequent thermal processing

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631479A (en) * 1995-04-26 1997-05-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with laminated refractory metal schottky barrier gate electrode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107204285A (en) * 2017-07-07 2017-09-26 睿力集成电路有限公司 The grid conducting layer of film, its forming method and its formation
CN107204285B (en) * 2017-07-07 2018-03-30 睿力集成电路有限公司 The grid conducting layer of film, its forming method and its formation

Also Published As

Publication number Publication date
US6551928B2 (en) 2003-04-22
US20020155704A1 (en) 2002-10-24
DE10145960A1 (en) 2002-10-31
TW502337B (en) 2002-09-11
DE10145960B4 (en) 2007-02-15

Similar Documents

Publication Publication Date Title
US6555471B2 (en) Method of making a void-free aluminum film
US6447933B1 (en) Formation of alloy material using alternating depositions of alloy doping element and bulk material
US5700718A (en) Method for increased metal interconnect reliability in situ formation of titanium aluminide
US20040058531A1 (en) Method for preventing metal extrusion in a semiconductor structure.
EP0735586A2 (en) Semi-conductor structures
US20020017724A1 (en) Chemical vapor deposition of titanium
KR0148325B1 (en) Formation method of metal layer in semiconductor device
US20070026671A1 (en) Method of forming low resistance tungsten films
JPH09199594A (en) Method for forming metal wirings of semiconductor element and wiring structure thereof
US6551928B2 (en) Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure
US8008774B2 (en) Multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same
CN101572252A (en) Etching stopping layer, semiconductor device with through hole and method for forming same two
EP1164630B1 (en) Silicide process having a variable silicon/metal ratio
US20030186498A1 (en) Method for fabricating metal interconnection with reliability using ionized physical vapor deposition
US6586320B2 (en) Graded/stepped silicide process to improve mos transistor
US5946599A (en) Method of manufacturing a semiconductor IC device
JP3328358B2 (en) Method for manufacturing semiconductor device
US7951713B2 (en) Method of forming metal wiring in semiconductor device
EP0839927A2 (en) Method of forming films comprising TiN and Al
US20050181600A1 (en) Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate
KR100523658B1 (en) Method for manufacturing copper diffusion barrier
JPH02188921A (en) Formation of high-melting-point-metal multilayer film
US6309963B1 (en) Method for manufacturing semiconductor device
KR940000505B1 (en) Multilayer tungsten-silicide and method of the same
JP2002353166A (en) Method of shrinking grain size of tungsten silicide, multilayer structure of tungsten silicide, and two-layer structure of tungsten-silicide crystalline grains

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION