US20030094981A1 - Chopper type comparator - Google Patents
Chopper type comparator Download PDFInfo
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- US20030094981A1 US20030094981A1 US10/197,432 US19743202A US2003094981A1 US 20030094981 A1 US20030094981 A1 US 20030094981A1 US 19743202 A US19743202 A US 19743202A US 2003094981 A1 US2003094981 A1 US 2003094981A1
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- 239000000758 substrate Substances 0.000 claims description 36
- 239000003990 capacitor Substances 0.000 claims description 24
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000003111 delayed effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000000638 solvent extraction Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
Definitions
- This invention relates to a chopper type comparator.
- an object of the present invention is to provide a chopper type comparator in which an offset difference is reduced.
- a chopper type comparator includes an input switch circuit which inputs an input voltage and a reference voltage alternately in response to a control signal; an output terminal which supplies an output voltage, having a level defined based on the difference between the input voltage and the reference voltage; a capacitor which is coupled between the input switch circuit and the output terminal; and a node which is coupled between the capacitor and the output terminal; a first inverter coupled between the node and the output terminal.
- the comparator further includes a first MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the first MOS transistor having a substrate voltage terminal; a supply terminal which provides a supply voltage; a bias control circuit which selectively connects the substrate voltage terminal of the first MOS transistor to the supply terminal and the output terminal in response to the control signal; and a timing control circuit which provide a delay to the control signal to be supplied to the first MOS transistor and the input switch circuit.
- a chopper type comparator includes an input switch circuit which inputs an input voltage and a reference voltage alternately in response to a control signal; an output terminal which supplies an output voltage, having a level defined based on the difference between the input voltage and the reference voltage; a capacitor which is coupled between the input switch circuit and the output terminal; a node which is coupled between the capacitor and the output terminal; a first inverter coupled between the node and the output terminal; a first MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the first MOS transistor having a substrate voltage terminal; a second MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the second MOS transistor having a substrate voltage terminal; and a supply terminal which provides a supply voltage.
- the comparator further includes a first bias control circuit which selectively connects the substrate voltage terminal of the first MOS transistor to the supply terminal and the output terminal in response to the control signal; a second bias control circuit which selectively connects the substrate voltage terminal of the second MOS transistor to the supply terminal and the output terminal in response to the control signal; and a timing control circuit which provide a delay to the control signal to be supplied to the first MOS transistor, the first bias control circuit and the input switch circuit.
- FIG. 1 is a circuit diagram showing a chopper type comparator.
- FIG. 2 is a circuit diagram showing a chopper type comparator according to the present invention.
- FIG. 3 is a timing chart showing operation of the chopper type comparator, shown in FIG. 2.
- FIG. 4 is a circuit diagram showing a chopper type comparator according to the present invention.
- FIG. 1 shows a chopper type comparator, which includes an input terminal 1 and an input switch circuit 2 .
- An input voltage Vi is applied to the input terminal 1 .
- the input terminal 1 is connected to an input of the input switch circuit 2 .
- the input switch circuit 2 includes another input terminal to which a reference voltage Vr is applied.
- the input switch circuit 2 is supplied with a clock signal CK, which functions as a switching control signal.
- the input switch circuit 2 has an output terminal connected to a terminal of a capacitor 3 .
- the other terminal of the capacitor 3 is connected to an internal node NA.
- the node NA is connected to an input terminal of an inverter 4 .
- An output of the inverter 4 is connected to an output terminal 5 .
- the chopper type comparator also includes a P channel MOS transistor (PMOS) 6 , which is connected between the node NA and the output terminal 5 .
- the PMOS transistor 6 is turned on and off in response to the clock signal CK.
- the comparator further includes another two PMOS transistors 7 and 8 , and another inverter 9 .
- the PMOS transistor 7 is connected between a drain of the PMOS transistor 6 and a substrate of the PMOS transistor 6 .
- the PMOS transistor 8 is connected between a supply terminal VDD and the substrate of the PMOS transistor 6 .
- the clock signal CK is supplied to a gate of the PMOS transistor 7 .
- An input terminal of the inverter 9 is supplied with the clock signal CK, while an output terminal of the inverter 9 is connected to a gate of the PMOS transistor 8 .
- a reversed clock signal /CK is supplied to the gate of the PMOS transistor 8 .
- the input switch circuit 2 allows the input terminal 1 to be in connection.
- the clock signal CK is at “L”
- the PMOS transistors 6 and 7 are turned off, and the PMOS transistor 8 is turned on.
- a short circuit is generated between the input and output terminals of the inverter 4 via the PMOS transistor 6 .
- the PMOS transistor 7 Since the PMOS transistor 7 is turned on at the same time as the PMOS transistor 6 is turned on, the PMOS transistor 7 makes a substrate voltage of the PMOS 6 to a threshold voltage Vt, and prevents the threshold voltage Vt from increasing due to a substrate-bias effect.
- a voltage at the node NA is converged to the threshold voltage Vt promptly.
- the capacitor 3 charges at a voltage of “Vi ⁇ Vt”.
- the clock signal CK is turned to a higher level “H”, the input switch circuit 2 allows the reference voltage Vr to be inputted.
- the PMOS transistors 6 and 7 are turned off, and the PMOS transistor 8 is turned on.
- the input and output terminals of the inverter 4 are disconnected, so that the inverter 4 inverts and amplifies a voltage at the node NA.
- the PMOS transistor 8 is turned on, and the substrate voltage of the PMOS transistor 6 becomes the supply voltage VDD.
- the PMOS transistor 6 is turned off promptly.
- One side of the capacitor 3 is applied with the reference voltage Vr via the input switch circuit 2 , so that a voltage Vn at the node NA becomes “Vr ⁇ (Vi ⁇ Vt)”.
- a parasitic capacitance Cp is generated between a source and substrate of the PMOS transistor 6 .
- the clock signal CK is turned from “L” to “H” and the PMOS transistor 6 is turned off, charge partitioning is generated between the capacitor 3 and the parasitic capacitance Cp.
- a voltage at the node NA is shifted from the threshold voltage Vt. Therefore, when the difference between the input voltage Vi and reference voltage Vr is small, an operation error may be occurred due to an offset difference or discrepancy.
- FIG. 2 shows a chopper type comparator according to the present invention.
- the same or corresponding elements to those shown in FIG. 1 are represented by the same reference numerals, and the same description is not repeated.
- the chopper type comparator includes an input switch circuit 2 which inputs an input voltage signal Vi and a reference voltage Vr alternately in response to a clock signal CK; an output terminal 5 which supplies an output voltage OUT, having a level defined based on the difference between the input voltage Vi and the reference voltage Vr; a capacitor 3 which is coupled between the input switch circuit 2 and the output terminal 5 ; a node NA which is coupled between the capacitor 3 and the output terminal 5 ; a first inverter 4 coupled between the node NA and the output terminal 5 ; a first PMOS transistor 6 which is coupled between the node NA and the output terminal 5 in parallel to the first inverter 4 and operates in response to the clock signal CK, the first PMOS transistor 6 having a substrate voltage terminal; a supply terminal VDD which provides a supply voltage; a bias control circuit ( 7 and 8 ) which selectively connects the substrate voltage terminal of the first PMOS transistor 6 to the supply terminal VDD and the output terminal 5 in response to the clock signal CK; and a timing control
- the delay circuit 10 functions to delay the clock signal CK by a period of time “dt” to provide a delayed clock signal DCK, which is supplied to a gate of the PMOS transistor 6 and the input switch circuit 2 .
- An input voltage Vi is applied to the input terminal 1 .
- the input terminal 1 is connected to an input of the input switch circuit 2 .
- the input switch circuit 2 includes another input terminal to which a reference voltage Vr is applied.
- the input switch circuit 2 is supplied with the clock signal CK, which functions as a switching control signal.
- the input switch circuit 2 has an output terminal connected to a terminal of the capacitor 3 .
- the other terminal of the capacitor 3 is connected to the internal node NA.
- the node NA is connected to an input terminal of the inverter 4 .
- An output of the inverter 4 is connected to the output terminal 5 .
- the PMOS 6 is turned on and off in response to the clock signal CK.
- the comparator further includes another two PMOS transistors 7 and 8 , and another inverter 9 .
- the PMOS transistor 7 is connected between a drain of the PMOS transistor 6 and the substrate voltage terminal of the PMOS transistor 6 .
- the PMOS transistor 8 is connected between a supply terminal VDD and the substrate voltage terminal of the PMOS transistor 6 .
- the clock signal CK is supplied to a gate of the PMOS transistor 7 .
- An input terminal of the inverter 9 is supplied with the clock signal CK, while an output terminal of the inverter 9 is connected to a gate of the PMOS transistor 8 .
- a reversed clock signal /CK is supplied to the gate of the PMOS transistor 8 .
- a substrate of the PMOS transistor 7 is connected to a source thereof, and a substrate of the PMOS transistor 8 is connected to a source thereof.
- the clock signal CK is turned to a higher level “H”
- the PMOS transistor 7 is turned off and the PMOS transistor 8 is turned on.
- the substrate voltage of the PMOS transistor 6 is increased to the supply voltage VDD.
- a voltage Vn at the node NA is changed in accordance with a parasitic capacitance Cp, which is generated between a source and a substrate of the PMOS transistor 6 .
- the delayed clock signal DCK supplied to the PMOS transistor is still at a lower level “L”, the PMOS transistor 6 maintains to be in a on state.
- the voltage Vn at the node NA is returned to the threshold voltage Vt of the inverter 4 after a small range of variation. Therefore, a voltage “Vi ⁇ Vt” charged at the capacitor 3 is not changed in level.
- a delayed clock signal is supplied to the input switch circuit 2 and the PMOS transistor 6 , while a regular clock signal CK is supplied to the PMOS transistor 7 and 8 .
- a regular clock signal CK is supplied to the PMOS transistor 7 and 8 .
- FIG. 4 shows another chopper type comparator according to the present invention.
- the same and corresponding elements to those in FIGS. 1 and 2 are represented by the same reference symbols and the same description is not repeated.
- the comparator includes an input terminal 1 , an input switch circuit 2 , a capacitor 3 , an inverter 4 , an output terminal 5 and a delay circuit 10 .
- the comparator further includes a first switch circuit ( 6 a , 7 a , 8 a and 9 a ) and a second switch circuit ( 6 b , 7 b , 8 b and 9 b ), each of which operates to turn on and off the inverter 4 .
- the input switch circuit 2 inputs an input voltage Vi and a reference voltage Vr alternately in response to a delayed clock signal DCK.
- the output terminal 5 supplies an output voltage, having a level defined based on the difference between the input voltage Vi and the reference voltage Vr.
- the capacitor 3 is coupled between the input switch circuit and the output terminal.
- a node NA is coupled between the capacitor 3 and the output terminal 5 .
- the inverter 4 is coupled between the node NA and the output terminal 5 .
- the first switch circuit include a first PMOS transistor 6 a and a first bias control circuit, which includes PMOS transistors 7 a and 8 a and an inverter 9 a .
- the first PMOS transistor 6 a is coupled between the node NA and the output terminal 5 in parallel to the inverter 4 .
- the first bias control circuit ( 7 a , 8 a and 9 a ) selectively connects the substrate voltage terminal of the first PMOS transistor 6 a to the supply terminal VDD and the output terminal 5 in response to the delay clock signal DCK.
- the second switch circuit include a second PMOS transistor 6 b and a second bias control circuit, which includes PMOS transistors 7 b and 8 b and an inverter 9 b .
- the second PMOS transistor 6 b is coupled between the node NA and the output terminal 5 in parallel to the inverter 4 .
- Each of gate widths of the PMOS transistors 6 a and 6 b are determined to be a half of a gate width of the PMOS transistor 6 , shown in FIG. 2.
- the second bias control circuit ( 7 b , 8 b and 9 b ) selectively connects the substrate voltage terminal of the second PMOS transistor 6 b to the supply terminal VDD and the output terminal 5 in response to the delay clock signal DCK.
- the PMOS transistors 6 a , 6 b , 7 a and 7 b are turned on, and the PMOS transistors 8 a and 8 b are turned off, so that the node NA has a voltage potential corresponding to a threshold voltage Vt of the inverter 4 .
- the PMOS transistors 6 b and 7 b are turned off, and the PMOS transistor 8 b is turned on.
- a voltage at the node NA is changed in a small range due to a parasitic capacitance Cpb, generated between a source and a substrate of the PMOS transistor 6 b and charge partitioning, generated between the node and the capacitance 3 .
- a voltage at the node NA reestablishes to the threshold voltage Vt, since the PMOS transistor 6 a is in an on state.
- the PMOS transistors 6 a and 7 a are turned off, and the PMOS transistor 8 a is turned on.
- a voltage at the node NA is changed in a small range due to a parasitic capacitance Cpb, generated between a source and a substrate of the PMOS transistor 6 a and charge partitioning, generated between the node and the capacitance 3 .
- Such a voltage change at the node NA is small, because the PMOS transistor 6 a has a gate width that is a half of the PMOS transistor 6 , shown in FIG. 2, and a parasitic capacitance should also be a half of the comparator shown in FIG. 2.
- a couple of PMOS transistors 6 a and 6 b are used in place of a single PMOS transistor 6 , shown in FIGS. 1 and 2, and each of the PMOS transistors 6 a and 6 b has a gate width that is a half of a gate width of the PMOS transistor 6 .
- the PMOS transistors 6 a and 6 b operate at different timing.
- each of parasitic capacitances Cpa and Cpb is a half of Cp, shown in FIGS. 1 and 2, so that voltage change at the node NA is suppressed.
- the input switch circuit 2 can be designed to connect the input terminal 1 and the capacitor 3 when the PMOS transistor 6 is in an off state. It can replace with the PMOS transistors 6 - 8 , 6 a - 8 a and 6 b - 8 b and NMOS transistors are employed.
- the PMOS transistors 6 a and 6 b can have different gate widths.
- the gate width of the PMOS transistor 6 a is determined to be smaller than that of the PMOS transistor 6 b in order that a voltage variation at the node NA can be more decreased.
Abstract
Description
- This application claims the priority of Application No. 2001-354941, filed Nov. 20, 2001 in Japan, the subject matter of which is incorporated herein by reference.
- This invention relates to a chopper type comparator.
- In a chopper type comparator, an input voltage and a predetermined reference voltage is compared and an output voltage corresponding to the reference between the input voltage and the reference voltage is generated. Recently, it is required to reduce an offset difference of an output voltage.
- Accordingly, an object of the present invention is to provide a chopper type comparator in which an offset difference is reduced.
- Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
- According to a first aspect of the present invention, a chopper type comparator includes an input switch circuit which inputs an input voltage and a reference voltage alternately in response to a control signal; an output terminal which supplies an output voltage, having a level defined based on the difference between the input voltage and the reference voltage; a capacitor which is coupled between the input switch circuit and the output terminal; and a node which is coupled between the capacitor and the output terminal; a first inverter coupled between the node and the output terminal.
- The comparator further includes a first MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the first MOS transistor having a substrate voltage terminal; a supply terminal which provides a supply voltage; a bias control circuit which selectively connects the substrate voltage terminal of the first MOS transistor to the supply terminal and the output terminal in response to the control signal; and a timing control circuit which provide a delay to the control signal to be supplied to the first MOS transistor and the input switch circuit.
- According to a second aspect of the present invention, a chopper type comparator includes an input switch circuit which inputs an input voltage and a reference voltage alternately in response to a control signal; an output terminal which supplies an output voltage, having a level defined based on the difference between the input voltage and the reference voltage; a capacitor which is coupled between the input switch circuit and the output terminal; a node which is coupled between the capacitor and the output terminal; a first inverter coupled between the node and the output terminal; a first MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the first MOS transistor having a substrate voltage terminal; a second MOS transistor which is coupled between the node and the output terminal in parallel to the first inverter and operates in response to the control signal, the second MOS transistor having a substrate voltage terminal; and a supply terminal which provides a supply voltage.
- The comparator further includes a first bias control circuit which selectively connects the substrate voltage terminal of the first MOS transistor to the supply terminal and the output terminal in response to the control signal; a second bias control circuit which selectively connects the substrate voltage terminal of the second MOS transistor to the supply terminal and the output terminal in response to the control signal; and a timing control circuit which provide a delay to the control signal to be supplied to the first MOS transistor, the first bias control circuit and the input switch circuit.
- FIG. 1 is a circuit diagram showing a chopper type comparator.
- FIG. 2 is a circuit diagram showing a chopper type comparator according to the present invention.
- FIG. 3 is a timing chart showing operation of the chopper type comparator, shown in FIG. 2.
- FIG. 4 is a circuit diagram showing a chopper type comparator according to the present invention.
- In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims.
- FIG. 1 shows a chopper type comparator, which includes an
input terminal 1 and aninput switch circuit 2. An input voltage Vi is applied to theinput terminal 1. Theinput terminal 1 is connected to an input of theinput switch circuit 2. Theinput switch circuit 2 includes another input terminal to which a reference voltage Vr is applied. Theinput switch circuit 2 is supplied with a clock signal CK, which functions as a switching control signal. Theinput switch circuit 2 has an output terminal connected to a terminal of acapacitor 3. The other terminal of thecapacitor 3 is connected to an internal node NA. The node NA is connected to an input terminal of aninverter 4. An output of theinverter 4 is connected to anoutput terminal 5. - The chopper type comparator also includes a P channel MOS transistor (PMOS)6, which is connected between the node NA and the
output terminal 5. ThePMOS transistor 6 is turned on and off in response to the clock signal CK. The comparator further includes another twoPMOS transistors inverter 9. ThePMOS transistor 7 is connected between a drain of thePMOS transistor 6 and a substrate of thePMOS transistor 6. ThePMOS transistor 8 is connected between a supply terminal VDD and the substrate of thePMOS transistor 6. The clock signal CK is supplied to a gate of thePMOS transistor 7. An input terminal of theinverter 9 is supplied with the clock signal CK, while an output terminal of theinverter 9 is connected to a gate of thePMOS transistor 8. In other words, a reversed clock signal /CK is supplied to the gate of thePMOS transistor 8. - In the above-described chopper type comparator, when the clock signal CK is at a lower level “L”, the
input switch circuit 2 allows theinput terminal 1 to be in connection. When the clock signal CK is at “L”, thePMOS transistors PMOS transistor 8 is turned on. As a result, a short circuit is generated between the input and output terminals of theinverter 4 via thePMOS transistor 6. Since thePMOS transistor 7 is turned on at the same time as thePMOS transistor 6 is turned on, thePMOS transistor 7 makes a substrate voltage of thePMOS 6 to a threshold voltage Vt, and prevents the threshold voltage Vt from increasing due to a substrate-bias effect. A voltage at the node NA is converged to the threshold voltage Vt promptly. When a voltage at the node NA becomes Vt, thecapacitor 3 charges at a voltage of “Vi−Vt”. - After that, the clock signal CK is turned to a higher level “H”, the
input switch circuit 2 allows the reference voltage Vr to be inputted. At the same time, thePMOS transistors PMOS transistor 8 is turned on. As a result, the input and output terminals of theinverter 4 are disconnected, so that theinverter 4 inverts and amplifies a voltage at the node NA. At this time, thePMOS transistor 8 is turned on, and the substrate voltage of thePMOS transistor 6 becomes the supply voltage VDD. ThePMOS transistor 6 is turned off promptly. One side of thecapacitor 3 is applied with the reference voltage Vr via theinput switch circuit 2, so that a voltage Vn at the node NA becomes “Vr−(Vi−Vt)”. - When the voltage Vn at the node NA is higher than the threshold voltage Vt of the
inverter 4, that is, when the reference voltage Vr is larger than the input voltage Vi, a low level output signal OUT is outputted from theoutput terminal 5. On the other hand, when the voltage Vn at the node NA is lower than the threshold voltage Vt of theinverter 4, that is, when the reference voltage Vr is lower than the input voltage Vi, a high level output signal OUT is outputted from theoutput terminal 5. - According to the chopper type comparator, shown in FIG. 1, a parasitic capacitance Cp is generated between a source and substrate of the
PMOS transistor 6. When the clock signal CK is turned from “L” to “H” and thePMOS transistor 6 is turned off, charge partitioning is generated between thecapacitor 3 and the parasitic capacitance Cp. As a result, a voltage at the node NA is shifted from the threshold voltage Vt. Therefore, when the difference between the input voltage Vi and reference voltage Vr is small, an operation error may be occurred due to an offset difference or discrepancy. - FIG. 2 shows a chopper type comparator according to the present invention. In FIG. 2, the same or corresponding elements to those shown in FIG. 1 are represented by the same reference numerals, and the same description is not repeated.
- The chopper type comparator includes an
input switch circuit 2 which inputs an input voltage signal Vi and a reference voltage Vr alternately in response to a clock signal CK; anoutput terminal 5 which supplies an output voltage OUT, having a level defined based on the difference between the input voltage Vi and the reference voltage Vr; acapacitor 3 which is coupled between theinput switch circuit 2 and theoutput terminal 5; a node NA which is coupled between thecapacitor 3 and theoutput terminal 5; afirst inverter 4 coupled between the node NA and theoutput terminal 5; afirst PMOS transistor 6 which is coupled between the node NA and theoutput terminal 5 in parallel to thefirst inverter 4 and operates in response to the clock signal CK, thefirst PMOS transistor 6 having a substrate voltage terminal; a supply terminal VDD which provides a supply voltage; a bias control circuit (7 and 8) which selectively connects the substrate voltage terminal of thefirst PMOS transistor 6 to the supply terminal VDD and theoutput terminal 5 in response to the clock signal CK; and atiming control circuit 10 which provide a delay to the clock signal CK to be supplied to thefirst PMOS transistor 6 and theinput switch circuit 2. - The
delay circuit 10 functions to delay the clock signal CK by a period of time “dt” to provide a delayed clock signal DCK, which is supplied to a gate of thePMOS transistor 6 and theinput switch circuit 2. - An input voltage Vi is applied to the
input terminal 1. Theinput terminal 1 is connected to an input of theinput switch circuit 2. Theinput switch circuit 2 includes another input terminal to which a reference voltage Vr is applied. Theinput switch circuit 2 is supplied with the clock signal CK, which functions as a switching control signal. Theinput switch circuit 2 has an output terminal connected to a terminal of thecapacitor 3. The other terminal of thecapacitor 3 is connected to the internal node NA. The node NA is connected to an input terminal of theinverter 4. An output of theinverter 4 is connected to theoutput terminal 5. - The
PMOS 6 is turned on and off in response to the clock signal CK. The comparator further includes another twoPMOS transistors inverter 9. ThePMOS transistor 7 is connected between a drain of thePMOS transistor 6 and the substrate voltage terminal of thePMOS transistor 6. ThePMOS transistor 8 is connected between a supply terminal VDD and the substrate voltage terminal of thePMOS transistor 6. The clock signal CK is supplied to a gate of thePMOS transistor 7. An input terminal of theinverter 9 is supplied with the clock signal CK, while an output terminal of theinverter 9 is connected to a gate of thePMOS transistor 8. In other words, a reversed clock signal /CK is supplied to the gate of thePMOS transistor 8. A substrate of thePMOS transistor 7 is connected to a source thereof, and a substrate of thePMOS transistor 8 is connected to a source thereof. - As shown in FIG. 3, in the above-described chopper type comparator, when the clock signal CK is at a lower level “L”, the
input switch circuit 2 allows theinput terminal 1 to be in connection. When the clock signal CK is at “L”, thePMOS transistors PMOS transistor 8 is turned on. As a result, the input and output terminals of theinverter 4 are connected via thePMOS transistor 6. A voltage Vn at the node NA is converged to a threshold voltage Vt of theinverter 4. Therefore, an output signal OUT having a level Vt is outputted. A voltage at the node NA is converged to the threshold voltage Vt promptly. When a voltage at the node NA becomes Vt, thecapacitor 3 charges at a voltage of “Vi−Vt”. - After that, the clock signal CK is turned to a higher level “H”, the
PMOS transistor 7 is turned off and thePMOS transistor 8 is turned on. As a result, the substrate voltage of thePMOS transistor 6 is increased to the supply voltage VDD. A voltage Vn at the node NA is changed in accordance with a parasitic capacitance Cp, which is generated between a source and a substrate of thePMOS transistor 6. At this time, since the delayed clock signal DCK supplied to the PMOS transistor is still at a lower level “L”, thePMOS transistor 6 maintains to be in a on state. The voltage Vn at the node NA is returned to the threshold voltage Vt of theinverter 4 after a small range of variation. Therefore, a voltage “Vi−Vt” charged at thecapacitor 3 is not changed in level. - After a delay time “dt”, when the delayed clock signal DCK is turned from “L” to “H”, the
PMOS transistor 6 is turned off and theinput switch circuit 2 allows the reference voltage Vr to be inputted. At the same time, thePMOS transistors capacitor 3, a voltage Vn at the node NA becomes “Vr−(Vi−Vt)”. When the voltage Vn at the node NA is higher than the threshold voltage Vt of theinverter 4, that is, when the reference voltage Vr is higher than the input voltage Vi, a low level output signal OUT is outputted from theoutput terminal 5. On the other hand, when the voltage Vn at the node NA is lower than the threshold voltage Vt of theinverter 4, that is, when the reference voltage Vr is lower than the input voltage Vi, a high level output signal OUT is outputted from theoutput terminal 5. - Subsequently, when the clock signal Ck is turned from “H” to “L”, the
PMOS transistors PMOS transistor 6 is turned on. When thePMOS transistor 6 is turned on, an input voltage signal Vi is allowed to be inputted. The voltage Vn at the node NA is converged to the threshold voltage Vt of theinverter 4. The above operation is repeated in response to the clock signal CK. - According to the chopper type comparator, shown in FIG. 2, a delayed clock signal is supplied to the
input switch circuit 2 and thePMOS transistor 6, while a regular clock signal CK is supplied to thePMOS transistor PMOS transistor 6 when the PMOStransistor PMOS transistor 8 is turned on, can be prevented. Therefore, an offset difference can be reduced. - FIG. 4 shows another chopper type comparator according to the present invention. In FIG. 4, the same and corresponding elements to those in FIGS. 1 and 2 are represented by the same reference symbols and the same description is not repeated.
- The comparator includes an
input terminal 1, aninput switch circuit 2, acapacitor 3, aninverter 4, anoutput terminal 5 and adelay circuit 10. The comparator further includes a first switch circuit (6 a, 7 a, 8 a and 9 a) and a second switch circuit (6 b, 7 b, 8 b and 9 b), each of which operates to turn on and off theinverter 4. - The
input switch circuit 2 inputs an input voltage Vi and a reference voltage Vr alternately in response to a delayed clock signal DCK. Theoutput terminal 5 supplies an output voltage, having a level defined based on the difference between the input voltage Vi and the reference voltage Vr. Thecapacitor 3 is coupled between the input switch circuit and the output terminal. A node NA is coupled between thecapacitor 3 and theoutput terminal 5. Theinverter 4 is coupled between the node NA and theoutput terminal 5. - The first switch circuit include a
first PMOS transistor 6 a and a first bias control circuit, which includesPMOS transistors inverter 9 a. Thefirst PMOS transistor 6 a is coupled between the node NA and theoutput terminal 5 in parallel to theinverter 4. The first bias control circuit (7 a, 8 a and 9 a) selectively connects the substrate voltage terminal of thefirst PMOS transistor 6 a to the supply terminal VDD and theoutput terminal 5 in response to the delay clock signal DCK. - The second switch circuit include a
second PMOS transistor 6 b and a second bias control circuit, which includesPMOS transistors inverter 9 b. Thesecond PMOS transistor 6 b is coupled between the node NA and theoutput terminal 5 in parallel to theinverter 4. Each of gate widths of thePMOS transistors PMOS transistor 6, shown in FIG. 2. The second bias control circuit (7 b, 8 b and 9 b) selectively connects the substrate voltage terminal of thesecond PMOS transistor 6 b to the supply terminal VDD and theoutput terminal 5 in response to the delay clock signal DCK. - In operation, first, the
PMOS transistors PMOS transistors inverter 4. - Next, the
PMOS transistors PMOS transistor 8 b is turned on. A voltage at the node NA is changed in a small range due to a parasitic capacitance Cpb, generated between a source and a substrate of thePMOS transistor 6 b and charge partitioning, generated between the node and thecapacitance 3. After such a small change, a voltage at the node NA reestablishes to the threshold voltage Vt, since thePMOS transistor 6 a is in an on state. - Subsequently, the
PMOS transistors PMOS transistor 8 a is turned on. A voltage at the node NA is changed in a small range due to a parasitic capacitance Cpb, generated between a source and a substrate of thePMOS transistor 6 a and charge partitioning, generated between the node and thecapacitance 3. Such a voltage change at the node NA is small, because thePMOS transistor 6 a has a gate width that is a half of thePMOS transistor 6, shown in FIG. 2, and a parasitic capacitance should also be a half of the comparator shown in FIG. 2. - As described above, according to the chopper type comparator shown in FIG. 4, a couple of
PMOS transistors single PMOS transistor 6, shown in FIGS. 1 and 2, and each of thePMOS transistors PMOS transistor 6. In addition, thePMOS transistors - The present invention is not limited by the embodiments, shown in FIGS. 1, 2 and4. For example, the
input switch circuit 2 can be designed to connect theinput terminal 1 and thecapacitor 3 when thePMOS transistor 6 is in an off state. It can replace with the PMOS transistors 6-8, 6 a-8 a and 6 b-8 b and NMOS transistors are employed. ThePMOS transistors PMOS transistor 6 a is determined to be smaller than that of thePMOS transistor 6 b in order that a voltage variation at the node NA can be more decreased.
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001354941A JP3476446B2 (en) | 2001-11-20 | 2001-11-20 | Chopper type comparator |
JP2001-354941 | 2001-11-20 |
Publications (2)
Publication Number | Publication Date |
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US6566916B1 US6566916B1 (en) | 2003-05-20 |
US20030094981A1 true US20030094981A1 (en) | 2003-05-22 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/197,432 Expired - Lifetime US6566916B1 (en) | 2001-11-20 | 2002-07-18 | Chopper type comparator |
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US (1) | US6566916B1 (en) |
JP (1) | JP3476446B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4255733B2 (en) * | 2003-04-09 | 2009-04-15 | ソニー株式会社 | Comparator, differential amplifier, two-stage amplifier and analog / digital converter |
JP3983220B2 (en) | 2003-12-24 | 2007-09-26 | 沖電気工業株式会社 | Analog switch |
US7454287B2 (en) * | 2005-07-18 | 2008-11-18 | Image Sensing Systems, Inc. | Method and apparatus for providing automatic lane calibration in a traffic sensor |
TWI462441B (en) * | 2013-03-14 | 2014-11-21 | Richtek Technology Corp | Power converting circuit and control circuit thereof |
WO2021245831A1 (en) * | 2020-06-03 | 2021-12-09 | 日本電信電話株式会社 | A/d converter |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4745393A (en) * | 1985-09-25 | 1988-05-17 | Hitachi, Ltd | Analog-to-digital converter |
JP3456099B2 (en) * | 1996-08-16 | 2003-10-14 | ソニー株式会社 | Chopper comparator and A / D converter |
JP2001016079A (en) * | 1999-06-30 | 2001-01-19 | Toshiba Lsi System Support Kk | Chopper-type voltage comparing circuit |
-
2001
- 2001-11-20 JP JP2001354941A patent/JP3476446B2/en not_active Expired - Fee Related
-
2002
- 2002-07-18 US US10/197,432 patent/US6566916B1/en not_active Expired - Lifetime
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JP2003158446A (en) | 2003-05-30 |
JP3476446B2 (en) | 2003-12-10 |
US6566916B1 (en) | 2003-05-20 |
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