US20030036224A1 - Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials - Google Patents

Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials Download PDF

Info

Publication number
US20030036224A1
US20030036224A1 US09/929,021 US92902101A US2003036224A1 US 20030036224 A1 US20030036224 A1 US 20030036224A1 US 92902101 A US92902101 A US 92902101A US 2003036224 A1 US2003036224 A1 US 2003036224A1
Authority
US
United States
Prior art keywords
layer
semiconductor
substrate
monocrystalline
material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/929,021
Other versions
US6673667B2 (en
Inventor
Jonathan Gorrell
Kenneth Cornett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Solutions Inc filed Critical Motorola Solutions Inc
Priority to US09/929,021 priority Critical patent/US6673667B2/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CORNETT, KENNETH D., GORRELL, JONATHAN F.
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. INVALID RECORDING, SEE DOCUMENT AT REEL 012659, FRAME 0757. (RECORDED TO CORRECT RECORDATION DATE) Assignors: CORNETT, KENNETH D., GORRELL, JONATHAN F.
Publication of US20030036224A1 publication Critical patent/US20030036224A1/en
Application granted granted Critical
Publication of US6673667B2 publication Critical patent/US6673667B2/en
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MOTOROLA, INC.
Assigned to CITIBANK, N.A. AS COLLATERAL AGENT reassignment CITIBANK, N.A. AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE ACQUISITION CORPORATION, FREESCALE ACQUISITION HOLDINGS CORP., FREESCALE HOLDINGS (BERMUDA) III, LTD., FREESCALE SEMICONDUCTOR, INC.
Assigned to CITIBANK, N.A., AS COLLATERAL AGENT reassignment CITIBANK, N.A., AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE SEMICONDUCTOR, INC.
Assigned to CITIBANK, N.A., AS NOTES COLLATERAL AGENT reassignment CITIBANK, N.A., AS NOTES COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE SEMICONDUCTOR, INC.
Assigned to CITIBANK, N.A., AS NOTES COLLATERAL AGENT reassignment CITIBANK, N.A., AS NOTES COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE SEMICONDUCTOR, INC.
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Assignors: CITIBANK, N.A.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Assignors: CITIBANK, N.A.
Assigned to NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC. reassignment NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Assignors: CITIBANK, N.A.
Assigned to SHENZHEN XINGUODU TECHNOLOGY CO., LTD. reassignment SHENZHEN XINGUODU TECHNOLOGY CO., LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02513Microstructure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials

Abstract

A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Description

    FIELD OF THE INVENTION
  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline material layer comprised of semiconductor material, compound semiconductor material, and/or other types of material such as metals and non-metals. [0001]
  • In particular, the present invention provides a method for manufacturing a semiconductor that aids in carrying out photolithography operations during manufacturing semiconductor devices involving multiple semiconductor materials within a single integral monolithic apparatus. The present invention provides improved alacrity and efficiency in manufacturing such multi-material integral monolithic semiconductor devices. [0002]
  • BACKGROUND OF THE INVENTION
  • Semiconductor devices often include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and band gap of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases. [0003]
  • For many years, attempts have been made to grow various monolithic thin films on a foreign substrate such as silicon (Si). To achieve optimal characteristics of the various monolithic layers, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow various monocrystalline layers on a substrate such as germanium, silicon, and various insulators. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting layer of monocrystalline material to be of low crystalline quality. [0004]
  • If a large area thin film of high quality monocrystalline material was available at low cost, a variety of semiconductor devices could advantageously be fabricated in or using that film at a low cost compared to the cost of fabricating such devices beginning with a bulk wafer of semiconductor material or in an epitaxial film of such material on a bulk wafer of semiconductor material. In addition, if a thin film of high quality monocrystalline material could be realized beginning with a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the high quality monocrystalline material. [0005]
  • Accordingly, a need exists for a semiconductor structure that provides a high quality monocrystalline film or layer over another monocrystalline material and for a process for making such a structure. In other words, there is a need for providing the formation of a monocrystalline substrate that is compliant with a high quality monocrystalline material layer so that true two-dimensional growth can be achieved for the formation of quality semiconductor structures, devices and integrated circuits having grown monocrystalline film having the same crystal orientation as an underlying substrate. This monocrystalline material layer may be comprised of a semiconductor material, a compound semiconductor material, and other types of material such as metals and non-metals. [0006]
  • A significant problem encountered during semiconductor manufacturing of integral monolithic devices involves limitations in employing lithographic manufacturing equipment in such operations. Lithographic manufacturing equipment is a common manufacturing tool for producing densely populated integrated circuitry that is desirable in today's market in which smaller, more compact products are constantly sought. Photolithographic equipment is optically-based equipment that has a depth of focus (depth of field) within which it must operate. Operation of photolithographic equipment outside its prescribed depth of focus is not practical, feasible or desirable. [0007]
  • As a consequence of the focal limitations of lithographic equipment, it is desirable that there be a coplanar relation among various lands, or areas, in which lithographic processes are to be practiced. Thus, using the processing technology taught by the present application one may, for example, require that top surfaces of gallium arsenide (GaAs) lands and top surfaces of silicon (Si) lands in an integral monolithic structure must be substantially coplanar. Such coplanarity assures that lithographic processes only need to deal with a single depth of focus for manufacturing the part involved. For example, it would be useful to be able to use coplanar alignment keys in manufacturing MOSFET devices (in silicon) and MESFET devices (in gallium arsenide) in a single semiconductor device using common alignment keys. Such common alignment keys would allow one to perform operations in either silicon or in gallium arsenide at any time during manufacturing operations without needing to reset lithographic equipment. [0008]
  • If the various lands are not coplanar to an extent that they are misaligned by a distance greater than the depth of focus of the lithographic equipment employed, then a product designer must decide where to establish alignment markings, or keys for registration of lithographic equipment for each set of coplanar lands implemented in a respective material. In such situations, there may likely be a need for more than one set of alignment keys. Such an arrangement is not desirable because the lithographic equipment must be reset to a different orientation for processing each material. That is, the lithographic equipment would have to be adjusted or reset to ensure that a particular land implemented in a respective material is within the depth of focus for the lithographic equipment. Such occasions for resetting equipment are disruptive to a manufacturing operation, provide unwanted opportunities for introduction of errors into the manufacturing process and generally contribute to inefficiency. Inefficiency is readily manifested as increased cost in manufacturing because of greater amounts of waste, lower yields and similar related factors. [0009]
  • The capability for multi-material semiconductor devices in an integral monolithic structure provided by the present invention has not been available to product designers or manufacturing process designers heretofore. Until now different semiconductor technologies were implemented separately on discrete chips or substrates and then mechanically combined in a single product. That is, no capability to produce multi-material integrated monolithic semiconductor devices has been available before. Now one can employ the present invention to efficiently and reliably produce multi-material integrated monolithic semiconductor devices. [0010]
  • The need for coplanarity among materials in different lands in an integral monolithic semiconductor apparatus is met using the method of the present invention. The present invention provides a method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.[0011]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which: [0012]
  • FIGS. 1, 2, and [0013] 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer; [0014]
  • FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer; [0015]
  • FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer; [0016]
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer; [0017]
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer; [0018]
  • FIGS. [0019] 9-12 illustrate schematically, in cross-section, the formation of a device structure in accordance with another embodiment of the invention;
  • FIGS. [0020] 13-16 illustrate a probable molecular bonding structure of the device structures illustrated in FIGS. 9-12;
  • FIGS. [0021] 17-20 illustrate schematically, in cross-section, the formation of a device structure in accordance with still another embodiment of the invention; and
  • FIGS. [0022] 21-23 illustrate schematically, in cross-section, the formation of yet another embodiment of a device structure in accordance with the invention.
  • FIGS. 24, 25 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention. [0023]
  • FIGS. [0024] 26-30 include illustrations of cross-sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein.
  • FIGS. [0025] 31-37 include illustrations of cross-sectional views of a portion of another integrated circuit that includes a semiconductor laser and a MOS transistor in accordance with what is shown herein.
  • FIG. 38-[0026] 41 are schematic elevation views illustrating structural manifestations associated with the steps involved in practicing the preferred embodiment of the present invention.
  • FIG. 42-[0027] 46 are schematic elevation views illustrating structural manifestations associated with the steps involved in practicing an alternate embodiment of the present invention.
  • FIG. 47 is a flow diagram illustrating embodiments of the present invention.[0028]
  • Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. [0029]
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure [0030] 20 in accordance with an embodiment of the invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a monocrystalline material layer 26. In this context, the term “monocrystalline” shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • In accordance with one embodiment of the invention, structure [0031] 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline material layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the monocrystalline material layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate [0032] 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor or compound semiconductor wafer, preferably of large diameter. The wafer can be of, for example, a material from Group IV of the periodic table. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline material layer 26 which may comprise a semiconductor material, a compound semiconductor material, or another type of material such as a metal or a non-metal.
  • Accommodating buffer layer [0033] 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying material layer. For example, the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied monocrystalline material layer. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitrides may include three or more different metallic elements.
  • Amorphous interface layer [0034] 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • The material for monocrystalline material layer [0035] 26 can be selected, as desired, for a particular structure or application. For example, the monocrystalline material of layer 26 may comprise a compound semiconductor which can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GaInAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like. However, monocrystalline material layer 26 may also comprise other semiconductor materials, metals, or non-metal materials which are used in the formation of semiconductor structures, devices and/or integrated circuits.
  • Appropriate materials for template [0036] 30 are discussed below. Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of monocrystalline material layer 26. When used, template layer 30 has a thickness ranging from about 1 to about 10 monolayers.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure [0037] 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and monocrystalline material layer 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of monocrystalline material. The additional buffer layer, formed of a semiconductor or compound semiconductor material when the monocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline semiconductor or compound semiconductor material layer.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure [0038] 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional monocrystalline layer 38.
  • As explained in greater detail below, amorphous layer [0039] 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and additional monocrystalline layer 26 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing—e.g., monocrystalline material layer 26 formation.
  • The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline material layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline material layers because it allows any strain in layer [0040] 26 to relax.
  • Additional monocrystalline layer [0041] 38 may include any of the materials described throughout this application in connection with either of monocrystalline material layer 26 or additional buffer layer 32. For example, when monocrystalline material layer 26 comprises a semiconductor or compound semiconductor material, layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
  • In accordance with one embodiment of the present invention, additional monocrystalline layer [0042] 38 serves as an anneal cap during layer 36 formation and as a template for subsequent monocrystalline layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline material.
  • In accordance with another embodiment of the invention, additional monocrystalline layer [0043] 38 comprises monocrystalline material (e.g., a material discussed above in connection with monocrystalline layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include monocrystalline material layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one monocrystalline layer disposed above amorphous oxide layer 36.
  • The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures [0044] 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • EXAMPLE 1
  • In accordance with one embodiment of the invention, monocrystalline substrate [0045] 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of SrzBa1-zTiO3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiOx) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the monocrystalline material layer 26 from the substrate to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.
  • In accordance with this embodiment of the invention, monocrystalline material layer [0046] 26 is a compound semiconductor layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer is formed by capping the oxide layer. The template layer is preferably 1-10 monolayers of Ti—As, Sr—O—As, Sr—Ga—O, or Sr—Al—O. By way of a preferred example, 1-2 monolayers of Ti—As or Sr—Ga—O have been illustrated to successfully grow GaAs layers.
  • EXAMPLE 2
  • In accordance with a further embodiment of the invention, monocrystalline substrate [0047] 22 is a silicon substrate as described above. The accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer. The accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO3, BaZrO3, SrHfO3, BaSnO3 or BaHfO3. For example, a monocrystalline oxide layer of BaZrO3 can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.
  • An accommodating buffer layer formed of these zirconate or hafnate materials is suitable for the growth of a monocrystalline material layer which comprises compound semiconductor materials in the indium phosphide (InP) system. In this system, the compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGaInAsP), having a thickness of about 1.0 nm to 10 μm. A suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr—As), zirconium-phosphorus (Zr—P), hafnium-arsenic (Hf—As), hafnium-phosphorus (Hf—P), strontium-oxygen-arsenic (Sr—O—As), strontium-oxygen-phosphorus (Sr—O—P), barium-oxygen-arsenic (Ba—O—As), indium-strontium-oxygen (In—Sr—O), or barium-oxygen-phosphorus (Ba—O—P), and preferably 1-2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr—As template. A monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer. The resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%. [0048]
  • EXAMPLE 3
  • In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a monocrystalline material comprising a II-VI material overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr[0049] xBa1-xTiO3, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. Where the monocrystalline layer comprises a compound semiconductor material, the II-VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe). A suitable template for this material system includes 1-10 monolayers of zinc-oxygen (Zn—O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr—S) followed by the ZnSeS.
  • EXAMPLE 4
  • This embodiment of the invention is an example of structure [0050] 40 illustrated in FIG. 2. Substrate 22, accommodating buffer layer 24, and monocrystalline material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AlInP), a gallium arsenide phosphide (GaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAsxP1-x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an InyGa1-yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying monocrystalline material which in this example is a compound semiconductor material. The compositions of other compound semiconductor materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge—Sr) or germanium-titanium (Ge—Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline material layer which in this example is a compound semiconductor material. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • EXAMPLE 5
  • This example also illustrates materials useful in a structure [0051] 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, additional buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline material layer. The buffer layer, a further monocrystalline material which in this instance comprises a semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs). In accordance with one aspect of this embodiment, additional buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 50%. The additional buffer layer 32 preferably has a thickness of about 10-30 nm. Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline material which in this example is a compound semiconductor material. Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline material layer 26.
  • EXAMPLE 6
  • This example provides exemplary materials useful in structure [0052] 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalline material layer 26 may be the same as those described above in connection with example 1.
  • Amorphous layer [0053] 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above). For example, amorphous layer 36 may include a combination of SiOX and SrzBa1-zTiO3 (where z ranges from 0 to 1), which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • The thickness of amorphous layer [0054] 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of monocrystalline material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
  • Layer [0055] 38 comprises a monocrystalline material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.
  • Referring again to FIGS. [0056] 1-3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms “substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve [0057] 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that have a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • In accordance with one embodiment of the invention, substrate [0058] 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.
  • Still referring to FIGS. [0059] 1-3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. For example, if the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline SrxBa1-xTiO3, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide. Similarly, if the host material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal. In some instances, a crystalline semiconductor buffer layer between the host oxide and the grown monocrystalline material layer can be used to reduce strain in the grown monocrystalline material layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline material layer can thereby be achieved.
  • The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. [0060] 1-3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 4° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term “bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term “bare” is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C. to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2×1 structure, includes strontium, oxygen, and silicon. The ordered 2×1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkaline earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750° C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2×1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer. [0061]
  • Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800° C. and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered (100) monocrystal with the (100) crystalline orientation rotated by 45° with respect to the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer. [0062]
  • After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired monocrystalline material. For example, for the subsequent growth of a monocrystalline compound semiconductor material layer of gallium arsenide, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti—As bond, a Ti—O—As bond or a Sr—O—As. Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr—O—Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs. [0063]
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with one embodiment of the present invention. Single crystal SrTiO[0064] 3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on a structure including GaAs monocrystalline layer [0065] 26 comprising GaAs grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The additional buffer layer [0066] 32 is formed overlying the template layer before the deposition of the monocrystalline material layer. If the buffer layer is a monocrystalline material comprising a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a monocrystalline material layer comprising a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.
  • Structure [0067] 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.
  • In accordance with one aspect of this embodiment, layer [0068] 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and monocrystalline layer 38 to a rapid thermal anneal process with a peak temperature of about 700° C. to about 1000° C. and a process time of about 5 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing, electron beam annealing, or “conventional” thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • As noted above, layer [0069] 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution TEM of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal SrTiO[0070] 3 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, additional monocrystalline layer 38 comprising a compound semiconductor layer of GaAs is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including additional monocrystalline layer [0071] 38 comprising a GaAs compound semiconductor layer and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
  • The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline material layer comprising a gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other monocrystalline material layers comprising other III-V and II-VI monocrystalline compound semiconductors, semiconductors, metals and non-metals can be deposited overlying the monocrystalline oxide accommodating buffer layer. [0072]
  • Each of the variations of monocrystalline material layer and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the monocrystalline material layer. For example, if the accommodating buffer layer is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively. In a similar manner, strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a monocrystalline material layer comprising compound semiconductors such as indium gallium arsenide, indium aluminum arsenide, or indium phosphide. [0073]
  • The formation of a device structure in accordance with another embodiment of the invention is illustrated schematically in cross-section in FIGS. [0074] 9A-9D. Like the previously described embodiments referred to in FIGS. 1-3, this embodiment of the invention involves the process of forming a compliant substrate utilizing the epitaxial growth of single crystal oxides, such as the formation of accommodating buffer layer 24 previously described with reference to FIGS. 1 and 2 and amorphous layer 36 previously described with reference to FIG. 3, and the formation of a template layer 30. However, the embodiment illustrated in FIGS. 9A-9D utilizes a template that includes a surfactant to facilitate layer-by-layer monocrystalline material growth.
  • Turning now to FIG. 9A, an amorphous intermediate layer [0075] 58 is grown on substrate 52 at the interface between substrate 52 and a growing accommodating buffer layer 54, which is preferably a monocrystalline crystal oxide layer, by the oxidation of substrate 52 during the growth of layer 54. Layer 54 is preferably a monocrystalline oxide material such as a monocrystalline layer of SrzBa1-zTiO3 where z ranges from 0 to 1. However, layer 54 may also comprise any of those compounds previously described with reference layer 24 in FIGS. 1-2 and any of those compounds previously described with reference to layer 36 in FIG. 3 which is formed from layers 24 and 28 referenced in FIGS. 1 and 2.
  • Layer [0076] 54 is grown with a strontium (Sr) terminated surface represented in FIG. 9A by hatched line 55 which is followed by the addition of a template layer 60 which includes a surfactant layer 61 and capping layer 63 as illustrated in FIGS. 9B and 9C. Surfactant layer 61 may comprise, but is not limited to, elements such as Al, In and Ga, but will be dependent upon the composition of layer 54 and the overlying layer of monocrystalline material for optimal results. In one exemplary embodiment, aluminum (Al) is used for surfactant layer 61 and functions to modify the surface and surface energy of layer 54. Preferably, surfactant layer 61 is epitaxially grown, to a thickness of one to two monolayers, over layer 54 as illustrated in FIG. 9B by way of molecular beam epitaxy (MBE), although other epitaxial processes may also be performed including chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • Surfactant layer [0077] 61 is then exposed to a Group V element such as arsenic, for example, to form capping layer 63 as illustrated in FIG. 9C. Surfactant layer 61 may be exposed to a number of materials to create capping layer 63 such as elements which include, but are not limited to, As, P, Sb and N. Surfactant layer 61 and capping layer 63 combine to form template layer 60.
  • Monocrystalline material layer [0078] 66, which in this example is a compound semiconductor such as GaAs, is then deposited via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like to form the final structure illustrated in FIG. 9D.
  • FIGS. [0079] 10A-10D illustrate possible molecular bond structures for a specific example of a compound semiconductor structure formed in accordance with the embodiment of the invention illustrated in FIGS. 9A-9D. More specifically, FIGS. 10A-10D illustrate the growth of GaAs (layer 66) on the strontium terminated surface of a strontium titanate monocrystalline oxide (layer 54) using a surfactant containing template (layer 60).
  • The growth of a monocrystalline material layer [0080] 66 such as GaAs on an accommodating buffer layer 54 such as a strontium titanium oxide over amorphous interface layer 58 and substrate layer 52, both of which may comprise materials previously described with reference to layers 28 and 22, respectively in FIGS. 1 and 2, illustrates a critical thickness of about 1000 Angstroms where the two-dimensional (2D) and three-dimensional (3D) growth shifts because of the surface energies involved. In order to maintain a true layer by layer growth (Frank Van der Mere growth), the following relationship must be satisfied:
  • δSTO>(δINTGaAs)
  • where the surface energy of the monocrystalline oxide layer [0081] 54 must be greater than the surface energy of the amorphous interface layer 58 added to the surface energy of the GaAs layer 66. Since it is impracticable to satisfy this equation, a surfactant containing template was used, as described above with reference to FIGS. 9B-9D, to increase the surface energy of the monocrystalline oxide layer 54 and also to shift the crystalline structure of the template to a diamond-like structure that is in compliance with the original GaAs layer.
  • FIG. 10A illustrates the molecular bond structure of a strontium terminated surface of a strontium titanate monocrystalline oxide layer. An aluminum surfactant layer is deposited on top of the strontium terminated surface and bonds with that surface as illustrated in FIG. 10B, which reacts to form a capping layer comprising a monolayer of Al[0082] 2Sr having the molecular bond structure illustrated in FIG. 10B which forms a diamond-like structure with an sp3 hybrid terminated surface that is compliant with compound semiconductors such as GaAs. The structure is then exposed to As to form a layer of AlAs as shown in FIG. 10C. GaAs is then deposited to complete the molecular bond structure illustrated in FIG. 10D which has been obtained by 2D growth. The GaAs can be grown to any thickness for forming other semiconductor structures, devices, or integrated circuits. Alkaline earth metals such as those in Group IIA are those elements preferably used to form the capping surface of the monocrystalline oxide layer 54 because they are capable of forming a desired molecular structure with aluminum.
  • In this embodiment, a surfactant containing template layer aids in the formation of a compliant substrate for the monolithic integration of various material layers including those comprised of Group III-V compounds to form high quality semiconductor structures, devices and integrated circuits. For example, a surfactant containing template may be used for the monolithic integration of a monocrystalline material layer such as a layer comprising Germanium (Ge), for example, to form high efficiency photocells. [0083]
  • Turning now to FIGS. [0084] 11-14, the formation of a device structure in accordance with still another embodiment of the invention is illustrated in cross-section. This embodiment utilizes the formation of a compliant substrate which relies on the epitaxial growth of single crystal oxides on silicon followed by the epitaxial growth of single crystal silicon onto the oxide.
  • An accommodating buffer layer [0085] 74 such as a monocrystalline oxide layer is first grown on a substrate layer 72, such as silicon, with an amorphous interface layer 78 as illustrated in FIG. 11. Monocrystalline oxide layer 74 may be comprised of any of those materials previously discussed with reference to layer 24 in FIGS. 1 and 2, while amorphous interface layer 78 is preferably comprised of any of those materials previously described with reference to the layer 28 illustrated in FIGS. 1 and 2. Substrate 72, although preferably silicon, may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
  • Next, a silicon layer [0086] 81 is deposited over monocrystalline oxide layer 74 via MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, and the like as illustrated in FIG. 12 with a thickness of a few hundred Angstroms but preferably with a thickness of about 50 Angstroms. Monocrystalline oxide layer 74 preferably has a thickness of about 20 to 100 Angstroms.
  • Rapid thermal annealing is then conducted in the presence of a carbon source such as acetylene or methane, for example at a temperature within a range of about 800° C. to 1000° C. to form capping layer [0087] 82 and silicate amorphous layer 86. However, other suitable carbon sources may be used as long as the rapid thermal annealing step functions to amorphize the monocrystalline oxide layer 74 into a silicate amorphous layer 86 and carbonize the top silicon layer 81 to form capping layer 82 which in this example would be a silicon carbide (SiC) layer as illustrated in FIG. 13. The formation of amorphous layer 86 is similar to the formation of layer 36 illustrated in FIG. 3 and may comprise any of those materials described with reference to layer 36 in FIG. 3 but the preferable material will be dependent upon the capping layer 82 used for silicon layer 81.
  • Finally, a compound semiconductor layer [0088] 96, such as gallium nitride (GaN) is grown over the SiC surface by way of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to form a high quality compound semiconductor material for device formation. More specifically, the deposition of GaN and GaN based systems such as GaInN and AlGaN will result in the formation of dislocation nets confined at the silicon/amorphous region. The resulting nitride containing compound semiconductor material may comprise elements from groups III, IV and V of the periodic table and is defect free.
  • Although GaN has been grown on SiC substrate in the past, this embodiment of the invention possesses a one step formation of the compliant substrate containing a SiC top surface and an amorphous layer on a Si surface. More specifically, this embodiment of the invention uses an intermediate single crystal oxide layer that is amorphosized to form a silicate layer which adsorbs the strain between the layers. Moreover, unlike past use of a SiC substrate, this embodiment of the invention is not limited by wafer size which is usually less than 50 mm in diameter for prior art SiC substrates. [0089]
  • The monolithic integration of nitride containing semiconductor compounds containing group III-V nitrides and silicon devices can be used for high temperature RF applications and optoelectronics. GaN systems have particular use in the photonic industry for the blue/green and UV light sources and detection. High brightness light emitting diodes (LEDs) and lasers may also be formed within the GaN system. [0090]
  • FIGS. [0091] 15-17 schematically illustrate, in cross-section, the formation of another embodiment of a device structure in accordance with the invention. This embodiment includes a compliant layer that functions as a transition layer that uses clathrate or Zintl type bonding. More specifically, this embodiment utilizes an intermetallic template layer to reduce the surface energy of the interface between material layers thereby allowing for two dimensional layer by layer growth.
  • The structure illustrated in FIG. 15 includes a monocrystalline substrate [0092] 102, an amorphous interface layer 108 and an accommodating buffer layer 104. Amorphous interface layer 108 is formed on substrate 102 at the interface between substrate 102 and accommodating buffer layer 104 as previously described with reference to FIGS. 1 and 2. Amorphous interface layer 108 may comprise any of those materials previously described with reference to amorphous interface layer 28 in FIGS. 1 and 2 but preferably comprises a monocrystalline oxide material such as a monocrystalline layer of SrzBa1-zTiO3 where z ranges from 0 to 1. Substrate 102 is preferably silicon but may also comprise any of those materials previously described with reference to substrate 22 in FIGS. 1-3.
  • A template layer [0093] 130 is deposited over accommodating buffer layer 104 as illustrated in FIG. 16 and preferably comprises a thin layer of Zintl type phase material composed of metals and metalloids having a great deal of ionic character. As in previously described embodiments, template layer 130 is deposited byway of MBE, CVD, MOCVD, MEE, ALE, PVD, CSD, PLD, or the like to achieve a thickness of one monolayer. Template layer 130 functions as a “soft” layer with non-directional bonding but high crystallinity which absorbs stress build up between layers having lattice mismatch. Materials for template 130 may include, but are not limited to, materials containing Si, Ga, In, and Sb such as, for example, AlSr2, (MgCaYb)Ga2, (Ca,Sr,Eu,Yb)In2, BaGe2As, and SrSn2As2
  • A monocrystalline material layer [0094] 126 is epitaxially grown over template layer 130 to achieve the final structure illustrated in FIG. 17. As a specific example, an SrAl2 layer may be used as template layer 130 and an appropriate monocrystalline material layer 126 such as a compound semiconductor material GaAs is grown over the SrAl2. The Al—Ti (from the accommodating buffer layer of layer of SrzBa1-zTiO3 where z ranges from 0 to 1) bond is mostly metallic while the Al—As (from the GaAs layer) bond is weakly covalent. The Sr participates in two distinct types of bonding with part of its electric charge going to the oxygen atoms in the lower accommodating buffer layer 104 comprising SrzBa1-zTiO3 to participate in ionic bonding and the other part of its valence charge being donated to Al in a way that is typically carried out with Zintl phase materials. The amount of the charge transfer depends on the relative electronegativity of elements comprising the template layer 130 as well as on the interatomic distance. In this example, Al assumes an sp3 hybridization and can readily form bonds with monocrystalline material layer 126, which in this example, comprises compound semiconductor material GaAs.
  • The compliant substrate produced by use of the Zintl type template layer used in this embodiment can absorb a large strain without a significant energy cost. In the above example, the bond strength of the Al is adjusted by changing the volume of the SrAl[0095] 2 layer thereby making the device tunable for specific applications which include the monolithic integration of III-V and Si devices and the monolithic integration of high-k dielectric materials for CMOS technology.
  • Clearly, those embodiments specifically describing structures having compound semiconductor portions and Group IV semiconductor portions, are meant to illustrate embodiments of the present invention and not limit the present invention. There are a multiplicity of other combinations and other embodiments of the present invention. For example, the present invention includes structures and methods for fabricating material layers which form semiconductor structures, devices and integrated circuits including other layers such as metal and non-metal layers. More specifically, the invention includes structures and methods for forming a compliant substrate which is used in the fabrication of semiconductor structures, devices and integrated circuits and the material layers suitable for fabricating those structures, devices, and integrated circuits. By using embodiments of the present invention, it is now simpler to integrate devices that include monocrystalline layers comprising semiconductor and compound semiconductor materials as well as other material layers that are used to form those devices with other components that work better or are easily and/or inexpensively formed within semiconductor or compound semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase. [0096]
  • In accordance with one embodiment of this invention, a monocrystalline semiconductor or compound semiconductor wafer can be used in forming monocrystalline material layers over the wafer. In this manner, the wafer is essentially a “handle” wafer used during the fabrication of semiconductor electrical components within a monocrystalline layer overlying the wafer. Therefore, electrical components can be formed within semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters. [0097]
  • By the use of this type of substrate, a relatively inexpensive “handle” wafer overcomes the fragile nature of compound semiconductor or other monocrystalline material wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within or using the monocrystalline material layer even though the substrate itself may include a monocrystalline semiconductor material. Fabrication costs for compound semiconductor devices and other devices employing non-silicon monocrystalline materials should decrease because larger substrates can be processed more economically and more readily compared to the relatively smaller and more fragile substrates (e.g. conventional compound semiconductor wafers). [0098]
  • FIG. 38-[0099] 41 are schematic elevation views illustrating structural manifestations associated with the steps involved in practicing the preferred embodiment of the present invention. In FIG. 38, a semiconductor substrate 3810 presents a first substantially planar land 3812. Substrate 3810 is preferably constructed of monocrystalline silicon (Si). Substrate 3810 is trenched to effect a cavity 3814 in substrate 3810. Cavity 3814 is dimensioned to receive a semiconductor structure that will be effected by later processing steps.
  • In FIG. 39, an accommodating layer [0100] 3816 is deposited or grown over substrate 3812, including within cavity 3814. Preferably accommodating layer 3816 is a monocrystalline perovskite oxide material. In the context of this application, the terms “deposit” and “grow” are intended to be interchangeable; no significant aspect of the present invention is substantially altered whether a deposition process or a growth process is employed in a respective method step.
  • An additional layer [0101] 3815 may be formed interfacing substrate 3810 and accommodating layer 3816. Such an additional layer 3815 preferably contains at least silicon and oxygen, and most preferably is a silicon oxide material that may be formed between substrate 3810 and accommodating layer 3816 by an oxidizing process.
  • A template layer [0102] 3819 maybe deposited over accommodating layer 3816, including within cavity 3814, but its presence is not essential to the practice of the method of the present invention. It is for this reason that template layer 3819 is indicated using broken lines in FIG. 39, and is not included in other views of FIGS. 38-41. A composition layer 3818 is deposited over accommodating layer 3816 (over template layer 3819, when present), including within cavity 3814. Composition layer 3818 is preferably constructed of a material that is different from the materials used in constructing substrate 3810. For example, composition layer 3818 may be constructed of gallium arsenide (GaAs).
  • In FIG. 40, portions of accommodating layer [0103] 3816 and composition layer 3818 (and template layer 3819, when present, not shown in FIG. 40) are selectively removed to establish a semiconductor structure 3820 within cavity 3814. Semiconductor structure 3820 includes remaining portions of accommodating layer 3816 and composition layer 3818 (and template layer 3819, when present, not shown in FIG. 40). Semiconductor structure 3820 presents a second substantially planar land 3813 that is substantially coplanar with first land 3812.
  • In FIG. 41, a cap layer [0104] 3822 is deposited over lands 3812, 3813 and within cavity 3814. Preferably, cap layer 3822 is constructed of an oxide, nitride or oxynitride material. Most preferably, cap layer 3822 is constructed of SiO2, Si3N4 or SiOxNy material. Cap layer 3822 is selectively removed to establish a substantially planar face 3824 generally parallel with substantially coplanar lands 3812, 3813. Face 3824 is displaced from second land 3813 by a predetermined distance “d”. In such a manner there is produced a semiconductor piece 3825. Predetermined distance “d” is selected to be equal to or less than the depth of focus associated with photolithographic material that will later be used for fashioning semiconductor piece 3825 into a product.
  • Providing that lands [0105] 3812, 3813 are substantially coplanar, and requiring that predetermined distance “d” is less than the depth of focus of lithographic equipment to be used for subsequent manufacturing operations assures that a product designer may establish alignment keys on each of land 3812, 3813 for lithographic processing of either silicon material (land 3812) or gallium arsenide material (land 3813).
  • FIG. 42-[0106] 46 are schematic elevation views illustrating structural manifestations associated with the steps involved in practicing an alternate embodiment of the present invention. In FIG. 42, a semiconductor substrate 4210 is preferably constructed of silicon (Si). An accommodating layer 4216 is deposited or grown over substrate 4212. A template layer 4219 may be deposited over accommodating layer 4216, but its presence is not essential to the practice of the method of the present invention. It is for this reason that template layer 4219 is indicated using broken lines in FIG. 42, and will not be included in other views of FIGS. 42-46. A composition layer 4218 is deposited over accommodating layer 4216 (over template layer 4219, when present). In the context of this application, the terms “deposit” and “grow” are intended to be interchangeable; no significant aspect of the present invention is substantially altered whether a deposition process or a growth process is employed in a respective method step. Composition layer 4218 is preferably constructed of a material that is different from the materials used in constructing substrate 4210. For example, composition layer 4218 may be constructed of gallium arsenide (GaAs).
  • In FIG. 43, portions of accommodating layer [0107] 4216 and composition layer 4218 (and template layer 4219, when present, not shown in FIG. 43) are selectively removed to establish a semiconductor structure 4220. Semiconductor structure 4220 includes remaining portions of accommodating layer 4216 and composition layer 4218 (and template layer 4219, when present, not shown in FIG. 43). Semiconductor structure 4220 presents a substantially planar land 4213.
  • In FIG. 44, a cap layer [0108] 4222 is deposited over semiconductor structure 4220 and substrate 4210. Preferably, cap layer 4222 is constructed of an oxide, nitride or oxynitride material. Most preferably, cap layer 4222 is constructed of SiO2, Si3N4 or SiOxNy material.
  • In FIG. 45, cap layer [0109] 4222 has been selectively removed to establish a capsule 4223. Capsule 4223 cooperates with substrate 4210 to substantially encapsulate semiconductor structure 4220. Capsule 4223 extends a distance d from land 4213. Distance d is selected to be a distance less than a predetermined distance; the predetermined distance is described in greater detail in connection with FIG. 46.
  • In FIG. 46, a supplemental cap layer [0110] 4224 is deposited over capsule 4223 and substrate 4210. Preferably, supplemental cap layer 4224 is constructed of the same material that comprises substrate 4210. Supplemental cap layer 4224 is selectively removed to establish a substantially planar face 4226 generally parallel with substantially planar land 4213. Face 4226 is displaced from land 4213 by a predetermined distance “D”. In such a manner there is produced a semiconductor piece 4227. Predetermined distance “D” is selected to be equal to or less than the depth of focus associated with photolithographic material that will later be used for fashioning semiconductor piece 4227 into a product.
  • In such a construction as is illustrated in FIG. 42-[0111] 46, face 4226 and land 4213 are substantially coplanar in so far as later-employed lithographic equipment is concerned. This is so because alignment marks established on face 4226 and land 4213 may be employed by the lithographic equipment for operating on face 4226 (fabricated in silicon, for example) and for operating on land 4213 (fabricated in gallium arsenide, for example) without resetting the lithographic equipment. That is, establishing face 4226 and land 4213 in such a substantially coplanar orientation by requiring that predetermined distance “D” be less than the depth of focus of lithographic equipment to be used for subsequent manufacturing operations assures that a product designer may establish alignment keys on face 4226 for lithographic processing of either silicon material (face 4226) or gallium arsenide material (land 4213).
  • FIG. 47 is a flow diagram illustrating embodiments of the present invention. In FIG. 47, two “tracks”—Track A and Track B—illustrate alternate embodiments of the method of the present invention. In FIG. 47, Track A, a method [0112] 4710 for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials presenting a plurality of substantially coplanar lands begins with the step of providing a substrate, as indicated by a block 4712. The substrate is constructed of a first semiconductor material of the plurality of semiconductor materials, and the substrate presents a first land of the plurality of lands. The first semiconductor material is preferably monocrystalline silicon.
  • Method [0113] 4710 continues by trenching the substrate from a first side of the substrate to effect a cavity in the substrate, as indicated by a block 4714. The cavity is appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land of the plurality of lands that is generally coplanar with the first land established according to block 4712.
  • Method [0114] 4710 continues by depositing an accommodating layer on the first side of the substrate and within the cavity to establish a workpiece, as indicated by a block 4716. The accommodating layer is constructed of a second semiconductor material of said plurality of semiconductor materials. The second semiconductor material is preferably a monocrystalline perovskite oxide material.
  • Method [0115] 4710 preferably continues by forming an amorphous oxide interface layer containing at least silicon and oxygen, and most preferably being a silicon oxide material, between the accommodating layer and the substrate, as indicated by a block 4717.
  • Method [0116] 4710 continues by depositing a composition layer on a first side of the workpiece adjacent the first side of the substrate, as indicated by a block 4718. The composition layer is constructed of a third semiconductor material of said plurality of semiconductor materials. The third semiconductor material preferably is gallium arsenide.
  • Method [0117] 4710 continues by selectively removing predetermined portions of the composition layer and the accommodating layer to establish the semiconductor structure, as indicated by a block 4720.
  • Method [0118] 4710 continues by depositing a cap layer at the first side of the workpiece, as indicated by a block 4722. The cap layer is constructed of a fourth semiconductor material of said plurality of semiconductor materials. The fourth semiconductor material is preferably an oxide, nitride or oxynitride material. Most preferably, the fourth semiconductor material is an SiO2, Si3N4 or SiOxNy material.
  • Method [0119] 4710 concludes by selectively removing the cap layer to establish a substantially planar face, as indicated by a block 4724. The planar face is displaced from the plurality of lands by a predetermined distance.
  • In FIG. 47, Track B, a method [0120] 4750 for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials presenting a plurality of substantially coplanar lands begins with the step of providing a substrate, as indicated by a block 4752. The substrate is constructed of a first semiconductor material of the plurality of semiconductor materials, and the substrate presents a first land of the plurality of lands. The first semiconductor material is preferably monocrystalline silicon.
  • Method [0121] 4750 continues by depositing an accommodating layer on the first side of the substrate to establish a workpiece, as indicated by a block 4754. The accommodating layer is constructed of a second semiconductor material of said plurality of semiconductor materials. The second semiconductor material is preferably a monocrystalline perovskite oxide.
  • Method [0122] 4750 preferably continues by forming an amorphous oxide interface layer containing at least silicon and oxygen, and most preferably being a silicon oxide material, between the accommodating layer and the substrate, as indicated by a block 4755.
  • Method [0123] 4750 continues by depositing a composition layer at a first side of the workpiece adjacent the first side of the substrate, as indicated by a block 4756. The composition layer is constructed of a third semiconductor material of said plurality of semiconductor materials. The third semiconductor material preferably is gallium arsenide.
  • Method [0124] 4750 continues by selectively removing predetermined portions of the composition layer and the accommodating layer to establish the semiconductor structure, as indicated by a block 4758.
  • Method [0125] 4750 continues by depositing a cap layer at the first side of the workpiece, as indicated by a block 4760. The cap layer is constructed of a fourth semiconductor material of said plurality of semiconductor materials. The fourth semiconductor material is preferably an oxide, nitride or oxynitride material. Most preferably, the fourth semiconductor material is an SiO2, Si3N4 or SiOxNy material.
  • Method [0126] 4750 continues by selectively removing the cap layer to establish a substantially planar face, as indicated by a block 4762. The planar face is displaced from the plurality of lands by less than a predetermined distance.
  • Method [0127] 4750 continues by depositing a second layer of the first semiconductor material over the face, as indicated by a block 4764.
  • Method [0128] 4750 concludes by selectively removing the second layer of the first semiconductor material to establish a second substantially planar face, as indicated by a block 4766. The second face is displaced from the plurality of lands by the predetermined distance.
  • Similarities between respective steps of method [0129] 4710 (FIG. 47, Track A) and method 4750 (FIG. 47, Track B) are indicated by arrows 4770, 4771, 4772, 4774, 4776, 4778. Thus, step 4716 is similar to step 4754, as indicated by arrow 4770. Step 4717 is similar to step 4755, as indicated by arrow 4771. Step 4718 is similar to step 4756, as indicated by arrow 4772. Step 4720 is similar to step 4758, as indicated by arrow 4774. Step 4722 is similar to step 4760, as indicated by arrow 4776. Step 4724 is similar to step 4762, as indicated by arrow 4778.
  • The similarities between step [0130] 4724 and step 4762 are less closely related than are the similarities between other steps recited above. Step 4724 requires removal of cap material to within a critical distance of the semiconductor structure, but step 4762 requires removal of cap material to less than a critical distance of the semiconductor structure. It is for this reason that arrow 4778 is indicated in a broken line.
  • In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. [0131]
  • Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. [0132]

Claims (10)

We claim:
1. A method for manufacturing a semiconductor apparatus; the semiconductor apparatus including a substantially integral monolithic semiconductor component including a plurality of materials presenting a plurality of substantially coplanar lands; the method comprising the steps of:
(a) providing a monocrystalline silicon substrate; said substrate presenting at least one first land of said plurality of lands; said monocrystalline silicon being a first material of said plurality of materials;
(b) trenching said substrate from a first side of said substrate to effect at least one cavity in said substrate; said at least one cavity being appropriately dimensioned to receive at least one semiconductor piece in a finished orientation; said finished orientation presenting at least one second land of said plurality of lands generally coplanar with said at least one first land;
(c) growing a monocrystalline perovskite oxide on said first side of said substrate to establish an accommodating layer at said first side of said substrate and within said at least one cavity; said monocrystalline perovskite oxide being a second material of said plurality of materials;
(d) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between said accommodating layer and said monocrystalline silicon substrate;
(e) growing a template for said at least one semiconductor piece on said oxide to establish a process piece; said at least one semiconductor piece being at least a portion of the semiconductor apparatus;
(f) growing said at least one semiconductor piece on said process piece; said at least one semiconductor piece being constructed of a monocrystalline compound semiconductor material; said monocrystalline compound semiconductor material being a third material of said plurality of materials;
(g) selectively removing predetermined portions of said at least one semiconductor piece and said accommodating layer to establish said at least one semiconductor piece in said finished orientation;
(h) depositing a cap layer on said substantially integral monolithic semiconductor component; and
(i) selectively removing said cap layer to establish a substantially planar face; said planar face being displaced from said plurality of lands by a predetermined distance.
2. A method for manufacturing a semiconductor apparatus as recited in claim 1, wherein the apparatus is configured for further working using optical manufacturing equipment; said optical manufacturing equipment having a depth of focus; and wherein said predetermined distance is less than or equal with said depth of focus.
3. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising repeating at least one of the steps (b) through (g) until said substantially integral monolithic semiconductor apparatus is completed.
4. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising annealing after said step of growing said at least one semiconductor piece.
5. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising annealing after said step of growing said at least one semiconductor piece is started.
6. A method for manufacturing a substantially integral monolithic semiconductor apparatus, the method comprising the steps of:
(a) providing a monocrystalline silicon substrate; said substrate presenting at least one first land of a plurality of lands;
(b) trenching said substrate from a first side of said substrate to effect at least one cavity in said substrate; said at least one cavity being appropriately dimensioned to receive at least one semiconductor piece in a finished orientation; said finished orientation presenting at least one second land of said plurality of lands generally coplanar with said at least one first land;
(c) growing a monocrystalline perovskite oxide on said first side of said substrate to establish an accommodating layer at said first side of said substrate and within said at least one cavity;
(d) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between said accommodating layer and said monocrystalline silicon substrate;
(e) growing a template for said at least one semiconductor piece on said oxide to establish a process piece; said at least one semiconductor piece being at least a portion of the semiconductor apparatus;
(f) growing said at least one semiconductor piece on said process piece; said at least one semiconductor piece being constructed of a monocrystalline compound semiconductor material;
(g) selectively removing predetermined portions of said at least one semiconductor piece and said accommodating layer to establish said at least one semiconductor piece in said finished orientation;
(h) depositing a cap layer on said substantially integral monolithic semiconductor component; and
(i) selectively removing said cap layer to establish a substantially planar face; said planar face being displaced from said plurality of lands by the predetermined distance.
7. A method for manufacturing a semiconductor apparatus as recited in claim 5, wherein the apparatus is configured for further working using optical manufacturing equipment; said optical manufacturing equipment having a depth of focus; and wherein said predetermined distance is less than or equal with said depth of focus.
8. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising repeating at least one of the steps (b) through (g) until said substantially integral monolithic semiconductor apparatus is completed.
9. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising annealing after said step of growing said at least one semiconductor piece.
10. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising annealing after said step of growing said at least one semiconductor piece has been started.
US09/929,021 2001-08-15 2001-08-15 Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials Expired - Fee Related US6673667B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/929,021 US6673667B2 (en) 2001-08-15 2001-08-15 Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/929,021 US6673667B2 (en) 2001-08-15 2001-08-15 Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials

Publications (2)

Publication Number Publication Date
US20030036224A1 true US20030036224A1 (en) 2003-02-20
US6673667B2 US6673667B2 (en) 2004-01-06

Family

ID=25457190

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/929,021 Expired - Fee Related US6673667B2 (en) 2001-08-15 2001-08-15 Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials

Country Status (1)

Country Link
US (1) US6673667B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040031990A1 (en) * 2002-08-16 2004-02-19 Been-Yih Jin Semiconductor on insulator apparatus and method

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849177B1 (en) * 2005-01-04 2008-07-30 삼성전자주식회사 Semiconductor integrated circuit devices employing a MOS transistor with facet channels and methods of fabricating the same
US7511678B2 (en) * 2006-02-24 2009-03-31 Northrop Grumman Corporation High-power dual-frequency coaxial feedhorn antenna
KR101064082B1 (en) * 2009-01-21 2011-09-08 엘지이노텍 주식회사 Light emitting element
GB2517697A (en) 2013-08-27 2015-03-04 Ibm Compound semiconductor structure
US9263586B2 (en) 2014-06-06 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure

Citations (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617951A (en) * 1968-11-21 1971-11-02 Western Microwave Lab Inc Broadband circulator or isolator of the strip line or microstrip type
US4177094A (en) * 1977-09-16 1979-12-04 U.S. Philips Corporation Method of treating a monocrystalline body utilizing a measuring member consisting of a monocrystalline layer and an adjoining substratum of different index of refraction
US4695120A (en) * 1985-09-26 1987-09-22 The United States Of America As Represented By The Secretary Of The Army Optic-coupled integrated circuits
US4801184A (en) * 1987-06-15 1989-01-31 Eastman Kodak Company Integrated optical read/write head and apparatus incorporating same
US4804866A (en) * 1986-03-24 1989-02-14 Matsushita Electric Works, Ltd. Solid state relay
US4866489A (en) * 1986-07-22 1989-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US5028563A (en) * 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US5057694A (en) * 1989-03-15 1991-10-15 Matsushita Electric Works, Ltd. Optoelectronic relay circuit having charging path formed by a switching transistor and a rectifying diode
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5140387A (en) * 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
US5148504A (en) * 1991-10-16 1992-09-15 At&T Bell Laboratories Optical integrated circuit designed to operate by use of photons
US5216359A (en) * 1991-01-18 1993-06-01 University Of North Carolina Electro-optical method and apparatus for testing integrated circuits
US5262659A (en) * 1992-08-12 1993-11-16 United Technologies Corporation Nyquist frequency bandwidth hact memory
US5268327A (en) * 1984-04-27 1993-12-07 Advanced Energy Fund Limited Partnership Epitaxial compositions
US5362972A (en) * 1990-04-20 1994-11-08 Hitachi, Ltd. Semiconductor device using whiskers
US5371621A (en) * 1993-08-23 1994-12-06 Unisys Corporation Self-routing multi-stage photonic interconnect
US5410622A (en) * 1992-08-21 1995-04-25 Sharp Kabushiki Kaisha Optical integrated circuit having light detector
US5446719A (en) * 1992-02-05 1995-08-29 Sharp Kabushiki Kaisha Optical information reproducing apparatus
US5477363A (en) * 1994-03-16 1995-12-19 Fujitsu Limited Optical switching device
US5508554A (en) * 1993-08-26 1996-04-16 Hitachi, Ltd. Semicoductor device having defect type compound layer between single crystal substrate and single crystal growth layer
US5510665A (en) * 1989-03-03 1996-04-23 E. F. Johnson Company Optoelectronic active circuit element
US5528209A (en) * 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
US5570226A (en) * 1991-04-26 1996-10-29 Fuji Xerox Co., Ltd. Optical link amplifier and a wavelength multiplex laser oscillator
US5574296A (en) * 1990-08-24 1996-11-12 Minnesota Mining And Manufacturing Company Doping of IIB-VIA semiconductors during molecular beam epitaxy electromagnetic radiation transducer having p-type ZnSe layer
US5574589A (en) * 1995-01-09 1996-11-12 Lucent Technologies Inc. Self-amplified networks
US5578162A (en) * 1993-06-25 1996-11-26 Lucent Technologies Inc. Integrated composite semiconductor devices and method for manufacture thereof
US5585167A (en) * 1992-05-18 1996-12-17 Matsushita Electric Industrial Co., Ltd. Thin-film conductor and method of fabricating the same
US5585288A (en) * 1990-07-16 1996-12-17 Raytheon Company Digital MMIC/analog MMIC structures and process
US5635453A (en) * 1994-12-23 1997-06-03 Neocera, Inc. Superconducting thin film system using a garnet substrate
US5666376A (en) * 1991-11-08 1997-09-09 University Of New Mexico Electro-optical device
US5674813A (en) * 1993-11-04 1997-10-07 Sumitomo Electric Industries, Ltd. Process for preparing layered structure including oxide super conductor thin film
US5679947A (en) * 1993-08-25 1997-10-21 Sony Corporation Optical device having a light emitter and a photosensor on the same optical axis
US5684302A (en) * 1993-07-15 1997-11-04 Siemens Aktiengesellschaft Pyrodetector element having a pyroelectric layer produced by oriented growth, and method for the fabrication of the element
US5693140A (en) * 1993-07-30 1997-12-02 Lockheed Martin Energy Systems, Inc. Process for growing a film epitaxially upon a MgO surface
US5719417A (en) * 1996-11-27 1998-02-17 Advanced Technology Materials, Inc. Ferroelectric integrated circuit structure
US5772758A (en) * 1994-12-29 1998-06-30 California Institute Of Technology Near real-time extraction of deposition and pre-deposition characteristics from rotating substrates and control of a deposition apparatus in near real-time
US5831960A (en) * 1997-07-17 1998-11-03 Motorola, Inc. Integrated vertical cavity surface emitting laser pair for high density data storage and method of fabrication
US5838053A (en) * 1996-09-19 1998-11-17 Raytheon Ti Systems, Inc. Method of forming a cadmium telluride/silicon structure
US5864171A (en) * 1995-03-30 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor optoelectric device and method of manufacturing the same
US5878175A (en) * 1994-04-15 1999-03-02 Fuji Photo Film Co., Ltd. Electro-optical waveguide element with reduced DC drift phenomena
US5882948A (en) * 1996-06-07 1999-03-16 Picolight, Inc. Method for fabricating a semiconductor device
US5905571A (en) * 1995-08-30 1999-05-18 Sandia Corporation Optical apparatus for forming correlation spectrometers and optical processors
US5937115A (en) * 1997-02-12 1999-08-10 Foster-Miller, Inc. Switchable optical components/structures and methods for the fabrication thereof
US5959308A (en) * 1988-07-25 1999-09-28 Texas Instruments Incorporated Epitaxial layer on a heterointerface
US5976953A (en) * 1993-09-30 1999-11-02 Kopin Corporation Three dimensional processor using transferred thin film circuits
US5987196A (en) * 1997-11-06 1999-11-16 Micron Technology, Inc. Semiconductor structure having an optical signal path in a substrate and method for forming the same
US5998819A (en) * 1996-03-19 1999-12-07 Sharp Kabushiki Kaisha Thin ferroelectric film element having a multi-layered thin ferroelectric film and method for manufacturing the same
US5998781A (en) * 1997-04-30 1999-12-07 Sandia Corporation Apparatus for millimeter-wave signal generation
US6049110A (en) * 1996-06-26 2000-04-11 Nec Corporation Body driven SOI-MOS field effect transistor
US6064783A (en) * 1994-05-25 2000-05-16 Congdon; Philip A. Integrated laser and coupled waveguide
US6080378A (en) * 1996-09-05 2000-06-27 Kabushiki Kaisha Kobe Seiko Sho Diamond films and methods for manufacturing diamond films
US6110813A (en) * 1997-04-04 2000-08-29 Matsushita Electric Industrial Co., Ltd. Method for forming an ohmic electrode
US6113225A (en) * 1997-01-24 2000-09-05 Seiko Epson Corporation Ink jet type recording head
US6198119B1 (en) * 1996-03-13 2001-03-06 Hitachi, Ltd. Ferroelectric element and method of producing the same
US6239012B1 (en) * 1998-01-27 2001-05-29 Micron Technology, Inc. Vertically mountable semiconductor device and methods
US20010020278A1 (en) * 2000-03-06 2001-09-06 Tatsuya Saito Phase-controlled source synchronous interface circuit
US6297598B1 (en) * 2001-02-20 2001-10-02 Harvatek Corp. Single-side mounted light emitting diode module
US6307996B1 (en) * 1997-11-06 2001-10-23 Fuji Xerox Co. Ltd. Optical waveguide device and manufacturing method thereof
US20010036142A1 (en) * 2000-03-03 2001-11-01 Kadowaki Shin-Ichi Optical pick-up head and information recording/reproducing apparatus
US6376337B1 (en) * 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
US6392253B1 (en) * 1998-08-10 2002-05-21 Arjun J. Saxena Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
US20020079576A1 (en) * 2000-06-30 2002-06-27 Krishna Seshan Ball limiting metallurgy for input/outputs and methods of fabrication
US6452232B1 (en) * 1998-12-03 2002-09-17 Sharp Kabushiki Kaisha Semiconductor device having SOI structure and manufacturing method thereof
US20020145168A1 (en) * 2001-02-05 2002-10-10 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US6477285B1 (en) * 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US6496469B1 (en) * 1999-09-27 2002-12-17 Kabushiki Kaisha Toshiba Integrated unit, optical pickup, and optical recording medium drive device
US20020195610A1 (en) * 2001-06-20 2002-12-26 Motorola, Inc. Structure and method for fabricating a semiconductor device with a side interconnect
US6504189B1 (en) * 1998-07-21 2003-01-07 Fujitsu Quantum Devices Limited Semiconductor device having a microstrip line

Family Cites Families (475)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670213A (en) 1969-05-24 1972-06-13 Tokyo Shibaura Electric Co Semiconductor photosensitive device with a rare earth oxide compound forming a rectifying junction
US4404265A (en) 1969-10-01 1983-09-13 Rockwell International Corporation Epitaxial composite and method of making
GB1319311A (en) 1970-06-04 1973-06-06 North American Rockwell Epitaxial composite and method of making
US4006989A (en) 1972-10-02 1977-02-08 Raytheon Company Laser gyroscope
US3766370A (en) 1971-05-14 1973-10-16 Hewlett Packard Co Elementary floating point cordic function processor and shifter
US3802967A (en) 1971-08-27 1974-04-09 Rca Corp Iii-v compound on insulating substrate and its preparation and use
US3914137A (en) 1971-10-06 1975-10-21 Motorola Inc Method of manufacturing a light coupled monolithic circuit by selective epitaxial deposition
US3935031A (en) 1973-05-07 1976-01-27 New England Institute, Inc. Photovoltaic cell with enhanced power output
US4084130A (en) 1974-01-18 1978-04-11 Texas Instruments Incorporated Laser for integrated optical circuits
JPS5816335B2 (en) * 1976-01-20 1983-03-30 Matsushita Electric Ind Co Ltd
US4120588A (en) 1976-07-12 1978-10-17 Erik Chaum Multiple path configuration for a laser interferometer
US4174422A (en) 1977-12-30 1979-11-13 International Business Machines Corporation Growing epitaxial films when the misfit between film and substrate is large
US4284329A (en) 1978-01-03 1981-08-18 Raytheon Company Laser gyroscope system
US4146297A (en) 1978-01-16 1979-03-27 Bell Telephone Laboratories, Incorporated Tunable optical waveguide directional coupler filter
US4242595A (en) 1978-07-27 1980-12-30 University Of Southern California Tunnel diode load for ultra-fast low power switching circuits
US4297656A (en) 1979-03-23 1981-10-27 Harris Corporation Plural frequency oscillator employing multiple fiber-optic delay line
US4424589A (en) 1980-04-11 1984-01-03 Coulter Systems Corporation Flat bed scanner system and method
US4452720A (en) 1980-06-04 1984-06-05 Teijin Limited Fluorescent composition having the ability to change wavelengths of light, shaped article of said composition as a light wavelength converting element and device for converting optical energy to electrical energy using said element
US4289920A (en) 1980-06-23 1981-09-15 International Business Machines Corporation Multiple bandgap solar cell on transparent substrate
JPS6352791B2 (en) 1981-04-14 1988-10-20 Intaanashonaru Sutandaado Erekutoritsuku Corp
EP0051488B1 (en) 1980-11-06 1985-01-30 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
US4442590A (en) 1980-11-17 1984-04-17 Ball Corporation Monolithic microwave integrated circuit with integral array antenna
US4392297A (en) 1980-11-20 1983-07-12 Spire Corporation Process of making thin film high efficiency solar cells
JPS57176785A (en) 1981-04-22 1982-10-30 Hitachi Ltd Semiconductor laser device
GB2115996B (en) 1981-11-02 1985-03-20 Kramer Kane N Portable data processing and storage system
US4439014A (en) 1981-11-13 1984-03-27 Mcdonnell Douglas Corporation Low voltage electro-optic modulator
US4482422A (en) 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
JPS58158944A (en) 1982-03-16 1983-09-21 Futaba Corp Semiconductor device
US4484332A (en) 1982-06-02 1984-11-20 The United States Of America As Represented By The Secretary Of The Air Force Multiple double heterojunction buried laser device
US4482906A (en) 1982-06-30 1984-11-13 International Business Machines Corporation Gallium aluminum arsenide integrated circuit structure using germanium
US4594000A (en) 1983-04-04 1986-06-10 Ball Corporation Method and apparatus for optically measuring distance and velocity
US4756007A (en) 1984-03-08 1988-07-05 Codex Corporation Adaptive communication rate modem
US4629821A (en) 1984-08-16 1986-12-16 Polaroid Corporation Photovoltaic cell
JPH069334B2 (en) 1984-09-03 1994-02-02 株式会社東芝 Optical / electrical integrated device
US4773063A (en) 1984-11-13 1988-09-20 University Of Delaware Optical wavelength division multiplexing/demultiplexing system
US4661176A (en) 1985-02-27 1987-04-28 The United States Of America As Represented By The Secretary Of The Air Force Process for improving the quality of epitaxial silicon films grown on insulating substrates utilizing oxygen ion conductor substrates
US4748485A (en) 1985-03-21 1988-05-31 Hughes Aircraft Company Opposed dual-gate hybrid structure for three-dimensional integrated circuits
JPH0511426B2 (en) 1985-05-08 1993-02-15 Mitsubishi Electric Corp
US4846926A (en) 1985-08-26 1989-07-11 Ford Aerospace & Communications Corporation HcCdTe epitaxially grown on crystalline support
DE3676019D1 (en) 1985-09-03 1991-01-17 Daido Steel Co Ltd Epitactic gallium arsenide semiconductor disc and method for their production.
JPH0518050B2 (en) 1985-09-06 1993-03-10 Yokogawa Electric Corp
JPH0415200B2 (en) 1985-11-18 1992-03-17 Nagoya Daigaku Gakucho
US4872046A (en) 1986-01-24 1989-10-03 University Of Illinois Heterojunction semiconductor device with <001> tilt
FR2595509B1 (en) 1986-03-07 1988-05-13 Thomson Csf Component epitaxy semiconductor material on a substrate parameter has different mesh and application to various semiconductor components
US4777613A (en) 1986-04-01 1988-10-11 Motorola Inc. Floating point numeric data processor
US4901133A (en) 1986-04-02 1990-02-13 Texas Instruments Incorporated Multilayer semi-insulating film for hermetic wafer passivation and method for making same
US4774205A (en) 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
US4891091A (en) 1986-07-14 1990-01-02 Gte Laboratories Incorporated Method of epitaxially growing compound semiconductor materials
US4888202A (en) 1986-07-31 1989-12-19 Nippon Telegraph And Telephone Corporation Method of manufacturing thin compound oxide film and apparatus for manufacturing thin oxide film
US5514885A (en) * 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
JP2516604B2 (en) 1986-10-17 1996-07-24 キヤノン株式会社 Method for manufacturing complementary MOS integrated circuit device
US5163118A (en) 1986-11-10 1992-11-10 The United States Of America As Represented By The Secretary Of The Air Force Lattice mismatched hetrostructure optical waveguide
US4772929A (en) 1987-01-09 1988-09-20 Sprague Electric Company Hall sensor with integrated pole pieces
US4876208A (en) 1987-01-30 1989-10-24 Yellowstone Diagnostics Corporation Diffraction immunoassay apparatus and method
US4868376A (en) 1987-05-15 1989-09-19 Smartcard International Inc. Intelligent portable interactive personal data system
US5511238A (en) 1987-06-26 1996-04-23 Texas Instruments Incorporated Monolithic microwave transmitter/receiver
DE3855246T2 (en) 1987-07-06 1996-12-05 Sumitomo Electric Industries Superconducting thin film and process for its production
JPS6414949A (en) 1987-07-08 1989-01-19 Nec Corp Semiconductor device and manufacture of the same
DE3851668T3 (en) 1987-07-24 1999-03-04 Matsushita Electric Ind Co Ltd Compound superconducting layer.
JPH0766922B2 (en) 1987-07-29 1995-07-19 株式会社村田製作所 Method for manufacturing semiconductor device
GB8718552D0 (en) 1987-08-05 1987-09-09 British Railways Board Track to train communications systems
US5081062A (en) 1987-08-27 1992-01-14 Prahalad Vasudev Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies
JPH0618290B2 (en) 1987-09-25 1994-03-09 松下電器産業株式会社 Microwave oscillator
JPH0695554B2 (en) 1987-10-12 1994-11-24 工業技術院長 Method for forming single crystal magnesia spinel film
US4885376A (en) 1987-10-13 1989-12-05 Iowa State University Research Foundation, Inc. New types of organometallic reagents and catalysts for asymmetric synthesis
US4802182A (en) 1987-11-05 1989-01-31 Xerox Corporation Monolithic two dimensional waveguide coupled cavity laser/modulator
US4981714A (en) 1987-12-14 1991-01-01 Sharp Kabushiki Kaisha Method of producing ferroelectric LiNb1-31 x Tax O3 0<x<1) thin film by activated evaporation
US5073981A (en) 1988-01-22 1991-12-17 At&T Bell Laboratories Optical communication by injection-locking to a signal which modulates an optical carrier
JPH01207920A (en) 1988-02-16 1989-08-21 Oki Electric Ind Co Ltd Manufacture of inp semiconductor thin film
JP2691721B2 (en) 1988-03-04 1997-12-17 富士通株式会社 Semiconductor thin film manufacturing method
US4912087A (en) 1988-04-15 1990-03-27 Ford Motor Company Rapid thermal annealing of superconducting oxide precursor films on Si and SiO2 substrates
US5130269A (en) 1988-04-27 1992-07-14 Fujitsu Limited Hetero-epitaxially grown compound semiconductor substrate and a method of growing the same
US5063166A (en) 1988-04-29 1991-11-05 Sri International Method of forming a low dislocation density semiconductor device
JPH01289108A (en) 1988-05-17 1989-11-21 Fujitsu Ltd Heteroepitaxy
US4910164A (en) 1988-07-27 1990-03-20 Texas Instruments Incorporated Method of making planarized heterostructures using selective epitaxial growth
US5221367A (en) 1988-08-03 1993-06-22 International Business Machines, Corp. Strained defect-free epitaxial mismatched heterostructures and method of fabrication
US4889402A (en) 1988-08-31 1989-12-26 American Telephone And Telegraph Company, At&T Bell Laboratories Electro-optic polarization modulation in multi-electrode waveguides
US4952420A (en) 1988-10-12 1990-08-28 Advanced Dielectric Technologies, Inc. Vapor deposition patterning method
DE68923756D1 (en) 1988-10-28 1995-09-14 Texas Instruments Inc Covered heat treatment.
US5286985A (en) 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
US5063081A (en) 1988-11-14 1991-11-05 I-Stat Corporation Method of manufacturing a plurality of uniform microfabricated sensing devices having an immobilized ligand receptor
US4965649A (en) 1988-12-23 1990-10-23 Ford Aerospace Corporation Manufacture of monolithic infrared focal plane arrays
US5227196A (en) 1989-02-16 1993-07-13 Semiconductor Energy Laboratory Co., Ltd. Method of forming a carbon film on a substrate made of an oxide material
US4999842A (en) 1989-03-01 1991-03-12 At&T Bell Laboratories Quantum well vertical cavity laser
US4990974A (en) 1989-03-02 1991-02-05 Thunderbird Technologies, Inc. Fermi threshold field effect transistor
US5260394A (en) 1989-03-20 1993-11-09 Idemitsu Kosan Co., Ltd. Styrene copolymer and process for production thereof
US4934777A (en) 1989-03-21 1990-06-19 Pco, Inc. Cascaded recirculating transmission line without bending loss limitations
US5198269A (en) 1989-04-24 1993-03-30 Battelle Memorial Institute Process for making sol-gel deposited ferroelectric thin films insensitive to their substrates
US5075743A (en) 1989-06-06 1991-12-24 Cornell Research Foundation, Inc. Quantum well optical device on silicon
US5143854A (en) 1989-06-07 1992-09-01 Affymax Technologies N.V. Large scale photolithographic solid phase synthesis of polypeptides and receptor binding screening thereof
US5067809A (en) 1989-06-09 1991-11-26 Oki Electric Industry Co., Ltd. Opto-semiconductor device and method of fabrication of the same
DE3923709A1 (en) 1989-07-18 1991-01-31 Standard Elektrik Lorenz Ag Optoelectronic arrangement
FR2650704B1 (en) 1989-08-01 1994-05-06 Thomson Csf Process for the manufacture by epitaxy of monocrystalline layers of materials with different mesh parameters
US5504035A (en) 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5055445A (en) 1989-09-25 1991-10-08 Litton Systems, Inc. Method of forming oxidic high Tc superconducting materials on substantially lattice matched monocrystalline substrates utilizing liquid phase epitaxy
US4959702A (en) 1989-10-05 1990-09-25 Motorola, Inc. Si-GaP-Si heterojunction bipolar transistor (HBT) on Si substrate
GB8922681D0 (en) 1989-10-09 1989-11-22 Secr Defence Oscillator
JPH03150218A (en) 1989-11-07 1991-06-26 Sumitomo Electric Ind Ltd Production of superconductive thin film
US5255031A (en) 1989-11-13 1993-10-19 Fuji Photo Film Co., Ltd. Data-retainable photographic film cartridge
US5648294A (en) * 1989-11-29 1997-07-15 Texas Instruments Incorp. Integrated circuit and method
US5051790A (en) 1989-12-22 1991-09-24 David Sarnoff Research Center, Inc. Optoelectronic interconnections for integrated circuits
JPH088214B2 (en) 1990-01-19 1996-01-29 三菱電機株式会社 Semiconductor device
US6362017B1 (en) 1990-02-28 2002-03-26 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using gallium nitride group compound
US5310707A (en) 1990-03-28 1994-05-10 Superconductivity Research Laboratory International Substrate material for the preparation of oxide superconductors
FR2661040A1 (en) 1990-04-13 1991-10-18 Thomson Csf Process for adapting two crystallized semiconductor materials and semiconductor device
US5358925A (en) 1990-04-18 1994-10-25 Board Of Trustees Of The Leland Stanford Junior University Silicon substrate having YSZ epitaxial barrier layer and an epitaxial superconducting layer
US5173474A (en) 1990-04-18 1992-12-22 Xerox Corporation Silicon substrate having an epitaxial superconducting layer thereon and method of making same
US5164359A (en) 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5122852A (en) 1990-04-23 1992-06-16 Bell Communications Research, Inc. Grafted-crystal-film integrated optics and optoelectronic devices
US5132648A (en) 1990-06-08 1992-07-21 Rockwell International Corporation Large array MMIC feedthrough
US5018816A (en) 1990-06-11 1991-05-28 Amp Incorporated Optical delay switch and variable delay system
US5608046A (en) 1990-07-27 1997-03-04 Isis Pharmaceuticals, Inc. Conjugated 4'-desmethyl nucleoside analog compounds
GB2250751B (en) 1990-08-24 1995-04-12 Kawasaki Heavy Ind Ltd Process for the production of dielectric thin films
DE4027024A1 (en) 1990-08-27 1992-03-05 Standard Elektrik Lorenz Ag Fiber gyro
US5281834A (en) 1990-08-31 1994-01-25 Motorola, Inc. Non-silicon and silicon bonded structure and method of manufacture
US5144409A (en) 1990-09-05 1992-09-01 Yale University Isotopically enriched semiconductor devices
US5442191A (en) 1990-09-05 1995-08-15 Yale University Isotopically enriched semiconductor devices
US5127067A (en) 1990-09-10 1992-06-30 Westinghouse Electric Corp. Local area network with star topology and ring protocol
DE4029060C2 (en) 1990-09-13 1994-01-13 Forschungszentrum Juelich Gmbh Process for the production of components for electronic, electro-optical and optical components
US5060031A (en) 1990-09-18 1991-10-22 Motorola, Inc Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices
US5119448A (en) 1990-09-21 1992-06-02 Tacan Corporation Modular micro-optical systems and method of making such systems
CA2052074A1 (en) 1990-10-29 1992-04-30 Victor Vali Integrated optics gyroscope sensor
US5880452A (en) 1990-11-15 1999-03-09 Geo Labs, Inc. Laser based PCMCIA data collection system with automatic triggering for portable applications and method of use
US5130762A (en) 1990-11-20 1992-07-14 Amp Incorporated Integrated quantum well feedback structure
US5418216A (en) 1990-11-30 1995-05-23 Fork; David K. Superconducting thin films on epitaxial magnesium oxide grown on silicon
JP3101321B2 (en) 1991-02-19 2000-10-23 富士通株式会社 Semiconductor device having isolation region containing oxygen and method of manufacturing the same
US5273911A (en) 1991-03-07 1993-12-28 Mitsubishi Denki Kabushiki Kaisha Method of producing a thin-film solar cell
KR940005454B1 (en) 1991-04-03 1994-06-18 김광호 Compound semiconductor device
US5482003A (en) 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
SE468267B (en) 1991-04-10 1992-11-30 Ericsson Telefon Ab L M Terminal foer a frequency divided, optical communication system
US5116461A (en) 1991-04-22 1992-05-26 Motorola, Inc. Method for fabricating an angled diffraction grating
US5221413A (en) 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
US5185589A (en) 1991-05-17 1993-02-09 Westinghouse Electric Corp. Microwave film bulk acoustic resonator and manifolded filter bank
US5194397A (en) 1991-06-05 1993-03-16 International Business Machines Corporation Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface
US5140651A (en) 1991-06-27 1992-08-18 The United States Of America As Represented By The Secretary Of The Air Force Semiconductive guided-wave programmable optical delay lines using electrooptic fabry-perot elements
US5312765A (en) 1991-06-28 1994-05-17 Hughes Aircraft Company Method of fabricating three dimensional gallium arsenide microelectronic device
EP0584410A1 (en) 1991-07-05 1994-03-02 Conductus, Inc. Superconducting electronic structures and methods of preparing same
DE69232236D1 (en) 1991-07-16 2002-01-10 Asahi Chemical Ind Semiconductor sensor and its manufacturing method
JP3130575B2 (en) 1991-07-25 2001-01-31 日本電気株式会社 Microwave and millimeter wave transceiver module
US5306649A (en) 1991-07-26 1994-04-26 Avantek, Inc. Method for producing a fully walled emitter-base structure in a bipolar transistor
DE69223009T2 (en) 1991-08-02 1998-04-02 Canon Kk Liquid crystal display unit
US5357122A (en) 1991-09-05 1994-10-18 Sony Corporation Three-dimensional optical-electronic integrated circuit device with raised sections
DE69233314D1 (en) 1991-10-11 2004-04-08 Canon Kk Process for the production of semiconductor products
US5173835A (en) 1991-10-15 1992-12-22 Motorola, Inc. Voltage variable capacitor
DE4135076A1 (en) 1991-10-24 1993-04-29 Daimler Benz Ag Multilayered, monocristalline silicon carbide composition
US5283462A (en) 1991-11-04 1994-02-01 Motorola, Inc. Integrated distributed inductive-capacitive network
US5208182A (en) 1991-11-12 1993-05-04 Kopin Corporation Dislocation density reduction in gallium arsenide on silicon heterostructures
US5216729A (en) 1991-11-18 1993-06-01 Harmonic Lightwaves, Inc. Active alignment system for laser to fiber coupling
US5397428A (en) 1991-12-20 1995-03-14 The University Of North Carolina At Chapel Hill Nucleation enhancement for chemical vapor deposition of diamond
EP0548391B1 (en) 1991-12-21 1997-07-23 Deutsche ITT Industries GmbH Offset compensated Hall-sensor
JP3416163B2 (en) 1992-01-31 2003-06-16 キヤノン株式会社 Semiconductor substrate and manufacturing method thereof
JP3250673B2 (en) 1992-01-31 2002-01-28 キヤノン株式会社 Semiconductor element substrate and method of manufacturing the same
US5155658A (en) 1992-03-05 1992-10-13 Bell Communications Research, Inc. Crystallographically aligned ferroelectric films usable in memories and method of crystallographically aligning perovskite films
US5270298A (en) 1992-03-05 1993-12-14 Bell Communications Research, Inc. Cubic metal oxide thin film epitaxially grown on silicon
TW232079B (en) 1992-03-17 1994-10-11 Wisconsin Alumni Res Found
US5244818A (en) 1992-04-08 1993-09-14 Georgia Tech Research Corporation Processes for lift-off of thin film materials and for the fabrication of three dimensional integrated circuits
JP3379106B2 (en) 1992-04-23 2003-02-17 セイコーエプソン株式会社 Liquid jet head
US5326721A (en) 1992-05-01 1994-07-05 Texas Instruments Incorporated Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer
EP0568064B1 (en) 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US5442561A (en) 1992-05-12 1995-08-15 Nippon Telegraph And Telephone Corporation Production management system and its application method
JPH08501900A (en) 1992-06-17 1996-02-27 ハリス・コーポレーション Bonded wafer manufacturing method
US5266355A (en) 1992-06-18 1993-11-30 Eastman Kodak Company Chemical vapor deposition of metal oxide films
US5399898A (en) 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5572052A (en) 1992-07-24 1996-11-05 Mitsubishi Denki Kabushiki Kaisha Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer
US5296721A (en) 1992-07-31 1994-03-22 Hughes Aircraft Company Strained interband resonant tunneling negative resistance diode
US5602418A (en) 1992-08-07 1997-02-11 Asahi Kasei Kogyo Kabushiki Kaisha Nitride based semiconductor device and manufacture thereof
US5438584A (en) 1992-09-22 1995-08-01 Xerox Corporation Dual polarization laser diode with quaternary material system
US5314547A (en) 1992-09-28 1994-05-24 General Motors Corporation Rare earth slab doping of group III-V compounds
JP3286921B2 (en) 1992-10-09 2002-05-27 富士通株式会社 Silicon substrate compound semiconductor device
US5356509A (en) 1992-10-16 1994-10-18 Astropower, Inc. Hetero-epitaxial growth of non-lattice matched semiconductors
US5514484A (en) 1992-11-05 1996-05-07 Fuji Xerox Co., Ltd. Oriented ferroelectric thin film
JPH06151872A (en) 1992-11-09 1994-05-31 Mitsubishi Kasei Corp Fet device
DE69331538D1 (en) 1992-12-01 2002-03-21 Matsushita Electric Ind Co Ltd Process for producing an electrical thin film
US5323023A (en) 1992-12-02 1994-06-21 Xerox Corporation Epitaxial magnesium oxide as a buffer layer on (111) tetrahedral semiconductors
US5248564A (en) 1992-12-09 1993-09-28 Bell Communications Research, Inc. C-axis perovskite thin films grown on silicon dioxide
US5347157A (en) 1992-12-17 1994-09-13 Eastman Kodak Company Multilayer structure having a (111)-oriented buffer layer
JPH06196648A (en) 1992-12-25 1994-07-15 Fuji Xerox Co Ltd Oriented ferroelectric thin film device
JPH06303137A (en) 1992-12-29 1994-10-28 Hitachi Ltd D/a converter, offset adjustment circuit and portable communication terminal equipment using them
US5352926A (en) 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making
EP0606821A1 (en) 1993-01-11 1994-07-20 International Business Machines Corporation Modulated strain heterostructure light emitting devices
JP3047656B2 (en) 1993-01-12 2000-05-29 株式会社村田製作所 Method for producing InSb thin film
US5371734A (en) 1993-01-29 1994-12-06 Digital Ocean, Inc. Medium access control protocol for wireless network
AU6132494A (en) 1993-03-12 1994-09-26 Neocera, Inc. Superconducting films on alkaline earth fluoride substrates with multiple buffer layers
US5334556A (en) 1993-03-23 1994-08-02 Texas Instruments Incorporated Method for improving gate oxide integrity using low temperature oxidation during source/drain anneal
US5293050A (en) 1993-03-25 1994-03-08 International Business Machines Corporation Semiconductor quantum dot light emitting/detecting devices
US5452118A (en) 1993-04-20 1995-09-19 Spire Corporation Optical heterodyne receiver for fiber optic communications system
US5955591A (en) 1993-05-12 1999-09-21 Imbach; Jean-Louis Phosphotriester oligonucleotides, amidites and method of preparation
US5815084A (en) 1993-05-20 1998-09-29 Harrow Products, Inc. Programmer for contact readable electronic control system and programming method therefor
JPH06338630A (en) 1993-05-28 1994-12-06 Omron Corp Semiconductor light-emitting element, and optical detector, optical information processor, optical coupler and light-emitting device using the light-emitting element
US5456205A (en) 1993-06-01 1995-10-10 Midwest Research Institute System for monitoring the growth of crystalline films on stationary substrates
US5312790A (en) 1993-06-09 1994-05-17 The United States Of America As Represented By The Secretary Of The Army Ceramic ferroelectric material
JP3244205B2 (en) 1993-06-17 2002-01-07 信越半導体株式会社 Semiconductor device
JPH0714853A (en) 1993-06-18 1995-01-17 Fujitsu Ltd Compound semiconductor device on silicon substrate and manufacture thereof
US5444016A (en) 1993-06-25 1995-08-22 Abrokwah; Jonathan K. Method of making ohmic contacts to a complementary III-V semiconductor device
US5480829A (en) 1993-06-25 1996-01-02 Motorola, Inc. Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts
US6048751A (en) 1993-06-25 2000-04-11 Lucent Technologies Inc. Process for manufacture of composite semiconductor devices
US5572040A (en) 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
US5394489A (en) 1993-07-27 1995-02-28 At&T Corp. Wavelength division multiplexed optical communication transmitters
US6139483A (en) 1993-07-27 2000-10-31 Texas Instruments Incorporated Method of forming lateral resonant tunneling devices
US5450812A (en) 1993-07-30 1995-09-19 Martin Marietta Energy Systems, Inc. Process for growing a film epitaxially upon an oxide surface and structures formed with the process
US5682046A (en) 1993-08-12 1997-10-28 Fujitsu Limited Heterojunction bipolar semiconductor device and its manufacturing method
JP3333325B2 (en) 1993-08-26 2002-10-15 株式会社東芝 Semiconductor device, semiconductor device simulation method, and semiconductor device simulator
US5792679A (en) 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5753928A (en) 1993-09-30 1998-05-19 Siemens Components, Inc. Monolithic optical emitter-detector
DE69431333T2 (en) 1993-10-08 2003-07-31 Mitsubishi Cable Ind Ltd GaN single crystal
JPH07115244A (en) 1993-10-19 1995-05-02 Toyota Motor Corp Semiconductor laser and its fabrication
US5650362A (en) 1993-11-04 1997-07-22 Fuji Xerox Co. Oriented conductive film and process for preparing the same
US5549977A (en) 1993-11-18 1996-08-27 Lucent Technologies Inc. Article comprising magnetoresistive material
BE1007865A3 (en) 1993-12-10 1995-11-07 Philips Electronics Nv Tunnel of permanent switch wiring element with different situations.
BE1007902A3 (en) 1993-12-23 1995-11-14 Philips Electronics Nv Switching element with memory with schottky barrier tunnel.
JP3395318B2 (en) 1994-01-07 2003-04-14 住友化学工業株式会社 Method for growing group 3-5 compound semiconductor crystal
US5576879A (en) 1994-01-14 1996-11-19 Fuji Xerox Co., Ltd. Composite optical modulator
US5623552A (en) 1994-01-21 1997-04-22 Cardguard International, Inc. Self-authenticating identification card with fingerprint identification
US5679152A (en) 1994-01-27 1997-10-21 Advanced Technology Materials, Inc. Method of making a single crystals Ga*N article
US5561305A (en) 1994-02-16 1996-10-01 The United States Of America As Represented By The Secretary Of The Army Method and apparatus for performing internal device structure analysis of a dual channel transistor by multiple-frequency Schubnikov-de Haas analysis
US5538941A (en) 1994-02-28 1996-07-23 University Of Maryland Superconductor/insulator metal oxide hetero structure for electric field tunable microwave device
GB2287327A (en) 1994-03-02 1995-09-13 Sharp Kk Electro-optic apparatus
JP3360105B2 (en) 1994-03-04 2002-12-24 富士通株式会社 Method for manufacturing semiconductor device
JP2985691B2 (en) 1994-03-23 1999-12-06 株式会社デンソー Semiconductor device
US5962883A (en) 1994-03-23 1999-10-05 Lucent Technologies Inc. Article comprising an oxide layer on a GaAs-based semiconductor body
JP3015656B2 (en) 1994-03-23 2000-03-06 株式会社東芝 Method and apparatus for producing semi-insulating GaAs single crystal
US6469357B1 (en) 1994-03-23 2002-10-22 Agere Systems Guardian Corp. Article comprising an oxide layer on a GaAs or GaN-based semiconductor body
JP3330218B2 (en) 1994-03-25 2002-09-30 三菱電機株式会社 Semiconductor device manufacturing method and semiconductor device
US5481102A (en) 1994-03-31 1996-01-02 Hazelrigg, Jr.; George A. Micromechanical/microelectromechanical identification devices and methods of fabrication and encoding thereof
US5478653A (en) * 1994-04-04 1995-12-26 Guenzer; Charles S. Bismuth titanate as a template layer for growth of crystallographically oriented silicon
US5689123A (en) 1994-04-07 1997-11-18 Sdl, Inc. III-V aresenide-nitride semiconductor materials and devices
US5716450A (en) 1994-04-08 1998-02-10 Japan Energy Corporation Growing method of gallium nitride related compound semiconductor crystal and gallium nitride related compound semiconductor device
US5883564A (en) 1994-04-18 1999-03-16 General Motors Corporation Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer
US5528414A (en) 1994-05-05 1996-06-18 Lots Technology Two dimensional electro-optic modulator array
US5491461A (en) 1994-05-09 1996-02-13 General Motors Corporation Magnetic field sensor on elemental semiconductor substrate with electric field reduction means
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP2643833B2 (en) 1994-05-30 1997-08-20 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
JP3460095B2 (en) 1994-06-01 2003-10-27 富士通株式会社 Ferroelectric memory
US5436759A (en) 1994-06-14 1995-07-25 The Regents Of The University Of California Cross-talk free, low-noise optical amplifier
DE4421007A1 (en) 1994-06-18 1995-12-21 Philips Patentverwaltung Electronic component and method for its production
JP2901493B2 (en) 1994-06-27 1999-06-07 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
US5589284A (en) 1994-08-01 1996-12-31 Texas Instruments Incorporated Electrodes comprising conductive perovskite-seed layers for perovskite dielectrics
US5828080A (en) 1994-08-17 1998-10-27 Tdk Corporation Oxide thin film, electronic device substrate and electronic device
US5838029A (en) 1994-08-22 1998-11-17 Rohm Co., Ltd. GaN-type light emitting device formed on a silicon substrate
JPH0864596A (en) 1994-08-25 1996-03-08 Fujitsu Ltd Semiconductor device and its manufacture
US5811839A (en) 1994-09-01 1998-09-22 Mitsubishi Chemical Corporation Semiconductor light-emitting devices
US5873977A (en) 1994-09-02 1999-02-23 Sharp Kabushiki Kaisha Dry etching of layer structure oxides
US5504183A (en) 1994-09-12 1996-04-02 Motorola Organometallic fluorescent complex polymers for light emitting applications
JPH0890832A (en) 1994-09-27 1996-04-09 Oki Electric Ind Co Ltd Light emitting element array and optical head
US5635741A (en) 1994-09-30 1997-06-03 Texas Instruments Incorporated Barium strontium titanate (BST) thin films by erbium donor doping
US5479317A (en) 1994-10-05 1995-12-26 Bell Communications Research, Inc. Ferroelectric capacitor heterostructure and method of making same
US5473047A (en) 1994-10-11 1995-12-05 Motorola, Inc. Soluble precursor to poly (cyanoterephthalydene) and method of preparation
US5778018A (en) 1994-10-13 1998-07-07 Nec Corporation VCSELs (vertical-cavity surface emitting lasers) and VCSEL-based devices
US5985356A (en) 1994-10-18 1999-11-16 The Regents Of The University Of California Combinatorial synthesis of novel materials
US5486406A (en) 1994-11-07 1996-01-23 Motorola Green-emitting organometallic complexes for use in light emitting devices
US5677551A (en) 1994-11-15 1997-10-14 Fujitsu Limited Semiconductor optical device and an optical processing system that uses such a semiconductor optical system
US5519235A (en) 1994-11-18 1996-05-21 Bell Communications Research, Inc. Polycrystalline ferroelectric capacitor heterostructure employing hybrid electrodes
JPH08148968A (en) 1994-11-24 1996-06-07 Mitsubishi Electric Corp Thin film piezoelectric element
KR0148596B1 (en) 1994-11-28 1998-10-15 양승택 Superconducting field effect device with grain boundary channel and method for making the same
US5777350A (en) 1994-12-02 1998-07-07 Nichia Chemical Industries, Ltd. Nitride semiconductor light-emitting device
JP2679653B2 (en) 1994-12-05 1997-11-19 日本電気株式会社 Semiconductor device
US5834362A (en) 1994-12-14 1998-11-10 Fujitsu Limited Method of making a device having a heteroepitaxial substrate
US5937274A (en) 1995-01-31 1999-08-10 Hitachi, Ltd. Fabrication method for AlGaIn NPAsSb based devices
US5552547A (en) 1995-02-13 1996-09-03 Shi; Song Q. Organometallic complexes with built-in fluorescent dyes for use in light emitting devices
US5610744A (en) 1995-02-16 1997-03-11 Board Of Trustees Of The University Of Illinois Optical communications and interconnection networks having opto-electronic switches and direct optical routers
US5530235A (en) 1995-02-16 1996-06-25 Xerox Corporation Interactive contents revealing storage device
WO1996029725A1 (en) 1995-03-21 1996-09-26 Northern Telecom Limited Ferroelectric dielectric for integrated circuit applications at microwave frequencies
US5679965A (en) 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5670798A (en) 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US6088216A (en) 1995-04-28 2000-07-11 International Business Machines Corporation Lead silicate based capacitor structures
US6051858A (en) 1996-07-26 2000-04-18 Symetrix Corporation Ferroelectric/high dielectric constant integrated circuit and method of fabricating same
US5606184A (en) 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making
US5528067A (en) 1995-05-08 1996-06-18 Hughes Aircraft Company Magnetic field detection
US5926496A (en) 1995-05-25 1999-07-20 Northwestern University Semiconductor micro-resonator device
US5825799A (en) 1995-05-25 1998-10-20 Northwestern University Microcavity semiconductor laser
US5790583A (en) 1995-05-25 1998-08-04 Northwestern University Photonic-well Microcavity light emitting devices
US5614739A (en) 1995-06-02 1997-03-25 Motorola HIGFET and method
JP3335075B2 (en) 1995-06-06 2002-10-15 キヤノン株式会社 Network system, node device, and transmission control method
KR100189966B1 (en) 1995-06-13 1999-06-01 윤종용 Mos transistor of soi structure and method for manufacturing the same
US5753300A (en) 1995-06-19 1998-05-19 Northwestern University Oriented niobate ferroelectric thin films for electrical and optical devices and method of making such films
JP4063896B2 (en) 1995-06-20 2008-03-19 Tdk株式会社 Colored see-through photovoltaic device
EP0972309A4 (en) 1995-06-28 2000-01-19 Telcordia Tech Inc Barrier layer for ferroelectric capacitor integrated on silicon
US6011641A (en) 1995-07-06 2000-01-04 Korea Advanced Institute Of Science And Technology Wavelength insensitive passive polarization converter employing electro-optic polymer waveguides
US5621227A (en) 1995-07-18 1997-04-15 Discovery Semiconductors, Inc. Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy
US5753934A (en) 1995-08-04 1998-05-19 Tok Corporation Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film
US5551238A (en) 1995-08-23 1996-09-03 Prueitt; Melvin L. Hydro-air renewable power system
JPH0964477A (en) 1995-08-25 1997-03-07 Toshiba Corp Semiconductor light emitting element and its manufacture
US5633724A (en) 1995-08-29 1997-05-27 Hewlett-Packard Company Evanescent scanning of biochemical array
US5635433A (en) 1995-09-11 1997-06-03 The United States Of America As Represented By The Secretary Of The Army Ceramic ferroelectric composite material-BSTO-ZnO
DE69524751D1 (en) 1995-09-21 2002-01-31 Alcatel Sa Optical gain combining arrangement and method for uplink transmission using such an arrangement
JPH09113767A (en) 1995-09-29 1997-05-02 Motorola Inc Electronic part to match optical transmission structure
US5783495A (en) 1995-11-13 1998-07-21 Micron Technology, Inc. Method of wafer cleaning, and system and cleaning solution regarding same
US5659180A (en) 1995-11-13 1997-08-19 Motorola Heterojunction interband tunnel diodes with improved P/V current ratios
DE69525535T2 (en) 1995-11-21 2002-11-28 St Microelectronics Srl Adaptive optical sensor
JP3645338B2 (en) 1995-12-11 2005-05-11 株式会社東芝 Nonvolatile semiconductor memory device
JP3396356B2 (en) 1995-12-11 2003-04-14 三菱電機株式会社 Semiconductor device and method of manufacturing the same
US6022963A (en) 1995-12-15 2000-02-08 Affymetrix, Inc. Synthesis of oligonucleotide arrays using photocleavable protecting groups
KR100199095B1 (en) 1995-12-27 1999-06-15 구본준 Capacitor of semiconductor memory device and its fabrication method
US5861966A (en) 1995-12-27 1999-01-19 Nynex Science & Technology, Inc. Broad band optical fiber telecommunications network
JP3036424B2 (en) 1996-01-12 2000-04-24 日本電気株式会社 Optical repeater with signal regeneration function
US5729394A (en) 1996-01-24 1998-03-17 Hewlett-Packard Company Multi-direction optical data port
US5745631A (en) 1996-01-26 1998-04-28 Irvine Sensors Corporation Self-aligning optical beam system
FR2744578B1 (en) 1996-02-06 1998-04-30 Motorola Semiconducteurs High frequency amplifier
DE19607107A1 (en) 1996-02-26 1997-08-28 Sel Alcatel Ag Light conductor to opto-electronic component coupling apparatus for optical communications
US5833603A (en) 1996-03-13 1998-11-10 Lipomatrix, Inc. Implantable biosensing transponder
US5801072A (en) 1996-03-14 1998-09-01 Lsi Logic Corporation Method of packaging integrated circuits
US5792569A (en) 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials
DE19712496A1 (en) 1996-03-26 1997-10-30 Mitsubishi Materials Corp Piezoelectric thin-film component
JPH09270558A (en) 1996-03-29 1997-10-14 Fuji Photo Film Co Ltd Semiconductor laser
WO1997039354A1 (en) 1996-04-16 1997-10-23 Kishimoto, Tadamitsu Method of detecting solid cancer cells and histological heterotypia and method of examining tissue for bone marrow transplantation and peripheral blood stem cell transplantation
US5981980A (en) 1996-04-22 1999-11-09 Sony Corporation Semiconductor laminating structure
TW410272B (en) 1996-05-07 2000-11-01 Thermoscan Lnc Enhanced protective lens cover
US5729641A (en) 1996-05-30 1998-03-17 Sdl, Inc. Optical device employing edge-coupled waveguide geometry
DE69730377D1 (en) 1996-05-30 2004-09-30 Oki Electric Ind Co Ltd Permanent semiconductor memory cell and its manufacturing process
US5733641A (en) 1996-05-31 1998-03-31 Xerox Corporation Buffered substrate for semiconductor devices
SE518132C2 (en) 1996-06-07 2002-08-27 Ericsson Telefon Ab L M Method and apparatus for synchronizing the transceivers in a cellular system
US5838851A (en) 1996-06-24 1998-11-17 Trw Inc. Optical-loop signal processing using reflection mechanisms
JP3193302B2 (en) 1996-06-26 2001-07-30 ティーディーケイ株式会社 Film structure, electronic device, recording medium, and method of manufacturing ferroelectric thin film
US6039803A (en) 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US5863326A (en) 1996-07-03 1999-01-26 Cermet, Inc. Pressurized skull crucible for crystal growth using the Czochralski technique
US6367699B2 (en) 1996-07-11 2002-04-09 Intermec Ip Corp. Method and apparatus for utilizing specular light to image low contrast symbols
US5858814A (en) 1996-07-17 1999-01-12 Lucent Technologies Inc. Hybrid chip and method therefor
IL119006A (en) 1996-08-04 2001-04-30 B G Negev Technologies And App Tunable delay line optical filters
US5830270A (en) 1996-08-05 1998-11-03 Lockheed Martin Energy Systems, Inc. CaTiO3 Interfacial template structure on semiconductor-based material and the growth of electroceramic thin-films in the perovskite class
US6023082A (en) 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
US5734672A (en) 1996-08-06 1998-03-31 Cutting Edge Optronics, Inc. Smart laser diode array assembly and operating method using same
EP0917719A2 (en) 1996-08-12 1999-05-26 Energenius, Inc. Semiconductor supercapacitor system, method for making same and articles produced therefrom
US5987011A (en) 1996-08-30 1999-11-16 Chai-Keong Toh Routing method for Ad-Hoc mobile networks
US5767543A (en) 1996-09-16 1998-06-16 Motorola, Inc. Ferroelectric semiconductor device having a layered ferroelectric structure
US5789733A (en) 1996-09-20 1998-08-04 Motorola, Inc. Smart card with contactless optical interface
US5764676A (en) 1996-09-26 1998-06-09 Xerox Corporation Transversely injected multiple wavelength diode laser array formed by layer disordering
JPH10126350A (en) 1996-10-15 1998-05-15 Nec Corp Optical network, optical branch insertion node, and fault recovery system
US5725641A (en) 1996-10-30 1998-03-10 Macleod; Cheryl A. Lightfast inks for ink-jet printing
US5953468A (en) 1996-11-01 1999-09-14 Mendez R&D Associates Scalable, quantized, delay-line array based on nested, generalized spirals
DE69720041T2 (en) 1996-11-14 2004-01-08 Affymetrix, Inc., Santa Clara Chemical amplification for synthesis of sample orders
US5912068A (en) 1996-12-05 1999-06-15 The Regents Of The University Of California Epitaxial oxides on amorphous SiO2 on single crystal silicon
JPH10223929A (en) 1996-12-05 1998-08-21 Showa Denko Kk Substrate for algainp light emitting element
US6320238B1 (en) 1996-12-23 2001-11-20 Agere Systems Guardian Corp. Gate structure for integrated circuit fabrication
US5741724A (en) 1996-12-27 1998-04-21 Motorola Method of growing gallium nitride on a spinel substrate
US5778116A (en) 1997-01-23 1998-07-07 Tomich; John L. Photonic home area network fiber/power insertion apparatus
US5812272A (en) 1997-01-30 1998-09-22 Hewlett-Packard Company Apparatus and method with tiled light source array for integrated assay sensing
US5864543A (en) 1997-02-24 1999-01-26 At&T Wireless Services, Inc. Transmit/receive compensation in a time division duplex system
CN1124494C (en) 1997-02-28 2003-10-15 旭化成电子株式会社 Magnetic sensor
US5952695A (en) 1997-03-05 1999-09-14 International Business Machines Corporation Silicon-on-insulator and CMOS-on-SOI double film structures
US5872493A (en) 1997-03-13 1999-02-16 Nokia Mobile Phones, Ltd. Bulk acoustic wave (BAW) filter having a top portion that includes a protective acoustic mirror
US6211096B1 (en) 1997-03-21 2001-04-03 Lsi Logic Corporation Tunable dielectric constant oxide and method of manufacture
EP0993027A4 (en) 1997-03-28 2002-05-29 Sharp Kk Method for manufacturing compound semiconductors
US6008762A (en) 1997-03-31 1999-12-28 Qualcomm Incorporated Folded quarter-wave patch antenna
US6114996A (en) 1997-03-31 2000-09-05 Qualcomm Incorporated Increased bandwidth patch antenna
FR2761811B1 (en) 1997-04-03 1999-07-16 France Telecom Engraving-free technology for integrating components
WO1998047170A1 (en) 1997-04-11 1998-10-22 Nichia Chemical Industries, Ltd. Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device
US5857049A (en) 1997-05-05 1999-01-05 Lucent Technologies, Inc., Precision alignment of optoelectronic devices
WO1998052280A1 (en) 1997-05-13 1998-11-19 Mitsubishi Denki Kabushiki Kaisha Piezoelectric thin film device
US5984190A (en) 1997-05-15 1999-11-16 Micron Technology, Inc. Method and apparatus for identifying integrated circuits
US6103403A (en) 1997-05-15 2000-08-15 University Of Kentucky Research Foundation Intellectual Property Development Clathrate structure for electronic and electro-optic applications
US5926493A (en) 1997-05-20 1999-07-20 Sdl, Inc. Optical semiconductor device with diffraction grating structure
US5937285A (en) 1997-05-23 1999-08-10 Motorola, Inc. Method of fabricating submicron FETs with low temperature group III-V material
EP0881669B1 (en) 1997-05-30 2005-12-14 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Manufacturing process of a germanium implanted heterojunction bipolar transistor
US6150239A (en) 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
KR100243294B1 (en) 1997-06-09 2000-02-01 윤종용 Ferroelectric memory cell &array in semiconductor device
DE19725900C2 (en) 1997-06-13 2003-03-06 Dieter Bimberg Process for the deposition of gallium nitride on silicon substrates
CA2295069A1 (en) 1997-06-24 1998-12-30 Eugene A. Fitzgerald Controlling threading dislocation densities in ge on si using graded gesi layers and planarization
US5869845A (en) 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
US6153454A (en) 1997-07-09 2000-11-28 Advanced Micro Devices, Inc. Convex device with selectively doped channel
US5852687A (en) 1997-07-09 1998-12-22 Trw Inc. Integrated optical time delay unit
JP3813740B2 (en) 1997-07-11 2006-08-23 Tdk株式会社 Substrates for electronic devices
US5963291A (en) 1997-07-21 1999-10-05 Chorum Technologies Inc. Optical attenuator using polarization modulation and a feedback controller
US6078717A (en) 1997-07-22 2000-06-20 Fuji Xerox Co., Ltd. Opical waveguide device
US6013553A (en) 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US5962069A (en) 1997-07-25 1999-10-05 Symetrix Corporation Process for fabricating layered superlattice materials and AB03 type metal oxides without exposure to oxygen at high temperatures
US6222654B1 (en) 1997-08-04 2001-04-24 Lucent Technologies, Inc. Optical node system for a ring architecture and method thereof
US5940691A (en) 1997-08-20 1999-08-17 Micron Technology, Inc. Methods of forming SOI insulator layers and methods of forming transistor devices
US5907792A (en) 1997-08-25 1999-05-25 Motorola,Inc. Method of forming a silicon nitride layer
JP4221765B2 (en) 1997-08-29 2009-02-12 ソニー株式会社 Optical integrated oxide device and method for manufacturing optical integrated oxide device
US6278138B1 (en) 1998-08-28 2001-08-21 Sony Corporation Silicon-based functional matrix substrate and optical integrated oxide device
US6002375A (en) 1997-09-02 1999-12-14 Motorola, Inc. Multi-substrate radio-frequency circuit
US5981400A (en) 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US6184144B1 (en) 1997-10-10 2001-02-06 Cornell Research Foundation, Inc. Methods for growing defect-free heteroepitaxial layers
US6265749B1 (en) 1997-10-14 2001-07-24 Advanced Micro Devices, Inc. Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant
US6058131A (en) 1997-11-17 2000-05-02 E-Tek Dynamics, Inc. Wavelength stabilization of laser source using fiber Bragg grating feedback
JP3658160B2 (en) 1997-11-17 2005-06-08 キヤノン株式会社 Molding machine
US6197503B1 (en) 1997-11-26 2001-03-06 Ut-Battelle, Llc Integrated circuit biochip microsystem containing lens
US6277436B1 (en) 1997-11-26 2001-08-21 Advanced Technology Materials, Inc. Liquid delivery MOCVD process for deposition of high frequency dielectric materials
US6049702A (en) 1997-12-04 2000-04-11 Rockwell Science Center, Llc Integrated passive transceiver section
JP3092659B2 (en) 1997-12-10 2000-09-25 日本電気株式会社 Thin film capacitor and method of manufacturing the same
US6069368A (en) 1997-12-15 2000-05-30 Texas Instruments Incorporated Method for growing high-quality crystalline Si quantum wells for RTD structures
US6020222A (en) 1997-12-16 2000-02-01 Advanced Micro Devices, Inc. Silicon oxide insulator (SOI) semiconductor having selectively linked body
US5966323A (en) 1997-12-18 1999-10-12 Motorola, Inc. Low switching field magnetoresistive tunneling junction for high density arrays
US5963949A (en) 1997-12-22 1999-10-05 Amazon.Com, Inc. Method for data gathering around forms and search barriers
EP0926739A1 (en) 1997-12-24 1999-06-30 Texas Instruments Incorporated A structure of and method for forming a mis field effect transistor
US6093302A (en) 1998-01-05 2000-07-25 Combimatrix Corporation Electrochemical solid phase synthesis
US5977567A (en) 1998-01-06 1999-11-02 Lightlogic, Inc. Optoelectronic assembly and method of making the same
US6278523B1 (en) 1998-02-13 2001-08-21 Centre National De La Recherche Scientifique-Cnrs Optical sensor on a silicon substrate and application for the in situ measurement of a fluorescent marker in the small bronchia
EP0950974B1 (en) 1998-02-20 2001-10-24 STOCKO Contact GmbH &amp; Co. KG Vertically installable, compact chipcard reader
US6069581A (en) 1998-02-20 2000-05-30 Amerigon High performance vehicle radar system
GB2334594A (en) 1998-02-20 1999-08-25 Fujitsu Telecommunications Eur Arrayed waveguide grating device
US6011646A (en) 1998-02-20 2000-01-04 The Regents Of The Unviersity Of California Method to adjust multilayer film stress induced deformation of optics
JPH11274467A (en) 1998-03-26 1999-10-08 Murata Mfg Co Ltd Photo-electronic integrated-circuit device
CA2268997C (en) 1998-05-05 2005-03-22 National Research Council Of Canada Quantum dot infrared photodetectors (qdip) and methods of making the same
JPH11330411A (en) 1998-05-13 1999-11-30 Matsushita Electric Ind Co Ltd Semiconductor storage device and its manufacture
US6055179A (en) 1998-05-19 2000-04-25 Canon Kk Memory device utilizing giant magnetoresistance effect
US6064078A (en) 1998-05-22 2000-05-16 Xerox Corporation Formation of group III-V nitride films on sapphire substrates with reduced dislocation densities
DE69801648T2 (en) 1998-05-25 2002-04-18 Alcatel Sa Optoelectronic module with at least one optoelectronic component and method for temperature stabilization
JP3171170B2 (en) * 1998-05-25 2001-05-28 日本電気株式会社 Thin film capacitor and method of manufacturing the same
FI108583B (en) 1998-06-02 2002-02-15 Nokia Corp resonator structures
US6372356B1 (en) 1998-06-04 2002-04-16 Xerox Corporation Compliant substrates for growing lattice mismatched films
US6113690A (en) 1998-06-08 2000-09-05 Motorola, Inc. Method of preparing crystalline alkaline earth metal oxides on a Si substrate
JPH11354820A (en) 1998-06-12 1999-12-24 Sharp Corp Photoelectric conversion element and manufacture thereof
FR2779843A1 (en) 1998-06-16 1999-12-17 Busless Computers Serial multi port memory component comprising RAM memory bank assemblies for use in computer
US6338756B2 (en) 1998-06-30 2002-01-15 Seh America, Inc. In-situ post epitaxial treatment process
KR20000003975A (en) 1998-06-30 2000-01-25 김영환 Method for manufacturing bonding-type soi wafer having a field oxide
US6121642A (en) 1998-07-20 2000-09-19 International Business Machines Corporation Junction mott transition field effect transistor (JMTFET) and switch for logic and memory applications
US6128178A (en) 1998-07-20 2000-10-03 International Business Machines Corporation Very thin film capacitor for dynamic random access memory (DRAM)
US6103008A (en) 1998-07-30 2000-08-15 Ut-Battelle, Llc Silicon-integrated thin-film structure for electro-optic applications
US6393167B1 (en) 1998-07-31 2002-05-21 Monica K. Davis Fast, environmentally-stable fiber switches using a Sagnac interferometer
US6300615B1 (en) 1998-08-31 2001-10-09 Canon Kabushiki Kaisha Photoelectric conversion apparatus
US6022410A (en) 1998-09-01 2000-02-08 Motorola, Inc. Alkaline-earth metal silicides on silicon
JP3289683B2 (en) 1998-09-04 2002-06-10 株式会社村田製作所 Semiconductor light emitting device
JP3159255B2 (en) 1998-09-16 2001-04-23 日本電気株式会社 Sputter growth method for electrodes used in ferroelectric capacitors
US6191011B1 (en) 1998-09-28 2001-02-20 Ag Associates (Israel) Ltd. Selective hemispherical grain silicon deposition
US6252261B1 (en) 1998-09-30 2001-06-26 Nec Corporation GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor
TW399309B (en) 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
US6343171B1 (en) 1998-10-09 2002-01-29 Fujitsu Limited Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making
JP3592553B2 (en) 1998-10-15 2004-11-24 株式会社東芝 Gallium nitride based semiconductor device
JP3430036B2 (en) 1998-10-29 2003-07-28 松下電器産業株式会社 Method for forming thin film and method for manufacturing semiconductor light emitting device
US6355939B1 (en) 1998-11-03 2002-03-12 Lockheed Martin Corporation Multi-band infrared photodetector
US6255198B1 (en) 1998-11-24 2001-07-03 North Carolina State University Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
FR2786887B1 (en) 1998-12-08 2001-01-26 Cit Alcatel Semiconductor phase modulator
JP3050542B1 (en) 1998-12-18 2000-06-12 有限会社新城製作所 Screws with holed heads and their driver bits
US6143366A (en) 1998-12-24 2000-11-07 Lu; Chung Hsin High-pressure process for crystallization of ceramic films at low temperatures
US6173474B1 (en) 1999-01-08 2001-01-16 Fantom Technologies Inc. Construction of a vacuum cleaner head
EP1173893A4 (en) 1999-01-15 2007-08-01 Univ California Polycrystalline silicon germanium films for forming micro-electromechanical systems
US6180486B1 (en) 1999-02-16 2001-01-30 International Business Machines Corporation Process of fabricating planar and densely patterned silicon-on-insulator structure
US6241821B1 (en) 1999-03-22 2001-06-05 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6248459B1 (en) 1999-03-22 2001-06-19 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
TW460717B (en) 1999-03-30 2001-10-21 Toppan Printing Co Ltd Optical wiring layer, optoelectric wiring substrate mounted substrate, and methods for manufacturing the same
US6143072A (en) 1999-04-06 2000-11-07 Ut-Battelle, Llc Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate
DE10017137A1 (en) 1999-04-14 2000-10-26 Siemens Ag Novel silicon structure, used for solar cells or LCD TFTs, comprises a crystalline textured silicon thin film over a biaxially textured lattice-matched diffusion barrier buffer layer on a thermal expansion-matched inert substrate
JP4631103B2 (en) 1999-05-19 2011-02-23 ソニー株式会社 Semiconductor device and manufacturing method thereof
US6312819B1 (en) 1999-05-26 2001-11-06 The Regents Of The University Of California Oriented conductive oxide electrodes on SiO2/Si and glass
US6372813B1 (en) 1999-06-25 2002-04-16 Motorola Methods and compositions for attachment of biomolecules to solid supports, hydrogels, and hydrogel arrays
JP2000068466A (en) 1999-07-01 2000-03-03 Seiko Epson Corp Semiconductor memory device
US6270568B1 (en) 1999-07-15 2001-08-07 Motorola, Inc. Method for fabricating a semiconductor structure with reduced leakage current density
US6319730B1 (en) 1999-07-15 2001-11-20 Motorola, Inc. Method of fabricating a semiconductor structure including a metal oxide interface
US6107721A (en) 1999-07-27 2000-08-22 Tfr Technologies, Inc. Piezoelectric resonators on a differentially offset reflector
US6238946B1 (en) 1999-08-17 2001-05-29 International Business Machines Corporation Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing
US6275122B1 (en) 1999-08-17 2001-08-14 International Business Machines Corporation Encapsulated MEMS band-pass filter for integrated circuits
US6389209B1 (en) 1999-09-07 2002-05-14 Agere Systems Optoelectronics Guardian Corp. Strain free planar optical waveguides
EP1085319B1 (en) 1999-09-13 2005-06-01 Interuniversitair Micro-Elektronica Centrum Vzw A device for detecting an analyte in a sample based on organic materials
US6306668B1 (en) 1999-09-23 2001-10-23 Ut-Battelle, Llc Control method and system for use when growing thin-films on semiconductor-based materials
US6326637B1 (en) 1999-10-18 2001-12-04 International Business Machines Corporation Antiferromagnetically exchange-coupled structure for magnetic tunnel junction device
US6340788B1 (en) 1999-12-02 2002-01-22 Hughes Electronics Corporation Multijunction photovoltaic cells and panels using a silicon or silicon-germanium active substrate cell for space and terrestrial applications
US6479173B1 (en) 1999-12-17 2002-11-12 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon
US6291319B1 (en) 1999-12-17 2001-09-18 Motorola, Inc. Method for fabricating a semiconductor structure having a stable crystalline interface with silicon
US6268269B1 (en) 1999-12-30 2001-07-31 United Microelectronics Corp. Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects
JP2000351682A (en) 2000-01-01 2000-12-19 Toto Ltd Tile and method of cleansing the same and tile cleanser
US6251738B1 (en) 2000-01-10 2001-06-26 International Business Machines Corporation Process for forming a silicon-germanium base of heterojunction bipolar transistor
US6404027B1 (en) 2000-02-07 2002-06-11 Agere Systems Guardian Corp. High dielectric constant gate oxides for silicon-based devices
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US20010013313A1 (en) 2000-02-10 2001-08-16 Motorola, Inc. Apparatus for fabricating semiconductor structures and method of forming the structures
US6348373B1 (en) 2000-03-29 2002-02-19 Sharp Laboratories Of America, Inc. Method for improving electrical properties of high dielectric constant films
JP2001326337A (en) * 2000-05-16 2001-11-22 Fujitsu Ltd Method for manufacturing dielectric film, method for manufacturing capacitor and method for manufacturing semiconductor device
US6313486B1 (en) 2000-06-15 2001-11-06 Board Of Regents, The University Of Texas System Floating gate transistor having buried strained silicon germanium channel layer
US20020030246A1 (en) 2000-06-28 2002-03-14 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
US20020008234A1 (en) 2000-06-28 2002-01-24 Motorola, Inc. Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
JP2002023123A (en) 2000-07-11 2002-01-23 Fujitsu Ltd Optical circuit provided with optical waveguide for guiding minor light
US6432546B1 (en) 2000-07-24 2002-08-13 Motorola, Inc. Microelectronic piezoelectric structure and method of forming the same
US6224669B1 (en) 2000-09-14 2001-05-01 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
JP4056226B2 (en) 2001-02-23 2008-03-05 株式会社ルネサステクノロジ Semiconductor device
US6788839B2 (en) 2001-03-19 2004-09-07 General Instrument Corporation Time slot tunable all-optical packet data routing switch
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
JP5291299B2 (en) 2007-05-17 2013-09-18 積水化学工業株式会社 Conductive paste
KR20100021342A (en) 2008-08-14 2010-02-24 삼성전자주식회사 System and method for transmitting/receiving call in home network
JP5289070B2 (en) 2009-01-19 2013-09-11 中国電力株式会社 Overcurrent relay device
JP5288354B2 (en) 2009-07-28 2013-09-11 祐子 伊藤 Abdominal wound urine pants with penis bag
RU2528176C2 (en) 2009-12-03 2014-09-10 ЭлДжи ЭЛЕКТРОНИКС ИНК. Method and apparatus for frame transmission in wireless radio access network (ran) system
JP5152529B2 (en) 2009-12-09 2013-02-27 三菱自動車工業株式会社 Internal resistance estimation device

Patent Citations (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617951A (en) * 1968-11-21 1971-11-02 Western Microwave Lab Inc Broadband circulator or isolator of the strip line or microstrip type
US4177094A (en) * 1977-09-16 1979-12-04 U.S. Philips Corporation Method of treating a monocrystalline body utilizing a measuring member consisting of a monocrystalline layer and an adjoining substratum of different index of refraction
US5268327A (en) * 1984-04-27 1993-12-07 Advanced Energy Fund Limited Partnership Epitaxial compositions
US4695120A (en) * 1985-09-26 1987-09-22 The United States Of America As Represented By The Secretary Of The Army Optic-coupled integrated circuits
US5140387A (en) * 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
US4804866A (en) * 1986-03-24 1989-02-14 Matsushita Electric Works, Ltd. Solid state relay
US4866489A (en) * 1986-07-22 1989-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US4801184A (en) * 1987-06-15 1989-01-31 Eastman Kodak Company Integrated optical read/write head and apparatus incorporating same
US5959308A (en) * 1988-07-25 1999-09-28 Texas Instruments Incorporated Epitaxial layer on a heterointerface
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5028563A (en) * 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US5510665A (en) * 1989-03-03 1996-04-23 E. F. Johnson Company Optoelectronic active circuit element
US5057694A (en) * 1989-03-15 1991-10-15 Matsushita Electric Works, Ltd. Optoelectronic relay circuit having charging path formed by a switching transistor and a rectifying diode
US5362972A (en) * 1990-04-20 1994-11-08 Hitachi, Ltd. Semiconductor device using whiskers
US5585288A (en) * 1990-07-16 1996-12-17 Raytheon Company Digital MMIC/analog MMIC structures and process
US5574296A (en) * 1990-08-24 1996-11-12 Minnesota Mining And Manufacturing Company Doping of IIB-VIA semiconductors during molecular beam epitaxy electromagnetic radiation transducer having p-type ZnSe layer
US5216359A (en) * 1991-01-18 1993-06-01 University Of North Carolina Electro-optical method and apparatus for testing integrated circuits
US5570226A (en) * 1991-04-26 1996-10-29 Fuji Xerox Co., Ltd. Optical link amplifier and a wavelength multiplex laser oscillator
US5148504A (en) * 1991-10-16 1992-09-15 At&T Bell Laboratories Optical integrated circuit designed to operate by use of photons
US5666376A (en) * 1991-11-08 1997-09-09 University Of New Mexico Electro-optical device
US5446719A (en) * 1992-02-05 1995-08-29 Sharp Kabushiki Kaisha Optical information reproducing apparatus
US5585167A (en) * 1992-05-18 1996-12-17 Matsushita Electric Industrial Co., Ltd. Thin-film conductor and method of fabricating the same
US5262659A (en) * 1992-08-12 1993-11-16 United Technologies Corporation Nyquist frequency bandwidth hact memory
US5410622A (en) * 1992-08-21 1995-04-25 Sharp Kabushiki Kaisha Optical integrated circuit having light detector
US5578162A (en) * 1993-06-25 1996-11-26 Lucent Technologies Inc. Integrated composite semiconductor devices and method for manufacture thereof
US5684302A (en) * 1993-07-15 1997-11-04 Siemens Aktiengesellschaft Pyrodetector element having a pyroelectric layer produced by oriented growth, and method for the fabrication of the element
US5693140A (en) * 1993-07-30 1997-12-02 Lockheed Martin Energy Systems, Inc. Process for growing a film epitaxially upon a MgO surface
US5371621A (en) * 1993-08-23 1994-12-06 Unisys Corporation Self-routing multi-stage photonic interconnect
US5679947A (en) * 1993-08-25 1997-10-21 Sony Corporation Optical device having a light emitter and a photosensor on the same optical axis
US5508554A (en) * 1993-08-26 1996-04-16 Hitachi, Ltd. Semicoductor device having defect type compound layer between single crystal substrate and single crystal growth layer
US5976953A (en) * 1993-09-30 1999-11-02 Kopin Corporation Three dimensional processor using transferred thin film circuits
US5674813A (en) * 1993-11-04 1997-10-07 Sumitomo Electric Industries, Ltd. Process for preparing layered structure including oxide super conductor thin film
US5477363A (en) * 1994-03-16 1995-12-19 Fujitsu Limited Optical switching device
US5878175A (en) * 1994-04-15 1999-03-02 Fuji Photo Film Co., Ltd. Electro-optical waveguide element with reduced DC drift phenomena
US6064783A (en) * 1994-05-25 2000-05-16 Congdon; Philip A. Integrated laser and coupled waveguide
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
US5635453A (en) * 1994-12-23 1997-06-03 Neocera, Inc. Superconducting thin film system using a garnet substrate
US5772758A (en) * 1994-12-29 1998-06-30 California Institute Of Technology Near real-time extraction of deposition and pre-deposition characteristics from rotating substrates and control of a deposition apparatus in near real-time
US5574589A (en) * 1995-01-09 1996-11-12 Lucent Technologies Inc. Self-amplified networks
US5864171A (en) * 1995-03-30 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor optoelectric device and method of manufacturing the same
US5528209A (en) * 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
US5905571A (en) * 1995-08-30 1999-05-18 Sandia Corporation Optical apparatus for forming correlation spectrometers and optical processors
US6198119B1 (en) * 1996-03-13 2001-03-06 Hitachi, Ltd. Ferroelectric element and method of producing the same
US5998819A (en) * 1996-03-19 1999-12-07 Sharp Kabushiki Kaisha Thin ferroelectric film element having a multi-layered thin ferroelectric film and method for manufacturing the same
US5882948A (en) * 1996-06-07 1999-03-16 Picolight, Inc. Method for fabricating a semiconductor device
US6049110A (en) * 1996-06-26 2000-04-11 Nec Corporation Body driven SOI-MOS field effect transistor
US6080378A (en) * 1996-09-05 2000-06-27 Kabushiki Kaisha Kobe Seiko Sho Diamond films and methods for manufacturing diamond films
US5838053A (en) * 1996-09-19 1998-11-17 Raytheon Ti Systems, Inc. Method of forming a cadmium telluride/silicon structure
US5719417A (en) * 1996-11-27 1998-02-17 Advanced Technology Materials, Inc. Ferroelectric integrated circuit structure
US6113225A (en) * 1997-01-24 2000-09-05 Seiko Epson Corporation Ink jet type recording head
US5937115A (en) * 1997-02-12 1999-08-10 Foster-Miller, Inc. Switchable optical components/structures and methods for the fabrication thereof
US6110813A (en) * 1997-04-04 2000-08-29 Matsushita Electric Industrial Co., Ltd. Method for forming an ohmic electrode
US5998781A (en) * 1997-04-30 1999-12-07 Sandia Corporation Apparatus for millimeter-wave signal generation
US5831960A (en) * 1997-07-17 1998-11-03 Motorola, Inc. Integrated vertical cavity surface emitting laser pair for high density data storage and method of fabrication
US6307996B1 (en) * 1997-11-06 2001-10-23 Fuji Xerox Co. Ltd. Optical waveguide device and manufacturing method thereof
US5987196A (en) * 1997-11-06 1999-11-16 Micron Technology, Inc. Semiconductor structure having an optical signal path in a substrate and method for forming the same
US6376337B1 (en) * 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
US6239012B1 (en) * 1998-01-27 2001-05-29 Micron Technology, Inc. Vertically mountable semiconductor device and methods
US6504189B1 (en) * 1998-07-21 2003-01-07 Fujitsu Quantum Devices Limited Semiconductor device having a microstrip line
US6392253B1 (en) * 1998-08-10 2002-05-21 Arjun J. Saxena Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
US6452232B1 (en) * 1998-12-03 2002-09-17 Sharp Kabushiki Kaisha Semiconductor device having SOI structure and manufacturing method thereof
US6496469B1 (en) * 1999-09-27 2002-12-17 Kabushiki Kaisha Toshiba Integrated unit, optical pickup, and optical recording medium drive device
US20010036142A1 (en) * 2000-03-03 2001-11-01 Kadowaki Shin-Ichi Optical pick-up head and information recording/reproducing apparatus
US20010020278A1 (en) * 2000-03-06 2001-09-06 Tatsuya Saito Phase-controlled source synchronous interface circuit
US6477285B1 (en) * 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US20020079576A1 (en) * 2000-06-30 2002-06-27 Krishna Seshan Ball limiting metallurgy for input/outputs and methods of fabrication
US20020145168A1 (en) * 2001-02-05 2002-10-10 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US6297598B1 (en) * 2001-02-20 2001-10-02 Harvatek Corp. Single-side mounted light emitting diode module
US20020195610A1 (en) * 2001-06-20 2002-12-26 Motorola, Inc. Structure and method for fabricating a semiconductor device with a side interconnect

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040031990A1 (en) * 2002-08-16 2004-02-19 Been-Yih Jin Semiconductor on insulator apparatus and method
US7427538B2 (en) * 2002-08-16 2008-09-23 Intel Corporation Semiconductor on insulator apparatus and method
US20080303116A1 (en) * 2002-08-16 2008-12-11 Been-Yih Jin Semiconductor on insulator apparatus
US20100038717A1 (en) * 2002-08-16 2010-02-18 Been-Yih Jin Semiconductor on Insulator Apparatus
US7671414B2 (en) 2002-08-16 2010-03-02 Intel Corporation Semiconductor on insulator apparatus
US7875932B2 (en) 2002-08-16 2011-01-25 Intel Corporation Semiconductor on insulator apparatus
US20110039377A1 (en) * 2002-08-16 2011-02-17 Been-Yih Jin Semiconductor on Insulator
US8173495B2 (en) 2002-08-16 2012-05-08 Intel Corporation Semiconductor on insulator

Also Published As

Publication number Publication date
US6673667B2 (en) 2004-01-06

Similar Documents

Publication Publication Date Title
US20170025564A1 (en) Nitride semiconductor component and process for its production
EP1595280B8 (en) Buffer structure for heteroepitaxy on a silicon substrate
US6818061B2 (en) Method for growing single crystal GaN on silicon
KR100503693B1 (en) Method of growing gallium nitride on a spinel substrate
US5863811A (en) Method for growing single crystal III-V compound semiconductor layers on non single crystal III-V Compound semiconductor buffer layers
US20130062612A1 (en) Nitride semiconductor device, nitride semiconductor wafer, and method for manufacturing nitride semiconductor layer
KR20140043460A (en) Nitride semiconductor structure and method of fabricating same
JP2018535536A (en) System and method for graphene-based layer transfer
US7632741B2 (en) Method for forming AlGaN crystal layer
US8803189B2 (en) III-V compound semiconductor epitaxy using lateral overgrowth
US20180151359A1 (en) Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers
Saint-Girons et al. Monolithic integration of InP based heterostructures on silicon using crystalline Gd 2 O 3 buffers
US8058705B2 (en) Composite material substrate
US20010006852A1 (en) Method for relieving lattice mismatch stress in semiconductor devices
US8674405B1 (en) Gallium—nitride-on-diamond wafers and devices, and methods of manufacture
KR20030007896A (en) Preparation method of a coating of gallium nitride
US7078318B2 (en) Method for depositing III-V semiconductor layers on a non-III-V substrate
US20040151463A1 (en) Optical waveguide structure and method for fabricating the same
CN102634849A (en) Method for growth of gan single crystal, method for preparation of gan substrate, process for producing gan-based element, and gan-based element
TW508834B (en) Integrated circuits with optical signal propagation
US20010006249A1 (en) Co-planar si and ge composite substrate and method of producing same
WO1989004594A1 (en) Omcvd of iii-v material on silicon
EP1875523A1 (en) Nitride semiconductor component and method for the production thereof
EP2333817B1 (en) Method for preparing compound semiconductor substrate
WO2002047127A2 (en) Pyroelectric device on a monocrystalline semiconductor substrate

Legal Events

Date Code Title Description
AS Assignment

Owner name: MOTOROLA, INC., ILLINOIS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GORRELL, JONATHAN F.;CORNETT, KENNETH D.;REEL/FRAME:012659/0757

Effective date: 20010817

AS Assignment

Owner name: MOTOROLA, INC., ILLINOIS

Free format text: INVALID RECORDING;ASSIGNORS:GORRELL, JONATHAN F.;CORNETT, KENNETH D.;REEL/FRAME:012457/0362

Effective date: 20010817

AS Assignment

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657

Effective date: 20040404

Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657

Effective date: 20040404

AS Assignment

Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129

Effective date: 20061201

Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129

Effective date: 20061201

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001

Effective date: 20100413

Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001

Effective date: 20100413

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424

Effective date: 20130521

AS Assignment

Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266

Effective date: 20131101

REMI Maintenance fee reminder mailed
AS Assignment

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225

Effective date: 20151207

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553

Effective date: 20151207

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143

Effective date: 20151207

LAPS Lapse for failure to pay maintenance fees
AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517

Effective date: 20151207

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292

Effective date: 20151207

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20160106

AS Assignment

Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001

Effective date: 20160912

Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001

Effective date: 20160912

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001

Effective date: 20160622

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536

Effective date: 20151207

AS Assignment

Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001

Effective date: 20190217