US20030006451A1 - Structure of flash memory - Google Patents
Structure of flash memory Download PDFInfo
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- US20030006451A1 US20030006451A1 US10/128,416 US12841602A US2003006451A1 US 20030006451 A1 US20030006451 A1 US 20030006451A1 US 12841602 A US12841602 A US 12841602A US 2003006451 A1 US2003006451 A1 US 2003006451A1
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- 230000015654 memory Effects 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 27
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000006243 chemical reaction Methods 0.000 claims abstract description 15
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- 230000007547 defect Effects 0.000 abstract description 8
- 239000000376 reactant Substances 0.000 abstract description 8
- 230000005527 interface trap Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007087 memory ability Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 150000003961 organosilicon compounds Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002912 waste gas Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Definitions
- the present invention relates to a structure of a flash memory having interpoly dielectric layer for improving reliability of flash memory devices. More particularly, it is related to a structure of a flash memory manufactured by using a process of semi-atmospheric pressure chemical vapor deposition (SAPCVD) and tetra-ethyl-ortho-silicate (TEOS) reactants.
- SAPCVD semi-atmospheric pressure chemical vapor deposition
- TEOS tetra-ethyl-ortho-silicate
- Flash memory is a semi-conductor technique developed according to RAM product of computer. Flash memory is a solid-state storage system, which consumes less-power to change inner data quickly by using the efficient block way, and flash memory retains data without any additional power.
- Flash memory and other solid-state memories for example, read only memory (ROM), static/dynamic random access memory (SRAM/DRAM), and electrically erasable programmable read only memory (EEPROM) are applied widely.
- ROM read only memory
- SRAM/DRAM static/dynamic random access memory
- EEPROM electrically erasable programmable read only memory
- the flash memory is the best storage system with high quality since the flash memory has characteristics of non-volatile, rewritable, high density and stability.
- FIG. 1 is a cross-section view of a conventional flash memory device.
- the structure of the conventional flash memory device includes a substrate 10 , and a source region 12 , a drain region 14 , and a channel region 16 located in the substrate 10 , and a stacked gate structure 18 located on the substrate 10 .
- the stacked gate structure 18 further includes a tunnel oxide layer 20 , a floating gate 22 , an interpoly dielectric layer 24 , and a control gate 26 .
- the floating gate 22 and the control gate 26 are usually composed of polysilicon, and the interpoly dielectric layer 24 is composed of multi-insulated layers, i.e. oxide/nitride/oxide (ONO) structure.
- the interpoly dielectric layer 24 includes a bottom oxide layer 28 , a nitride layer 30 , and a top oxide layer 32 .
- the interpoly dielectric layer 24 has to be high reliability. For example, if the top oxide layer 32 is too thick, the needful conductive voltage may be increased. Otherwise, if the top oxide layer 32 is too thin, in the flash memory the current leaks out easily so that the memory ability and storage time of charges also decreased. Accordingly, it is important to control the thickness of the top oxide layer. In addition, if the nitride layer 30 is too thin, current leakage may be happened between floating gate 22 and control gate 26 , and charge storage time is also shortened.
- the conventional method of manufacturing the interpoly dielectric layer 24 ONO structure of flash memory device is to oxidize the nitride layer 30 directly by wet thermal oxidation. For example, under 950° C. vapor circumstance the process of oxidizing the nitride layer about 40 minutes to transform a portion of the nitride layer into the top oxide layer 32 .
- the other conventional method of manufacturing the interpoly dielectric layer 24 , ONO structure of flash memory device is to form an oxide layer on the nitride layer, for example, by low-pressure vapor deposition (LPCVD).
- LPCVD low-pressure vapor deposition
- the LPCVD process is performed under the circumstance, includes: lower temperature between about 600° C. and about 850° C. and higher pressure between about 400 mTorr and about 750 mTorr; injecting reactive gases (as SiH 4 and N 2 O) and inert gas or N 2 to form SiO 2 layer; and performing a rapid thermal anneal (RTA) process to nitrify the oxide layer for about 40 seconds to 80 seconds under a temperature between about 700° C. and 950° C.
- RTA rapid thermal anneal
- the conventional method of LPCVD process is more complex and consumes more gases by repeating decompression and gas exhausting to maintain low-pressure circumstance.
- Molecules in low-pressure move in the form of molecular flow, so that the collision frequency between molecules is very low and it is therefore very hard to produce the collisions needed to induce CVD process.
- the deposition rate of film is slow and takes long time.
- the turbulent flow also induces dust in reaction chamber so that the deposition quality is influenced.
- the SiH 4 reactant is reacted by homogeneous nucleation so that the step coverage ability of this conventional process is poor because of the surface pollution of the reactor by dust.
- one aspect of the present invention is to provide a semi-atmospheric pressure chemical vapor deposition process to improve the disadvantages of long thermal budget and uncontrolled thickness, which are caused from conventional wet thermal oxidation under high temperature.
- the present invention also improves the problems caused by repeating decompression, low collision frequency and turbulent flow.
- TEOS tetra-ethyl-ortho-silicate
- the present invention provides a structure of a flash memory manufactured by the method combining SAPCVD process and TEOS reactants to decrease defect and interface trap, wherein SAPCVD includes the step of reacting TEOS reactants with oxygen under temperature between about 600° C. and 750° C. and pressure between about 340 Torr and 550 Torr.
- a structure of a flash memory comprises: a tunnel oxide layer located on a substrate; a floating gate located on the tunnel oxide layer; and an interpoly dielectric layer located on the floating gate, wherein the interpoly dielectric layer comprises an oxide layer, a nitride layer and a semi-atmospheric pressure chemical vapor deposition (SAPCVD) oxide layer, wherein the SAPCVD oxide layer is formed by a semi-atmospheric pressure chemical vapor deposition process.
- SAPCVD semi-atmospheric pressure chemical vapor deposition
- FIG. 1 is a cross-section view of a conventional flash memory device
- FIG. 2 is a cross-section view of a flash memory device according to the present invention.
- the present invention discloses a top oxide layer with a few defects and interface traps to improve reliability of interpoly dielectric layer of a flash memory device.
- the present invention produces the oxide/nitride/oxide (ONO) structure of flash memory devices by using semi-atmospheric pressure CVD (SAPCVD) process and tetra-ethyl-ortho-silicate (TEOS) reactants to decrease defect and interface trap and to increase reliability of the tunnel oxide layer.
- SAPCVD semi-atmospheric pressure CVD
- TEOS tetra-ethyl-ortho-silicate
- FIG. 2 is a cross-section view of a flash memory device according to the present invention.
- the flash memory device of the present invention includes a substrate 100 and a source region 120 , a drain region 140 and a channel region 160 located in the substrate 100 , and a stacked gate structure 180 located on the substrate 100 .
- the stacked gate structure 180 further includes a tunnel oxide layer 200 , a floating gate 220 , an interpoly dielectric layer 240 , and a control gate 260 .
- the floating gate 220 and the control gate 260 are, composed of polysilicon
- the interpoly dielectric layer 240 is composed of multi-insulated layers, namely, oxide/nitride/oxide (ONO) structure.
- the interpoly dielectric layer 240 (ONO structure) is a stacked structure composed of a bottom oxide layer 280 , a nitride layer 300 , and a top oxide layer 320 .
- One characteristic of the present invention is the use of SAPCVD process to form the top oxide layer 320 .
- the reaction temperature of SAPCVD process of the present invention is, for example, between about 600° C. and about 750° C., and the preferred reaction temperature is about 680° C.
- the reaction pressure is, for example, between about 340 Torr and about 550 Torr, and the preferred pressure is about 400 Torr.
- reactive gases for example, TEOS and oxygen, are introduced, and following reaction (1) is also performed to form the top oxide layer 320 , wherein the deposition thickness of the top oxide layer 320 is between about 20 ⁇ and about 80 ⁇ , and the preferred deposition thickness is about 40 ⁇ .
- the reaction temperature of the present invention is lower than the reaction temperature (950° C.) of the conventional method to avoid decomposition of interpoly dielectric layer under high temperature.
- Another advantage of the present invention is that before reaction, the pressure of the chamber is decompressed to 500 mTorr instead of 5 mTorr disclosed by conventional LPCVD method. Moreover, gases are transported into the chamber in a continuous way to achieve vapor deposition and the waste gases are exhausted through exhausting system. Therefore, it is not necessary to vacuum the chamber to perform the next stage of the process, and the time and gas consumption problems are also dissolved.
- the pressure of the present invention is semi-atmospheric pressure.
- the collision frequency of molecule is enhanced and the reaction time is shortened compared with the low-pressure circumstance of LPCVD.
- the way of delivering the gas continuity is used to lower the turbulent flow do the phenomenon of reactant to be particle decreases. Therefore there are the preferred uniformity and quality in the top oxide layer of the deposition and lowering the thermal budget.
- the present invention can improve the thermal budget and decrease charge trap to get the tunnel oxide layer with high reliability.
- the present invention is easier than the conventional step of oxidization to control the thickness of interpoly dielectric layer to avoid the defect caused by the too thin or too thick thickness of oxide layer in the interpoly dielectric layer and the current leakage problem caused by the defect is avoided also. Otherwise, the present invention can shorten reaction time and resolve dust problem so that an interpoly dielectric layer with high deposition quality is formed.
Abstract
A structure of a flash memory having a tunnel oxide layer with high reliability, low defect and interface trap, manufactured by using a process of semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant, wherein the SAPCVD process is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.
Description
- The present invention relates to a structure of a flash memory having interpoly dielectric layer for improving reliability of flash memory devices. More particularly, it is related to a structure of a flash memory manufactured by using a process of semi-atmospheric pressure chemical vapor deposition (SAPCVD) and tetra-ethyl-ortho-silicate (TEOS) reactants.
- Flash memory is a semi-conductor technique developed according to RAM product of computer. Flash memory is a solid-state storage system, which consumes less-power to change inner data quickly by using the efficient block way, and flash memory retains data without any additional power.
- Flash memory and other solid-state memories, for example, read only memory (ROM), static/dynamic random access memory (SRAM/DRAM), and electrically erasable programmable read only memory (EEPROM) are applied widely.
- Among these solid-state memories, the flash memory is the best storage system with high quality since the flash memory has characteristics of non-volatile, rewritable, high density and stability.
- FIG. 1 is a cross-section view of a conventional flash memory device. The structure of the conventional flash memory device includes a
substrate 10, and asource region 12, adrain region 14, and achannel region 16 located in thesubstrate 10, and a stackedgate structure 18 located on thesubstrate 10. Herein the stackedgate structure 18 further includes atunnel oxide layer 20, afloating gate 22, an interpolydielectric layer 24, and acontrol gate 26. Thefloating gate 22 and thecontrol gate 26 are usually composed of polysilicon, and the interpolydielectric layer 24 is composed of multi-insulated layers, i.e. oxide/nitride/oxide (ONO) structure. The interpolydielectric layer 24 includes abottom oxide layer 28, anitride layer 30, and atop oxide layer 32. When current flows through thechannel region 16 of the flash memory device to electrically connect thesource region 12 and thedrain region 14, meanwhile electric field is applied to the stackedgate structure 18. - To be the insulation structure between the
floating gate 22 and thecontrol gate 26, the interpolydielectric layer 24 has to be high reliability. For example, if thetop oxide layer 32 is too thick, the needful conductive voltage may be increased. Otherwise, if thetop oxide layer 32 is too thin, in the flash memory the current leaks out easily so that the memory ability and storage time of charges also decreased. Accordingly, it is important to control the thickness of the top oxide layer. In addition, if thenitride layer 30 is too thin, current leakage may be happened between floatinggate 22 andcontrol gate 26, and charge storage time is also shortened. - The conventional method of manufacturing the interpoly
dielectric layer 24 ONO structure of flash memory device is to oxidize thenitride layer 30 directly by wet thermal oxidation. For example, under 950° C. vapor circumstance the process of oxidizing the nitride layer about 40 minutes to transform a portion of the nitride layer into thetop oxide layer 32. - The other conventional method of manufacturing the interpoly
dielectric layer 24, ONO structure of flash memory device is to form an oxide layer on the nitride layer, for example, by low-pressure vapor deposition (LPCVD). The LPCVD process is performed under the circumstance, includes: lower temperature between about 600° C. and about 850° C. and higher pressure between about 400 mTorr and about 750 mTorr; injecting reactive gases (as SiH4 and N2O) and inert gas or N2 to form SiO2 layer; and performing a rapid thermal anneal (RTA) process to nitrify the oxide layer for about 40 seconds to 80 seconds under a temperature between about 700° C. and 950° C. in order to densify the oxide layer or reduce defects and charge trap formed on the top oxide layer of flash memory devices. Since the increased temperature decomposes N2O to N2 and reactive oxygen molecules, the oxygen molecules will diffuse to oxygen lattice's vacancies of LPCVD oxide layer resulting to density decreasing and current leakage. - In the above interpretation, the conventional method of wet thermal oxidation tends to react excess nitride, so that the nitride layer may be too thin resulting charge leakage. In the other hand, long reactive time and high reaction temperature also introduce defects and charge traps and decrease the reliability of tunnel oxide layer.
- In the above interpretation, the conventional method of LPCVD process is more complex and consumes more gases by repeating decompression and gas exhausting to maintain low-pressure circumstance. Molecules in low-pressure move in the form of molecular flow, so that the collision frequency between molecules is very low and it is therefore very hard to produce the collisions needed to induce CVD process. Hence, the deposition rate of film is slow and takes long time. Moreover the turbulent flow also induces dust in reaction chamber so that the deposition quality is influenced. Furthermore, the SiH 4 reactant is reacted by homogeneous nucleation so that the step coverage ability of this conventional process is poor because of the surface pollution of the reactor by dust.
- Therefore, one aspect of the present invention is to provide a semi-atmospheric pressure chemical vapor deposition process to improve the disadvantages of long thermal budget and uncontrolled thickness, which are caused from conventional wet thermal oxidation under high temperature. The present invention also improves the problems caused by repeating decompression, low collision frequency and turbulent flow.
- Other aspect of the present invention is that using tetra-ethyl-ortho-silicate (TEOS) reactants to form the oxide layer to improve the disadvantage of dusted pollution caused from SiH 4.
- According to the above aspects, the present invention provides a structure of a flash memory manufactured by the method combining SAPCVD process and TEOS reactants to decrease defect and interface trap, wherein SAPCVD includes the step of reacting TEOS reactants with oxygen under temperature between about 600° C. and 750° C. and pressure between about 340 Torr and 550 Torr. A structure of a flash memory comprises: a tunnel oxide layer located on a substrate; a floating gate located on the tunnel oxide layer; and an interpoly dielectric layer located on the floating gate, wherein the interpoly dielectric layer comprises an oxide layer, a nitride layer and a semi-atmospheric pressure chemical vapor deposition (SAPCVD) oxide layer, wherein the SAPCVD oxide layer is formed by a semi-atmospheric pressure chemical vapor deposition process.
- The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
- FIG. 1 is a cross-section view of a conventional flash memory device; and
- FIG. 2 is a cross-section view of a flash memory device according to the present invention.
- The present invention discloses a top oxide layer with a few defects and interface traps to improve reliability of interpoly dielectric layer of a flash memory device. The present invention produces the oxide/nitride/oxide (ONO) structure of flash memory devices by using semi-atmospheric pressure CVD (SAPCVD) process and tetra-ethyl-ortho-silicate (TEOS) reactants to decrease defect and interface trap and to increase reliability of the tunnel oxide layer.
- FIG. 2 is a cross-section view of a flash memory device according to the present invention. The flash memory device of the present invention includes a
substrate 100 and asource region 120, adrain region 140 and achannel region 160 located in thesubstrate 100, and a stackedgate structure 180 located on thesubstrate 100. The stackedgate structure 180 further includes atunnel oxide layer 200, afloating gate 220, an interpolydielectric layer 240, and acontrol gate 260. For example, thefloating gate 220 and thecontrol gate 260 are, composed of polysilicon, and the interpolydielectric layer 240 is composed of multi-insulated layers, namely, oxide/nitride/oxide (ONO) structure. The interpoly dielectric layer 240 (ONO structure) is a stacked structure composed of abottom oxide layer 280, anitride layer 300, and atop oxide layer 320. - One characteristic of the present invention is the use of SAPCVD process to form the
top oxide layer 320. - The reaction temperature of SAPCVD process of the present invention is, for example, between about 600° C. and about 750° C., and the preferred reaction temperature is about 680° C. The reaction pressure is, for example, between about 340 Torr and about 550 Torr, and the preferred pressure is about 400 Torr. Under such process circumstance, reactive gases, for example, TEOS and oxygen, are introduced, and following reaction (1) is also performed to form the
top oxide layer 320, wherein the deposition thickness of thetop oxide layer 320 is between about 20 Å and about 80Å, and the preferred deposition thickness is about 40 Å. - Si(OC2H5)4→SiO2+by-product (1)
- (Wherein the by-product is a complex mixture of organic and organosilicon compounds)
- According to the above process, the reaction temperature of the present invention is lower than the reaction temperature (950° C.) of the conventional method to avoid decomposition of interpoly dielectric layer under high temperature. Another advantage of the present invention is that before reaction, the pressure of the chamber is decompressed to 500 mTorr instead of 5 mTorr disclosed by conventional LPCVD method. Moreover, gases are transported into the chamber in a continuous way to achieve vapor deposition and the waste gases are exhausted through exhausting system. Therefore, it is not necessary to vacuum the chamber to perform the next stage of the process, and the time and gas consumption problems are also dissolved.
- Furthermore, the pressure of the present invention is semi-atmospheric pressure. The collision frequency of molecule is enhanced and the reaction time is shortened compared with the low-pressure circumstance of LPCVD. Moreover, in the present invention, the way of delivering the gas continuity is used to lower the turbulent flow do the phenomenon of reactant to be particle decreases. Therefore there are the preferred uniformity and quality in the top oxide layer of the deposition and lowering the thermal budget.
- According to the above advantages, the present invention can improve the thermal budget and decrease charge trap to get the tunnel oxide layer with high reliability. The present invention is easier than the conventional step of oxidization to control the thickness of interpoly dielectric layer to avoid the defect caused by the too thin or too thick thickness of oxide layer in the interpoly dielectric layer and the current leakage problem caused by the defect is avoided also. Otherwise, the present invention can shorten reaction time and resolve dust problem so that an interpoly dielectric layer with high deposition quality is formed.
- As is understood by a person skilled in the art, the foregoing preferred embodiments are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
Claims (9)
1. A structure of a flash memory, which can improve the reliability of the flash memory, the structure of a flash memory comprises:
a tunnel oxide layer located on a substrate;
a floating gate located on the tunnel oxide layer; and
an interpoly dielectric layer located on the floating gate, wherein the interpoly dielectric layer comprises an oxide layer, a nitride layer and a semi-atmospheric pressure chemical vapor deposition (SAPCVD) oxide layer, wherein the SAPCVD oxide layer is formed by a semi-atmospheric pressure chemical vapor deposition process.
2. The structure according to claim 1 , wherein the oxide layer, the nitride layer and the SAPCVD oxide layer in a stacked structure from bottom to top are located on the floating gate.
3. The structure according to claim 1 , wherein a reaction temperature of the semi-atmospheric pressure chemical vapor deposition process is between about 600° C. and 750° C.
4. The structure according to claim 1 , wherein a reaction temperature of the semi-atmospheric pressure chemical vapor deposition process is about 680° C.
5. The structure according to claim 1 , wherein a reaction pressure of the semi-atmospheric pressure chemical vapor deposition process is between about 340 Torr and 550 Torr.
6. The structure according to claim 1 , wherein a reaction pressure of the semi-atmospheric pressure chemical vapor deposition process is about 400 Torr.
7. The structure according to claim 1 , wherein the semi-atmospheric pressure chemical vapor deposition process further comprises the use of tetra-ethyl-ortho-silicate (TEOS) and oxygen.
8. The structure according to claim 1 , wherein a thickness of the SAPCVD oxide layer is between about 20 Å and 80 Å.
9. The structure according to claim 1 , wherein a thickness of the SAPCVD oxide layer is about 40 Å.
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| US10/128,416 US20030006451A1 (en) | 2001-03-22 | 2002-04-24 | Structure of flash memory |
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| US09/814,408 US6589835B2 (en) | 2001-03-22 | 2001-03-22 | Method of manufacturing flash memory |
| US10/128,416 US20030006451A1 (en) | 2001-03-22 | 2002-04-24 | Structure of flash memory |
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| US6228713B1 (en) * | 1999-06-28 | 2001-05-08 | Chartered Semiconductor Manufacturing Ltd. | Self-aligned floating gate for memory application using shallow trench isolation |
| US6291331B1 (en) * | 1999-10-04 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue |
| US6426285B1 (en) * | 1999-11-03 | 2002-07-30 | Taiwan Semiconductor Manufacturing Company | Method to solve intermetallic dielectric cracks in integrated circuit devices |
| EP1130130A1 (en) * | 2000-02-29 | 2001-09-05 | STMicroelectronics S.r.l. | Method and reactor for SACVD deposition |
-
2001
- 2001-03-22 US US09/814,408 patent/US6589835B2/en not_active Expired - Lifetime
-
2002
- 2002-04-24 US US10/128,416 patent/US20030006451A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070202708A1 (en) * | 2006-02-28 | 2007-08-30 | Luo Tien Y | Method for forming a deposited oxide layer |
| US7767588B2 (en) * | 2006-02-28 | 2010-08-03 | Freescale Semiconductor, Inc. | Method for forming a deposited oxide layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US6589835B2 (en) | 2003-07-08 |
| US20020137289A1 (en) | 2002-09-26 |
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