US20020177315A1 - Method for manufacturing semiconductor device capable of expelling argon gas - Google Patents

Method for manufacturing semiconductor device capable of expelling argon gas Download PDF

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Publication number
US20020177315A1
US20020177315A1 US10/187,968 US18796802A US2002177315A1 US 20020177315 A1 US20020177315 A1 US 20020177315A1 US 18796802 A US18796802 A US 18796802A US 2002177315 A1 US2002177315 A1 US 2002177315A1
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conductive layer
chamber
semiconductor device
plasma etching
heating
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US10/187,968
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Masayuki Yoshida
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NEC Electronics Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device by a plasma etching process using argon (Ar) ions.
  • a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer. This will be explained later in detail.
  • JP-A-4-10621 discloses a radio-frequency (RF) plasma etching process using halogen fluoride diluted by Ar gas for silicon nitride
  • JP-A-11-243082 discloses an RF plasma etching process using a mixture of fluorine gas and Ar gas for silicon oxide.
  • RF radio-frequency
  • a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Then, a heating process at a temperature higher than about 650° C. is performed upon the first conductive layer to expel Ar atoms from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer.
  • FIGS. 1A through 1C are cross-sectional views for explaining a prior art method for manufacturing a semiconductor device
  • FIG. 2 is a cross-sectional view for explaining a problem created in the method as illustrated in FIGS. 1A through 1C;
  • FIGS. 3A through 3D are cross-sectional views for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention.
  • FIG. 4 is a graph for showing the expelling characteristics of argon atoms in FIG. 3C.
  • FIG. 5 is a diagram illustrating an apparatus for carrying out the method as illustrated in FIGS. 3A, 3B, 3 C and 3 D.
  • FIGS. 1A through 1C Before the description of the preferred embodiment, a prior art method for manufacturing a semiconductor device will be explained with reference to FIGS. 1A through 1C.
  • a silicon oxide layer 2 is formed on a silicon substrate 1 where active regions are already formed. Then, the silicon oxide layer 2 is perforated by a photolithography and etching process. Then, a conductive layer 3 made of aluminum or refractory metal such as WSi is deposited by a sputtering process or the like. Then, a boron-included phosphor-silicated silicon glass (BPSG) layer 4 and a silicon nitride layer 5 are sequentially deposited by a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • the silicon nitride layer 5 and the BPSG layer 4 are perforated by a photolithography and etching process, so that a throughhole TH is formed therein.
  • a very thin natural oxide layer 6 is formed on the conductive layer 3 .
  • a conductive layer 6 made of aluminum or refractory metal such as WSi is deposited on the silicon nitride layer 5 and the throughhole TH by a sputtering process or the like, so that the conductive layer 6 is in contact with the conductive layer 3 at the throughhole TH.
  • FIGS. 3A through 3D An embodiment of the method for manufacturing a semiconductor device according to the present invention will be explained next with reference to FIGS. 3A through 3D.
  • a silicon oxide layer 2 is formed on a silicon substrate 1 where active regions are already formed. Then, the silicon oxide layer 2 is perforated by a photolithography and etching process. Then, a conductive layer 3 made of aluminum or refractory metal such as WSi is deposited by a sputtering process or the like. Then, a BPSG layer 4 and a silicon nitride layer 5 are sequentially deposited by a CVD process. Then, the silicon nitride layer 5 and the BPSG layer 4 are perforated by a photolithography and etching process, so that a throughhole TH is formed therein. In this case, since the conductive layer 3 is oxidized, a very thin natural oxide layer 6 is formed on the conductive layer 3 .
  • a conductive layer 6 made of aluminum or refractory metal such as WSi is deposited on the silicon nitride layer 5 and the throughhole TH by a sputtering process on the like, so that the conductive layer 6 is in contact with the conductive layer 3 at the throughhole TH.
  • the Heating temperature in FIG. 3C is preferably higher than about 650° C.
  • reference numeral 51 designates a vacuum unit where an RF plasma etching chamber 52 , a cooling camber 53 and a separation chamber 54 are provided.
  • a plate 541 for mounting a wafer W, expansible arms 542 for supporting the plate 541 , and a pivot pedestal 543 for pivotally supporting the arms 542 are provided in the separation chamber 54 .
  • sputtering chambers 55 - 1 and 55 - 2 heating chambers 56 - 1 and 56 - 2 and loading chambers 57 - 1 and 57 - 2 are connected to the vacuum unit 51 .
  • the heating chambers 56 includes a lamp annealer.
  • control circuit 58 which may consist of a microcomputer.
  • a package including wafers W, in which layers 2 , 3 , 4 and 5 are already formed on a silicon substrate 1 is set in the loading chamber 57 - 1 , and one of the wafers W is moved by the plate 541 and the arms 542 from the loading chamber 57 - 1 to the RF plasma etching chamber 52 .
  • an RF plasma etching process using Ar ions is carried out to remove a natural oxide layer 6 from the conductive layer 3 .
  • one of the wafers W is moved by the plate 541 and the arms 542 from the RF plasma etching chamber 52 to the heating chamber 56 - 1 . Then, a heating process using the lamp annealing operation is carried out at a temperature higher than 650° C. for 30 seconds to expel the Ar atoms from the conductive layer 3 .
  • one of the wafers W is moved by the plate 541 and the arms 542 from the heating chamber 56 - 1 to the sputtering chamber 55 - 1 . Then, a sputtering process is carried out to form a conductive layer 6 .
  • one of the wafers W is moved by the plate 541 and the arms 542 from the sputterning chamber 55 - 1 to the loading chamber 57 - 1 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

In a method for manufacturing a semiconductor device, a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Then, a heating process at a temperature higher than about 650° C. is performed upon the first conductive layer to expel Ar atoms from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method for manufacturing a semiconductor device by a plasma etching process using argon (Ar) ions. [0002]
  • 2. Description of the Related Art [0003]
  • In a prior art method for manufacturing a semiconductor device, a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer. This will be explained later in detail. [0004]
  • In the above-described semiconductor device, if a heating process at a temperature such as 840° C. is carried out at a post stage, argon atoms immersed in the first conductive layer are moved to an interface between the first and second conductive layers. As a result, the contact characteristics between the first and second conductive layers are deteriorated. At worst, the second conductive layer is peeled from the first conductive layer, and therefore, the second conductive layer is electrically separated from the first conductive layer. This would degrade the performance of the semiconductor device. [0005]
  • Note that JP-A-4-10621 discloses a radio-frequency (RF) plasma etching process using halogen fluoride diluted by Ar gas for silicon nitride, and JP-A-11-243082 discloses an RF plasma etching process using a mixture of fluorine gas and Ar gas for silicon oxide. However, neither one suggests the expulsion of Ar atoms immersed into semiconductor devices. [0006]
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to expel Ar atoms from a semiconductor device to improve the contact characteristics between two conductive layers, one of the conductive layers being formed by a sputtering process. [0007]
  • According to the present invention, in a method for manufacturing a semiconductor device, a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Then, a heating process at a temperature higher than about 650° C. is performed upon the first conductive layer to expel Ar atoms from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer.[0008]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: [0009]
  • FIGS. 1A through 1C are cross-sectional views for explaining a prior art method for manufacturing a semiconductor device; [0010]
  • FIG. 2 is a cross-sectional view for explaining a problem created in the method as illustrated in FIGS. 1A through 1C; [0011]
  • FIGS. 3A through 3D are cross-sectional views for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention; [0012]
  • FIG. 4 is a graph for showing the expelling characteristics of argon atoms in FIG. 3C; and [0013]
  • FIG. 5 is a diagram illustrating an apparatus for carrying out the method as illustrated in FIGS. 3A, 3B, [0014] 3C and 3D.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Before the description of the preferred embodiment, a prior art method for manufacturing a semiconductor device will be explained with reference to FIGS. 1A through 1C. [0015]
  • First, referring to FIG. 1A, a [0016] silicon oxide layer 2 is formed on a silicon substrate 1 where active regions are already formed. Then, the silicon oxide layer 2 is perforated by a photolithography and etching process. Then, a conductive layer 3 made of aluminum or refractory metal such as WSi is deposited by a sputtering process or the like. Then, a boron-included phosphor-silicated silicon glass (BPSG) layer 4 and a silicon nitride layer 5 are sequentially deposited by a chemical vapor deposition (CVD) process. Then, the silicon nitride layer 5 and the BPSG layer 4 are perforated by a photolithography and etching process, so that a throughhole TH is formed therein. In this case, since the conductive layer 3 is oxidized, a very thin natural oxide layer 6 is formed on the conductive layer 3.
  • Next, referring to FIG. 1B, an RF plasma etching process using Ar ions is performed upon the [0017] natural oxide layer 6 to remove it. As a result, some argon ions are immersed into the conductive layer 3 as indicated by X.
  • Finally, referring to FIG. 1C, a [0018] conductive layer 6 made of aluminum or refractory metal such as WSi is deposited on the silicon nitride layer 5 and the throughhole TH by a sputtering process or the like, so that the conductive layer 6 is in contact with the conductive layer 3 at the throughhole TH.
  • In the semiconductor device manufactured as illustrated in FIGS. 1A, 1B and [0019] 1C, if a heating process at a temperature such as 840° C. is carried out at a post stage, argon atoms immersed in the conductive layer 3 are moved to an interface between the conductive layers 3 and 6. As a result, the contact characteristics between the conductive layers 3 and 6 are deteriorated. At worst, the conductive layer 6 is peeled from the conductive layer 3, and therefore, the conductive layer 6 is electrically separated from the conductive layer 3. This would degrade the performance of the semiconductor device.
  • An embodiment of the method for manufacturing a semiconductor device according to the present invention will be explained next with reference to FIGS. 3A through 3D. [0020]
  • First, referring to FIG. 3A, in the same way as in FIG. 1A, a [0021] silicon oxide layer 2 is formed on a silicon substrate 1 where active regions are already formed. Then, the silicon oxide layer 2 is perforated by a photolithography and etching process. Then, a conductive layer 3 made of aluminum or refractory metal such as WSi is deposited by a sputtering process or the like. Then, a BPSG layer 4 and a silicon nitride layer 5 are sequentially deposited by a CVD process. Then, the silicon nitride layer 5 and the BPSG layer 4 are perforated by a photolithography and etching process, so that a throughhole TH is formed therein. In this case, since the conductive layer 3 is oxidized, a very thin natural oxide layer 6 is formed on the conductive layer 3.
  • Next, referring to FIG. 3B, in the same way as in FIG. 1B, an RF plasma etching process using Ar ions is performed upon the [0022] natural oxide layer 6 to remove it. As a result, some argon ions are immersed into the conductive layer 3 as indicated by X.
  • Next, referring to FIG. 3C, a heating process at a temperature higher than about 650° C. is carried out. This will be explained later in detail. As a result, the argon atoms immersed in the [0023] conductive layer 3 are effectively expelled therefrom as indicated by arrows.
  • Finally, referring FIG. 3D, in the same way as in to FIG. 1C, a [0024] conductive layer 6 made of aluminum or refractory metal such as WSi is deposited on the silicon nitride layer 5 and the throughhole TH by a sputtering process on the like, so that the conductive layer 6 is in contact with the conductive layer 3 at the throughhole TH.
  • In the semiconductor device manufactured as illustrated in FIGS. 3A, 3B, [0025] 3C and 3D, if a heating process at a temperature such as 840° C. is carried out at a post stage, since no argon atoms are immersed in the conductive layer 3, the contact characteristics between the conductive layers 3 and 6 are not deteriorated. In addition, the conductive layer 6 is never peeled from the conductive layer 3, and therefore, the conductive layer 6 is never electrically separated from the conductive layer 3. This would not degrade the performance of the semiconductor device.
  • The expelling characteristics of argon atoms from the [0026] conductive layer 3 by the heating process in FIG. 3C are shown in FIG. 4 where the Ar expelling amount at 850° C. for 30 seconds under a high vacuum state of 1.0×10−6 Torr (=1.33 ×10−4 Pa) is defined as 100%. As shown in FIG. 4, when the heating temperature is about 650° C., the Ar expelling amount is about 70%, and when the heating temperature is about 700° C., the Ar expelling amount is about 90%. Therefore, the heating temperature in FIG. 3C is preferably higher than about 650° C.
  • In FIG. 5, which illustrates an apparatus for carrying out the method as illustrated in FIGS. 3A, 3B, [0027] 3C and 3D, reference numeral 51 designates a vacuum unit where an RF plasma etching chamber 52, a cooling camber 53 and a separation chamber 54 are provided.
  • Also, a [0028] plate 541 for mounting a wafer W, expansible arms 542 for supporting the plate 541, and a pivot pedestal 543 for pivotally supporting the arms 542 are provided in the separation chamber 54.
  • Further, sputtering chambers [0029] 55-1 and 55-2, heating chambers 56-1 and 56-2 and loading chambers 57-1 and 57-2 are connected to the vacuum unit 51. The heating chambers 56 includes a lamp annealer.
  • Note that entire apparatus of FIG. 5 is in one vacuum atmosphere. [0030]
  • Also, the apparatus of FIG. 5 is controlled by a [0031] control circuit 58 which may consist of a microcomputer.
  • The operation of the apparatus of FIG. 5 will be explained below. [0032]
  • First, a package including wafers W, in which layers [0033] 2, 3, 4 and 5 are already formed on a silicon substrate 1, is set in the loading chamber 57-1, and one of the wafers W is moved by the plate 541 and the arms 542 from the loading chamber 57-1 to the RF plasma etching chamber 52. After that, the vacuum chamber 51 is vacuumized at about 1.0×10−6 Torr (=1.33×10−4 Pa).
  • Next, in the RF [0034] plasma etching chamber 52, an RF plasma etching process using Ar ions is carried out to remove a natural oxide layer 6 from the conductive layer 3.
  • Next, one of the wafers W is moved by the [0035] plate 541 and the arms 542 from the RF plasma etching chamber 52 to the heating chamber 56-1. Then, a heating process using the lamp annealing operation is carried out at a temperature higher than 650° C. for 30 seconds to expel the Ar atoms from the conductive layer 3.
  • Next, one of the wafers W is moved by the [0036] plate 541 and the arms 542 from the heating chamber 56-1 to the sputtering chamber 55-1. Then, a sputtering process is carried out to form a conductive layer 6.
  • Finally, one of the wafers W is moved by the [0037] plate 541 and the arms 542 from the sputterning chamber 55-1 to the loading chamber 57-1.
  • As explained hereinabove, according to the present invention, since Ar atoms are sufficiently expelled from an underlying conductive layer before an overlying conductive layer is formed by a sputtering process, the contact characteristics between the two conductive layers can be improved, which would not degrade the performance of semiconductor devices. [0038]

Claims (3)

1. An apparatus for manufacturing a semiconductor device comprising:
a plasma etching chamber for performing a plasma etching process using Ar ions upon said semiconductor device;
a heating chamber for heating said semiconductor device at a temperature higher than about 650° C. to expel Ar atoms from said semiconductor device;
a sputtering chamber for forming a conductive layer of said semiconductor device;
a separation chamber, coupled to said plasma etching chamber, said heating chamber and said sputtering chamber, said separation chamber being provided with members for moving said semiconductor device from one of said plasma etching chamber, said heating chamber and said sputtering chamber to another,
said plasma etching chamber, said heating chamber, said sputtering chamber and said separation chamber being in one vacuum atmosphere.
2. The apparatus as set forth in claim 1, wherein said heating chamber is provided with a Ramp annealer.
3. The apparatus as set forth in claim 1, wherein said plasma etching process is a radio-frequency plasma etching process.
US10/187,968 1999-11-22 2002-07-03 Method for manufacturing semiconductor device capable of expelling argon gas Abandoned US20020177315A1 (en)

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JP33200399A JP2001148367A (en) 1999-11-22 1999-11-22 Processing method and apparatus for semiconductor device
US09/716,287 US6444585B1 (en) 1999-11-22 2000-11-21 Method for manufacturing semiconductor device capable of expelling argon gas
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JP2881796B2 (en) * 1989-02-13 1999-04-12 ソニー株式会社 Method for selective formation of tungsten film
US5254872A (en) * 1989-03-14 1993-10-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JPH03165515A (en) * 1989-11-25 1991-07-17 Seiko Epson Corp Contact forming method
JPH0410621A (en) 1990-04-27 1992-01-14 Kawasaki Steel Corp Etching-processing method for silicon nitride film, and its device
JPH0423323A (en) * 1990-05-14 1992-01-27 Fujitsu Ltd Manufacture of semiconductor device
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JP3382031B2 (en) * 1993-11-16 2003-03-04 株式会社東芝 Method for manufacturing semiconductor device
JPH08288219A (en) 1995-04-13 1996-11-01 Sony Corp Apparatus and method for treatment of semiconductor
JPH09102541A (en) * 1995-10-05 1997-04-15 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH09115866A (en) * 1995-10-17 1997-05-02 Mitsubishi Electric Corp Semiconductor device manufacturing method
KR100296365B1 (en) * 1996-06-28 2001-11-30 고지마 마타오 Heat treatment method of silicon single crystal wafer, heat treatment device and silicon single crystal wafer and manufacturing method thereof
JP3905232B2 (en) 1997-12-27 2007-04-18 東京エレクトロン株式会社 Etching method

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Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013882/0640

Effective date: 20021101

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION