US20020146862A1 - Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice - Google Patents

Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice Download PDF

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Publication number
US20020146862A1
US20020146862A1 US10/156,976 US15697602A US2002146862A1 US 20020146862 A1 US20020146862 A1 US 20020146862A1 US 15697602 A US15697602 A US 15697602A US 2002146862 A1 US2002146862 A1 US 2002146862A1
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Prior art keywords
pads
integrated circuit
circuit die
base
flip
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US10/156,976
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US6605489B2 (en
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James Wark
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US Bank NA
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Micron Technology Inc
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Priority to US10/156,976 priority Critical patent/US6605489B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of US20020146862A1 publication Critical patent/US20020146862A1/en
Priority to US10/634,074 priority patent/US6869826B2/en
Application granted granted Critical
Publication of US6605489B2 publication Critical patent/US6605489B2/en
Priority to US11/086,144 priority patent/US7109059B2/en
Priority to US11/252,389 priority patent/US7282792B2/en
Priority to US11/601,970 priority patent/US7411286B2/en
Priority to US11/601,969 priority patent/US7402902B2/en
Priority to US11/602,051 priority patent/US7423339B2/en
Priority to US11/601,883 priority patent/US7423338B2/en
Priority to US12/197,514 priority patent/US7776652B2/en
Priority to US12/197,453 priority patent/US7812436B2/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
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Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Definitions

  • the present invention relates in general to stacked integrated circuit (IC) dice, and, in particular, to devices and methods for stacking wire-bonded IC dice on flip-chip bonded IC dice.
  • IC integrated circuit
  • Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from a semiconductor wafer, such as a silicon wafer, on which multiple IC's have been fabricated.
  • a semiconductor wafer such as a silicon wafer
  • bare IC dice are packaged to protect them from corrosion by enclosing them in die packages.
  • Such packages work well to protect IC dice, but they can be more bulky than desirable for certain multi-chip applications requiring compact die packaging.
  • the back-side surface of a bare IC die is directly mounted on the surface of a Printed Circuit Board (PCB), and bond pads on the front-side surface of the bare die are then wire-bonded to wire-bondable pads on the surface of the PCB to interconnect circuitry in the die with external circuitry through conductive traces on the PCB.
  • This technique may be referred to as “Chip-On-Board (COB) with wire-bonding.”
  • COB Chip-On-Board
  • conductive “bumps” on the front-side surface of a bare IC die are bonded to “flip-chip” pads on the surface of a PCB to interconnect circuitry in the die with external circuitry.
  • a further technique involves stacking exotic IC dice having conductive bumps or pads on both sides on top of one another and then flip-chip bonding the dice to a PCB and to one another.
  • an additional technique involves stacking bare IC dice on top of a die mounted to a PCB using the COB with the wire-bonding technique described above. These stacked dice are then wire-bonded to the PCB and to one another, or are interconnected using flip-chip bumps, or both.
  • a still further technique involves back-side bonding a pair of IC dice to one another and then wire-bonding bond pads on the front-sides of the bonded dice to a PCB.
  • An inventive electronic device such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided.
  • the flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads.
  • a first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die of the same type as the first die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads.
  • the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner. Because the first and second IC dice are of the same type, the flip-chip pads and the wire-bondable pads are interconnected so they “electrically mirror” one another (i.e., so corresponding bond pads on the “flipped” first IC die and the second IC die are interconnected).
  • a memory device includes one or more electronic devices, as described above.
  • an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base, first IC die, and second IC die, as described above.
  • the wire-bondable and flip-chip pads of the electronic device, described above are interconnected in single and multiple layers of the base.
  • an electronic device as described above, also includes a third IC die back-side attached to the second IC die and then wire-bonded to the wire-bondable pads on the surface of the base.
  • an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base and first, second, and third IC dice, as described above.
  • a base has a surface on which flip-chip pads are arranged in a pattern.
  • the flip-chip pads are flip-chip connectable to flip-chip bumps on a first IC die carryable on the surface.
  • Wire-bondable pads are interconnected with the flip-chip pads and are arranged in a pattern on the surface so the wire-bondable pads as a group “electrically mirror” the flip-chip pads as a group.
  • the wire-bondable pads at least partially bound an area defined by the pattern of flip-chip pads and are wire-bondable to bond pads on a second IC die carryable on the first IC die.
  • an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base, as described above.
  • a method of assembling a multi-chip structure on a base having a surface for carrying the structure includes: providing a plurality of flip-chip pads arranged in a pattern on the surface of the base defining an area thereon; providing a plurality of wire-bondable pads arranged in a pattern on the surface of the base and at least partially bounding the area defined by the pattern of flip-chip pads; interconnecting the wire-bondable pads and the flip-chip pads so the wire-bondable pads as a group electrically mirror the flip-chip pads as a group; positioning a first IC chip so a front-side surface thereof faces the surface of the base with a gap therebetween and with a plurality of flip-chip bumps on the front-side surface aligned with the flip-chip pads on the surface of the base; connecting the flip-chip bumps on the front-side surface of the first chip to the flip-chip pads on the surface of the base; sealing the gap between the front-side surface of the first chip and the surface of the base;
  • a method of repairing an IC die having flip-chip bumps that are bonded to flip-chip pads on a surface of a die-carrying base, such as a printed circuit board includes: providing wire-bondable pads on the surface of the base arranged generally about the perimeter of the flip-chip bonded die and each connected to one of a group of conductors through which the flip-chip bonded die communicates with circuitry external to the die; back-bonding a replacement IC die to the back-side surface of the flip-chip bonded IC die; disconnecting the flip-chip bonded IC die from the conductors; and wire-bonding bond pads on the replacement die to the wire-bondable pads on the surface of the base so the replacement die may communicate with circuitry external to the die.
  • FIG. 1 is an isometric view of a portion of a multi-chip module in accordance with the present invention
  • FIG. 2 is an isometric view of the multi-chip module of FIG. 1 including an additional stacked die
  • FIGS. 3A and 3B are respective top plan and isometric views of the multi-chip module of FIG. 1 showing alternative embodiments of the module in detail;
  • FIG. 4 is a block diagram of an electronic system including the multi-chip module of FIG. 1.
  • an inventive Multi-Chip Module (MCM) 10 includes a flip-chip integrated circuit (IC) die 12 with flip-chip bumps (not shown) on its front-side surface 16 , reflow-soldered in a well-known manner to flip-chip pads (not shown) screen printed on a surface 20 of a printed circuit board (PCB) 22 .
  • Circuitry (not shown) within the flip-chip IC die 12 communicates with external circuitry (not shown) through conductors 24 connected to the flip-chip pads (not shown).
  • the present invention will be described with respect to the MCM 10 , it will be understood by those having skill in the field of the invention that the invention includes within its scope a wide variety of electronic devices other than MCM's, including, for example, memory devices such as Single In-line Memory Modules (SIMM's) and Dual In-line Memory Modules (DIMM's).
  • the flip-chip IC die 12 may comprise any IC die having flip-chip bumps, and that the flip-chip IC die 12 may be bonded to the flip-chip pads (not shown) using methods other than reflow soldering.
  • the flip-chip pads (not shown) may be provided on the surface 20 using a method other than screen printing, such as selective plating, and that the present invention includes within its scope bases other than the PCB 22 .
  • a wire-bondable IC die 26 is stacked on top of the flip-chip IC die 12 . This may be done, for example, to increase the amount of Dynamic Random Access Memory (DRAM) provided on the PCB 22 if the IC dice 12 and 26 are DRAM IC dice. It may also be done to replace the flip-chip IC die 12 with the wire-bondable IC die 26 if the flip-chip IC die 12 is defective. Of course, it will be understood that the wire-bondable IC die 26 may be any wire-bondable IC die.
  • DRAM Dynamic Random Access Memory
  • a back-side surface of the wire-bondable IC die 26 is attached to a back-side surface of the flip-chip IC die 12 with epoxy 28 , and bond pads on a front-side surface of the wire-bondable IC die 26 are wire-bonded to wire-bondable pads 30 screen printed on the surface 20 of the PCB 22 .
  • the IC dice 12 and 26 may be back-bonded using means other than epoxy, and that the wire-bondable pads 30 may be provided on the surface 20 using a method other than screen printing, such as selective plating.
  • the wire-bondable IC die 26 is being used to replace a defective flip-chip IC die 12 , communication between the defective flip-chip IC die 12 and external circuitry (not shown) is interrupted by cutting the conductors 24 at locations proximate to each of the flip-chip pads (not shown).
  • the present invention includes within its scope other methods for interrupting communication between the flip-chip IC die 12 and external circuitry, including, for example, de-selecting or de-powering the flip-chip IC die 12 . With communication between the flip-chip IC die 12 and external circuitry interrupted, the wire-bondable IC die 26 communicates with external circuitry through the conductors 24 without interference from the defective flip-chip IC die 12 .
  • the present invention provides a simple stacking technique for IC dice flip-chip mounted to a PCB or any other base, and the inventive technique is useful for repairing or replacing flip-chip mounted IC dice.
  • a method of assembling the MCM 10 includes: screen printing or selectively plating the flip-chip pads (not shown) and wire-bondable pads 30 ; picking and placing the flip-chip IC die 12 ; reflow soldering the flip-chip bumps (not shown) to the flip-chip pads (not shown); testing the connection between the flip-chip bumps (not shown) and the flip-chip pads and, if the connection fails the test, repairing the connection; underfilling the flip-chip IC die 12 ; picking and placing the wire-bondable IC die 26 ; back-bonding the IC dice 12 and 26 to one another with un-cured epoxy; curing the epoxy; wire-bonding the bond pads on the wire-bondable IC die 26 to the wire-bondable pads 30 ; testing the connection between the bond pads and the wire-bondable pads 30 and, if the connection fails the test, repairing the connection; and encapsulating the IC dice 12 and 26 .
  • the MCM 10 includes an additional IC die 32 back-side attached to the wire-bondable IC die 26 and wire-bonded to the bond pads of the wire-bondable IC die 26 .
  • the density of dice on the PCB 22 is increased.
  • the present invention includes within its scope multiple dice stacked on top of the wire-bondable IC die 26 .
  • the IC dice 12 (shown in FIG. 1) and 26 are identical with respect to the arrangement of their bond pads and the functions associated with their respective bond pads.
  • the bond pads of the flip chip IC die 12 (shown in FIG. 1) are oriented in a “flipped” relationship with respect to the bond pads of the wire-bondable IC die 26 .
  • the flip chip pads 18 on the PCB 22 are interconnected with the wire-bondable pads 30 on the surface 20 of the PCB 22 so bond pads on each of the dice 12 (shown in FIG. 1) and 26 that are associated with the same function are interconnected, thus allowing both dice 12 and 26 to operate in parallel.
  • the flip chip pads 18 may be said to then “electrically mirror” the wire bondable pads 30 .
  • FIG. 3A it will be understood that a wide variety of interconnection arrangements which vary widely from that shown in FIG. 3A is within the scope of the present invention.
  • the IC dice 12 and 26 are identical with respect to the arrangement of their bond pads and the functions associated with their respective bond pads.
  • the bond pads of the flip chip IC die 12 are oriented in a “flipped” relationship with respect to the bond pads of the wire-bondable IC die 26 .
  • flip chip pads 34 on the PCB 22 are interconnected with wire-bondable pads 36 on the PCB 22 through different layers 37 and 38 in the PCB 22 so bond pads on each of the IC dice 12 and 26 that are associated with the same function are interconnected, thus allowing both IC dice 12 and 26 to operate in parallel.
  • the flip chip pads 34 may be said to then “electrically mirror” the wire bondable pads 36 .
  • the flip chip pads 34 may be said to then “electrically mirror” the wire bondable pads 36 .
  • multi-layer PCB interconnection arrangements which vary widely from that shown in FIG. 3B are within the scope of the present invention.
  • the MCM 10 is incorporated into a memory device 40 in an electronic system 42 that also includes an input device 44 , an output device 46 , and a processor device 48 . It will be understood that the MCM 10 may alternatively be incorporated into any one or all of the input, output, and processor devices 44 , 46 , and 48 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of application Ser. No. 09/642,134, filed Aug. 18, 2000, pending, which is a continuation of application Ser. No. 09/390,889, filed Sep. 7, 1999, now U.S. Pat. No. 6,140,149, issued Oct. 31, 2000, which is a continuation of application Ser. No. 08/914,719, filed Aug. 19, 1997, now U.S. Pat. No. 6,071,754, issued Jun. 6, 2000, which is a continuation of application Ser. No. 08/752,802, filed Nov. 20, 1996, now U.S. Pat. No. 5,696,031, issued Dec. 9, 1997. The present application is also related to a prior application entitled “FLIP CHIP AND CONVENTIONAL STACK” that was filed Feb. 20, 1996, has Ser. No. 08/602,503, pending, and is assigned in common with the present application to Micron Technology, Inc.[0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates in general to stacked integrated circuit (IC) dice, and, in particular, to devices and methods for stacking wire-bonded IC dice on flip-chip bonded IC dice. [0003]
  • 2. State of the Art [0004]
  • Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from a semiconductor wafer, such as a silicon wafer, on which multiple IC's have been fabricated. Traditionally, bare IC dice are packaged to protect them from corrosion by enclosing them in die packages. Such packages work well to protect IC dice, but they can be more bulky than desirable for certain multi-chip applications requiring compact die packaging. [0005]
  • Accordingly, a variety of compact die packaging techniques exists. In one such technique, the back-side surface of a bare IC die is directly mounted on the surface of a Printed Circuit Board (PCB), and bond pads on the front-side surface of the bare die are then wire-bonded to wire-bondable pads on the surface of the PCB to interconnect circuitry in the die with external circuitry through conductive traces on the PCB. This technique may be referred to as “Chip-On-Board (COB) with wire-bonding.” In another such technique, conductive “bumps” on the front-side surface of a bare IC die are bonded to “flip-chip” pads on the surface of a PCB to interconnect circuitry in the die with external circuitry. Both the COB with wire-bonding technique and the flip-chip technique are well-known to those of skill in the field of this invention, and are described in more detail in U.S. Pat. Nos. 5,422,435, 5,495,398, 5,502,289, and 5,508,561. [0006]
  • While these traditional compact die packaging techniques are more compact than the bulky die packages described above, they still are not compact enough for some multi-chip applications requiring many chips in a small area. For example, an ever-growing demand for Dynamic Random Access Memory (DRAM) capacity is driving a need for ever-more DRAM memory chips to be packed into a small area. [0007]
  • As a consequence, a variety of techniques exists for stacking chips on top of one another to increase the number of chips provided in a small area. As described in U.S. Pat. Nos. 5,228,192, 5,252,857, and 5,514,907, some of these techniques involve mounting individual bare IC dice, or individual dice packaged using a traditional die package, to parts of a structure, and then assembling the structure so the mounted dice are stacked. Also, as described in U.S. Pat. No. 5,323,060, another technique involves stacking bare IC dice on top of one another, and then wire-bonding the dice to a PCB and to one another. Similarly, as described in U.S. Pat. No. 5,399,898, a further technique involves stacking exotic IC dice having conductive bumps or pads on both sides on top of one another and then flip-chip bonding the dice to a PCB and to one another. Further, as described in U.S. Pat. Nos. 5,422,435, 5,495,398, and 5,502,289, an additional technique involves stacking bare IC dice on top of a die mounted to a PCB using the COB with the wire-bonding technique described above. These stacked dice are then wire-bonded to the PCB and to one another, or are interconnected using flip-chip bumps, or both. In addition, as described in U.S. Pat. No. 5,527,740, a still further technique involves back-side bonding a pair of IC dice to one another and then wire-bonding bond pads on the front-sides of the bonded dice to a PCB. [0008]
  • While all of these stacking techniques work well to increase the density of chips provided in a given area, they do not provide a simple stacking technique for IC dice flip-chip mounted to a PCB in the manner described above. They also do not provide a stacking technique that can be used to repair or replace a defective IC die flip-chip mounted to a PCB. Such “repair” stacking techniques are well known for IC dice mounted to a PCB using the COB with wire-bonding technique, as described in U.S. Pat. No. 4,567,643. [0009]
  • Therefore, there is a need in the art for a simple stacking technique for IC dice flip-chip mounted to a PCB or any other base, and the inventive technique should be useful for repairing or replacing flip-chip mounted IC dice. [0010]
    • BRIEF SUMMARY OF THE INVENTION
  • An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die of the same type as the first die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner. Because the first and second IC dice are of the same type, the flip-chip pads and the wire-bondable pads are interconnected so they “electrically mirror” one another (i.e., so corresponding bond pads on the “flipped” first IC die and the second IC die are interconnected). [0011]
  • In another embodiment of the present invention, a memory device includes one or more electronic devices, as described above. In a further embodiment, an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base, first IC die, and second IC die, as described above. In still further embodiments, the wire-bondable and flip-chip pads of the electronic device, described above, are interconnected in single and multiple layers of the base. [0012]
  • In an additional embodiment, an electronic device, as described above, also includes a third IC die back-side attached to the second IC die and then wire-bonded to the wire-bondable pads on the surface of the base. In a still additional embodiment, an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base and first, second, and third IC dice, as described above. [0013]
  • In still another embodiment, a base has a surface on which flip-chip pads are arranged in a pattern. The flip-chip pads are flip-chip connectable to flip-chip bumps on a first IC die carryable on the surface. Wire-bondable pads are interconnected with the flip-chip pads and are arranged in a pattern on the surface so the wire-bondable pads as a group “electrically mirror” the flip-chip pads as a group. The wire-bondable pads at least partially bound an area defined by the pattern of flip-chip pads and are wire-bondable to bond pads on a second IC die carryable on the first IC die. An additional embodiment is a method of making a base, as described above. [0014]
  • In yet another embodiment, an electronic system includes input, output, memory, and processor devices, and one of these devices includes a base, as described above. [0015]
  • In an additional embodiment, a method of assembling a multi-chip structure on a base having a surface for carrying the structure includes: providing a plurality of flip-chip pads arranged in a pattern on the surface of the base defining an area thereon; providing a plurality of wire-bondable pads arranged in a pattern on the surface of the base and at least partially bounding the area defined by the pattern of flip-chip pads; interconnecting the wire-bondable pads and the flip-chip pads so the wire-bondable pads as a group electrically mirror the flip-chip pads as a group; positioning a first IC chip so a front-side surface thereof faces the surface of the base with a gap therebetween and with a plurality of flip-chip bumps on the front-side surface aligned with the flip-chip pads on the surface of the base; connecting the flip-chip bumps on the front-side surface of the first chip to the flip-chip pads on the surface of the base; sealing the gap between the front-side surface of the first chip and the surface of the base; positioning a second IC chip so a back-side surface thereof faces a back-side surface of the first chip; attaching the back-side surface of the second chip to the back-side surface of the first chip; connecting a plurality of bond pads on a front-side surface of the second chip to the wire-bondable pads on the surface of the base; and sealing the first and second chips. [0016]
  • In a further embodiment, a method of repairing an IC die having flip-chip bumps that are bonded to flip-chip pads on a surface of a die-carrying base, such as a printed circuit board, includes: providing wire-bondable pads on the surface of the base arranged generally about the perimeter of the flip-chip bonded die and each connected to one of a group of conductors through which the flip-chip bonded die communicates with circuitry external to the die; back-bonding a replacement IC die to the back-side surface of the flip-chip bonded IC die; disconnecting the flip-chip bonded IC die from the conductors; and wire-bonding bond pads on the replacement die to the wire-bondable pads on the surface of the base so the replacement die may communicate with circuitry external to the die.[0017]
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is an isometric view of a portion of a multi-chip module in accordance with the present invention; [0018]
  • FIG. 2 is an isometric view of the multi-chip module of FIG. 1 including an additional stacked die; [0019]
  • FIGS. 3A and 3B are respective top plan and isometric views of the multi-chip module of FIG. 1 showing alternative embodiments of the module in detail; and [0020]
  • FIG. 4 is a block diagram of an electronic system including the multi-chip module of FIG. 1.[0021]
    • DETAILED DESCRIPTION OF THE INVENTION
  • As shown in FIG. 1, an inventive Multi-Chip Module (MCM) [0022] 10 includes a flip-chip integrated circuit (IC) die 12 with flip-chip bumps (not shown) on its front-side surface 16, reflow-soldered in a well-known manner to flip-chip pads (not shown) screen printed on a surface 20 of a printed circuit board (PCB) 22. Circuitry (not shown) within the flip-chip IC die 12 communicates with external circuitry (not shown) through conductors 24 connected to the flip-chip pads (not shown). Although the present invention will be described with respect to the MCM 10, it will be understood by those having skill in the field of the invention that the invention includes within its scope a wide variety of electronic devices other than MCM's, including, for example, memory devices such as Single In-line Memory Modules (SIMM's) and Dual In-line Memory Modules (DIMM's). It will also be understood that the flip-chip IC die 12 may comprise any IC die having flip-chip bumps, and that the flip-chip IC die 12 may be bonded to the flip-chip pads (not shown) using methods other than reflow soldering. Further, it will be understood that the flip-chip pads (not shown) may be provided on the surface 20 using a method other than screen printing, such as selective plating, and that the present invention includes within its scope bases other than the PCB 22.
  • A wire-bondable IC die [0023] 26 is stacked on top of the flip-chip IC die 12. This may be done, for example, to increase the amount of Dynamic Random Access Memory (DRAM) provided on the PCB 22 if the IC dice 12 and 26 are DRAM IC dice. It may also be done to replace the flip-chip IC die 12 with the wire-bondable IC die 26 if the flip-chip IC die 12 is defective. Of course, it will be understood that the wire-bondable IC die 26 may be any wire-bondable IC die.
  • A back-side surface of the wire-bondable IC die [0024] 26 is attached to a back-side surface of the flip-chip IC die 12 with epoxy 28, and bond pads on a front-side surface of the wire-bondable IC die 26 are wire-bonded to wire-bondable pads 30 screen printed on the surface 20 of the PCB 22. Of course, it will be understood that the IC dice 12 and 26 may be back-bonded using means other than epoxy, and that the wire-bondable pads 30 may be provided on the surface 20 using a method other than screen printing, such as selective plating.
  • As will be described in more detail below with respect to FIGS. 3A and 3B, it will also be understood that, while the present invention will be described with respect to [0025] IC dice 12 and 26 that perform the same functions and thus require common connections among the flip chip pads (not shown) and the wire-bondable pads 30, the present invention includes within its scope pads that are connected to different conductors so the IC dice 12 and 26 may receive different signals and perform different functions.
  • If the wire-bondable IC die [0026] 26 is being used to replace a defective flip-chip IC die 12, communication between the defective flip-chip IC die 12 and external circuitry (not shown) is interrupted by cutting the conductors 24 at locations proximate to each of the flip-chip pads (not shown). Of course, the present invention includes within its scope other methods for interrupting communication between the flip-chip IC die 12 and external circuitry, including, for example, de-selecting or de-powering the flip-chip IC die 12. With communication between the flip-chip IC die 12 and external circuitry interrupted, the wire-bondable IC die 26 communicates with external circuitry through the conductors 24 without interference from the defective flip-chip IC die 12.
  • Thus, the present invention provides a simple stacking technique for IC dice flip-chip mounted to a PCB or any other base, and the inventive technique is useful for repairing or replacing flip-chip mounted IC dice. [0027]
  • A method of assembling the [0028] MCM 10 includes: screen printing or selectively plating the flip-chip pads (not shown) and wire-bondable pads 30; picking and placing the flip-chip IC die 12; reflow soldering the flip-chip bumps (not shown) to the flip-chip pads (not shown); testing the connection between the flip-chip bumps (not shown) and the flip-chip pads and, if the connection fails the test, repairing the connection; underfilling the flip-chip IC die 12; picking and placing the wire-bondable IC die 26; back-bonding the IC dice 12 and 26 to one another with un-cured epoxy; curing the epoxy; wire-bonding the bond pads on the wire-bondable IC die 26 to the wire-bondable pads 30; testing the connection between the bond pads and the wire-bondable pads 30 and, if the connection fails the test, repairing the connection; and encapsulating the IC dice 12 and 26.
  • As shown in FIG. 2, the [0029] MCM 10 includes an additional IC die 32 back-side attached to the wire-bondable IC die 26 and wire-bonded to the bond pads of the wire-bondable IC die 26. As a result, the density of dice on the PCB 22 is increased. Of course, although only one additional die 32 is shown in FIG. 2 stacked on top of the wire-bondable IC die 26, the present invention includes within its scope multiple dice stacked on top of the wire-bondable IC die 26.
  • As shown in a top plan view in FIG. 3A, the IC dice [0030] 12 (shown in FIG. 1) and 26 are identical with respect to the arrangement of their bond pads and the functions associated with their respective bond pads. As a result, the bond pads of the flip chip IC die 12 (shown in FIG. 1) are oriented in a “flipped” relationship with respect to the bond pads of the wire-bondable IC die 26. Consequently, the flip chip pads 18 on the PCB 22 are interconnected with the wire-bondable pads 30 on the surface 20 of the PCB 22 so bond pads on each of the dice 12 (shown in FIG. 1) and 26 that are associated with the same function are interconnected, thus allowing both dice 12 and 26 to operate in parallel. The flip chip pads 18 may be said to then “electrically mirror” the wire bondable pads 30. Of course, it will be understood that a wide variety of interconnection arrangements which vary widely from that shown in FIG. 3A is within the scope of the present invention.
  • As shown in FIG. 3B in a portion of an alternative interconnection arrangement, the [0031] IC dice 12 and 26 are identical with respect to the arrangement of their bond pads and the functions associated with their respective bond pads. As a result, the bond pads of the flip chip IC die 12 are oriented in a “flipped” relationship with respect to the bond pads of the wire-bondable IC die 26. Consequently, flip chip pads 34 on the PCB 22 are interconnected with wire-bondable pads 36 on the PCB 22 through different layers 37 and 38 in the PCB 22 so bond pads on each of the IC dice 12 and 26 that are associated with the same function are interconnected, thus allowing both IC dice 12 and 26 to operate in parallel. The flip chip pads 34 may be said to then “electrically mirror” the wire bondable pads 36. Of course, it will be understood that a wide variety of multi-layer PCB interconnection arrangements which vary widely from that shown in FIG. 3B are within the scope of the present invention.
  • As shown in FIG. 4, the [0032] MCM 10 is incorporated into a memory device 40 in an electronic system 42 that also includes an input device 44, an output device 46, and a processor device 48. It will be understood that the MCM 10 may alternatively be incorporated into any one or all of the input, output, and processor devices 44, 46, and 48.
  • Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described. [0033]

Claims (32)

What is claimed is:
1. A method of assembling an integrated circuit die on a base having a first plurality of pads and having a second plurality of pads on the surface of said base, said method comprising:
connecting at least one pad of the first plurality of pads to at least one pad of the second plurality of pads;
providing a first integrated circuit die having a front-side surface having a plurality of flip-chip bumps thereon and having a back-side surface;
positioning the front-side surface of the first integrated circuit die facing the surface of the base;
aligning at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die aligned with at least one pad of the first plurality of pads on the surface of the base;
connecting at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die to at least one pad of the first plurality of pads on the surface of the base;
providing a second integrated circuit die having a front-side surface having a plurality of bond pads thereon and having a back-side surface;
positioning the back-side surface of the second integrated circuit die facing the back-side surface of the first integrated circuit die;
attaching the back-side surface of the second integrated circuit die to the back-side surface of the first integrated circuit die; and
connecting at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die to at least one pad of the second plurality of pads on the surface of the base.
2. The method of claim 1, further comprising:
sealing between at least a portion of the front-side surface of the first integrated circuit die and the surface of the base.
3. The method of claim 2, wherein the step of sealing between at least a portion the front-side surface of the first integrated circuit die and the surface of the base comprises underfilling therebetween.
4. The method of claim 1, further comprising:
sealing the first integrated circuit die and the second integrated circuit die.
5. The method of claim 4, wherein the step of sealing the first integrated circuit die and the second integrated circuit die comprises:
encapsulating the first integrated circuit die and the second integrated circuit die.
6. The method of claim 1, wherein the steps of providing the first plurality of pads on the base and providing the second plurality of pads on the base comprise one of screen printing and selectively plating the first plurality of pads and the second plurality of pads on the surface of the base.
7. The method of claim 1, wherein the steps of positioning the first integrated circuit die and positioning the second integrated circuit die comprise:
picking and placing the first integrated circuit die and the second integrated circuit die.
8. The method of claim 1, wherein the step of connecting the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the first plurality of pads on the base comprises:
reflow-soldering the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the first plurality of pads on the base.
9. The method of claim 1, further comprising:
testing the connection of the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the first plurality of pads on the base;
determining if the connection is defective; and
repairing the connection when defective.
10. The method of claim 1, wherein the step of attaching the back-side surface of the second integrated circuit die to the back-side surface of the first integrated circuit die comprises:
attaching the back-side surface of the first integrated circuit die and the back-side surface of the second integrated circuit die using an un-cured epoxy; and
curing the un-cured epoxy.
11. The method of claim 1, wherein the step of connecting the at least one bond pad of the plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base comprises:
wire-bonding the at least one bond pad of the second plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base.
12. The method of claim 1, further comprising:
testing the connection of the at least one bond pad of the plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base;
determining if the connection is defective; and
repairing the connection when defective.
13. A method of repairing a flip-chip die connected to a surface of a base having a first plurality of pads and a second plurality of pads on a surface thereof, the flip-chip die having a front-side surface and back-side surface, the front-side surface having at least one flip-chip bump of a plurality of flip-chip bumps thereon bonded to at least one pad of the first plurality of pads on the surface of the base, at least one pad of the first plurality of pads and at least one pad of the second plurality of pads on said surface of said base each connected to at least one conductor of a plurality of conductors for communication between the flip-chip die and circuitry external to the flip-chip die, said method comprising:
attaching a replacement integrated circuit die having a front-side surface and back-side surface to the back-side surface of the flip-chip die, the front-side surface of the replacement integrated circuit die having a plurality of bond pads thereon;
stopping communication between the flip-chip die and the external circuitry connected thereto; and
electrically connecting at least one bond pad of the plurality of bond pads on the front-side surface of the replacement integrated circuit die to at least one pad of the second plurality of pads on the surface of the base for communication between the replacement integrated circuit die and circuitry external to the replacement integrated circuit die.
14. The method of claim 13, wherein the step of providing the second plurality of pads on the surface of the base includes:
connecting at least one pad of the second plurality of pads on the surface of the base to the at least one pad of the first plurality pads of the base.
15. The method of claim 13, wherein stopping communication between the flip-chip connected integrated circuit die and the external circuitry comprises:
disconnecting the first plurality of pads on the surface of the base from the conductors at locations proximal to the pads.
16. A method of making a base for integrated circuit dice, the method comprising:
providing a base having a surface;
providing a first plurality of pads on a surface of the base;
arranging the first plurality of pads on the surface of the base having at least one pad of the first plurality of pads for bonding to at least one flip-chip bump of a plurality of flip-chip bumps on a first integrated circuit die to be located on the surface of the base;
providing a second plurality of pads on the surface of the base;
arranging the second plurality of pads on the surface of the base having at least one pad of the second plurality of pads for bonding to at least one bond pad of a plurality of bond pads on a second integrated circuit die to be located on the first integrated circuit die; and
interconnecting the second plurality of pads and the first plurality of pads.
17. A method of assembling a multi-chip structure on a base comprising:
providing a base having a surface;
forming a first plurality of pads on the surface of the base;
forming a second plurality of pads on the surface of the base;
interconnecting at least one pad of the second plurality of pads and at least one pad of the first plurality of pads;
positioning a first integrated circuit die having a front-side surface having a plurality of flip-chip bumps thereon and having a back-side surface, the front-side surface of the first integrated circuit die facing the surface of the base, at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface aligned with at least one pad of the first plurality of pads on the surface of the base;
connecting the at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die to the at least one pad of the first plurality of pads on the surface of the base;
positioning a second integrated circuit die having a front-side surface having a plurality of bond pads thereon and having a back-side surface, the back-side surface of the second integrated circuit die facing the back-side surface of the first integrated circuit die;
attaching the back-side surface of the second integrated circuit die to the back-side surface of the first integrated circuit die; and
connecting at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die to at least one of the second plurality of pads on the surface of the base.
18. The method of claim 17, further comprising:
sealing a gap between the front-side surface of the first integrated circuit die and the surface of the base.
19. The method of claim 18, wherein the step of sealing the gap between the front-side surface of the first integrated circuit die and the surface of the base comprises:
underfilling the gap.
20. The method of claim 17, further comprising:
sealing the first integrated circuit die and the second integrated circuit die.
21. The method of claim 20, wherein the step of sealing the first integrated circuit die and the second integrated circuit die comprises:
encapsulating the first integrated circuit die and the second integrated circuit die.
22. The method of claim 17, wherein the steps of forming the first plurality of pads and forming the second plurality of pads comprise one of screen printing and selectively plating the first plurality of pads and the second plurality of pads on the surface of the base.
23. The method of claim 17, wherein the steps of positioning the first integrated circuit die and positioning the second integrated circuit die comprise:
picking and placing the first integrated circuit die and the second integrated circuit die.
24. The method of claim 17, wherein the step of connecting the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the plurality of pads on the base comprises reflow-soldering the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the first plurality of pads on the base.
25. The method of claim 17, further comprising:
testing the connection of the at least one flip-chip bump of the plurality of flip-chip bumps on the first integrated circuit die to the at least one pad of the first plurality of pads on the base;
determining if the connection is defective; and
repairing the connection when the connection is defective.
26. The method of claim 17, wherein the step of attaching the back-side surface of the second integrated circuit die to the back-side surface of the first integrated circuit die comprises:
attaching the back-side surface of the first integrated circuit die and the back-side surface of the second integrated circuit die using un-cured epoxy; and
curing the un-cured epoxy.
27. The method of claim 17, wherein the step of connecting the at least one bond pad of the plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base comprises:
wire-bonding the at least one bond pad of the plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base.
28. The method of claim 17, further comprising:
testing the connection of the at least one bond pad of the plurality of bond pads on the second integrated circuit die to the at least one pad of the second plurality of pads on the base;
determining if the connection is defective; and
repairing the connection when the connection is defective.
29. A method of repairing a flip-chip die connected to a surface of a die-carrying base, said method comprising:
providing a flip-chip die having a front-side surface and back-side surface, the front side surface having flip-chip bumps thereon;
providing a base having a surface having a first plurality of pads thereon, the first plurality of pads connected to a plurality of conductors for communication between the flip-chip die and circuitry external to the flip-chip die;
bonding the front-side surface having flip-chip bumps thereon of the flip-chip die to a first plurality of pads on the surface of the base;
forming a second plurality of pads on the surface of the base, at least one pad of the second plurality of pads connected to at least one conductor of the plurality of conductors;
bonding a replacement integrated circuit die having an opposing front-side surface having a plurality of bond pads thereon and back-side surface to the back-side surface of the flip-chip die;
interrupting communication between the flip-chip die and the external circuitry; and
bonding at least one bond pad of the plurality of bond pads on the front-side surface of the replacement integrated circuit die to at least one pad of the second plurality of the surface of the base for communication between the replacement integrated circuit die and the external circuitry.
30. The method of claim 29, wherein the step of forming the second plurality of pads includes connecting at least one pad of the plurality of pads with at least one pad of the first plurality of pads.
31. The method of claim 29, wherein the step of interrupting communication between the flip-chip die and the external circuitry comprises:
disconnecting the at least one pad of the first plurality of pads on the surface of the base from the at least one conductor of the plurality of conductors by cutting the at least one conductor of the plurality of conductors adjacent the at least one pad of the first plurality of pads.
32. A method of making a base having a first plurality of pads on a surface thereof having at least one pad of the first plurality of pads connected to at least one flip-chip bump of a plurality of flip-chip bumps on a first die to be located on the surface of the base, said base used to carry a plurality of integrated circuit dice, the method comprising:
forming a second plurality of pads on the surface of the base so at least one pad of the second plurality of pads;
connecting at least one pad of a plurality of bond pads on a second die to be located on the first die; and
interconnecting at least one pad of the second plurality of pads on the base and at least one pad of the first plurality of pads on the base.
US10/156,976 1996-11-20 2002-05-29 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice Expired - Lifetime US6605489B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US10/156,976 US6605489B2 (en) 1996-11-20 2002-05-29 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US10/634,074 US6869826B2 (en) 1996-11-20 2003-08-04 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/086,144 US7109059B2 (en) 1996-11-20 2005-03-22 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/252,389 US7282792B2 (en) 1996-11-20 2005-10-18 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,970 US7411286B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,969 US7402902B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/602,051 US7423339B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,883 US7423338B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US12/197,514 US7776652B2 (en) 1996-11-20 2008-08-25 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US12/197,453 US7812436B2 (en) 1996-11-20 2008-08-25 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

Applications Claiming Priority (5)

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US08/752,802 US5696031A (en) 1996-11-20 1996-11-20 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US08/914,719 US6071754A (en) 1996-11-20 1997-08-19 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/390,889 US6140149A (en) 1996-02-20 1999-09-07 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/642,134 US6399416B1 (en) 1996-11-20 2000-08-18 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US10/156,976 US6605489B2 (en) 1996-11-20 2002-05-29 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

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US08/752,802 Expired - Lifetime US5696031A (en) 1996-02-20 1996-11-20 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US08/914,515 Expired - Lifetime US5973403A (en) 1996-11-20 1997-08-19 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US08/914,719 Expired - Lifetime US6071754A (en) 1996-02-20 1997-08-19 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/390,889 Expired - Lifetime US6140149A (en) 1996-02-20 1999-09-07 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/642,134 Expired - Lifetime US6399416B1 (en) 1996-11-20 2000-08-18 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US10/156,976 Expired - Lifetime US6605489B2 (en) 1996-11-20 2002-05-29 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US10/634,074 Expired - Fee Related US6869826B2 (en) 1996-11-20 2003-08-04 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/086,144 Expired - Fee Related US7109059B2 (en) 1996-11-20 2005-03-22 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/252,389 Expired - Fee Related US7282792B2 (en) 1996-11-20 2005-10-18 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/602,051 Expired - Fee Related US7423339B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,883 Expired - Fee Related US7423338B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,970 Expired - Fee Related US7411286B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,969 Expired - Fee Related US7402902B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US12/197,453 Expired - Fee Related US7812436B2 (en) 1996-11-20 2008-08-25 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
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US08/914,515 Expired - Lifetime US5973403A (en) 1996-11-20 1997-08-19 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US08/914,719 Expired - Lifetime US6071754A (en) 1996-02-20 1997-08-19 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/390,889 Expired - Lifetime US6140149A (en) 1996-02-20 1999-09-07 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US09/642,134 Expired - Lifetime US6399416B1 (en) 1996-11-20 2000-08-18 Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

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US11/086,144 Expired - Fee Related US7109059B2 (en) 1996-11-20 2005-03-22 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/252,389 Expired - Fee Related US7282792B2 (en) 1996-11-20 2005-10-18 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/602,051 Expired - Fee Related US7423339B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,883 Expired - Fee Related US7423338B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,970 Expired - Fee Related US7411286B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US11/601,969 Expired - Fee Related US7402902B2 (en) 1996-11-20 2006-11-20 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US12/197,453 Expired - Fee Related US7812436B2 (en) 1996-11-20 2008-08-25 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US12/197,514 Expired - Fee Related US7776652B2 (en) 1996-11-20 2008-08-25 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

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US20060033194A1 (en) 2006-02-16
US20070063326A1 (en) 2007-03-22
US6605489B2 (en) 2003-08-12
US6869826B2 (en) 2005-03-22
US20050161796A1 (en) 2005-07-28
US6140149A (en) 2000-10-31
US7282792B2 (en) 2007-10-16
US7423339B2 (en) 2008-09-09
US7776652B2 (en) 2010-08-17
US7411286B2 (en) 2008-08-12
US6071754A (en) 2000-06-06
US20040029315A1 (en) 2004-02-12
US20080315435A1 (en) 2008-12-25
US20070063328A1 (en) 2007-03-22
US6399416B1 (en) 2002-06-04
US20080311702A1 (en) 2008-12-18
US7109059B2 (en) 2006-09-19
US7423338B2 (en) 2008-09-09
US7402902B2 (en) 2008-07-22
US20070063327A1 (en) 2007-03-22
US5973403A (en) 1999-10-26
US7812436B2 (en) 2010-10-12
US5696031A (en) 1997-12-09
US20070063229A1 (en) 2007-03-22

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