US20020130702A1 - Voltage boosting circuit for an integrated circuit device - Google Patents
Voltage boosting circuit for an integrated circuit device Download PDFInfo
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- US20020130702A1 US20020130702A1 US09/877,811 US87781102A US2002130702A1 US 20020130702 A1 US20020130702 A1 US 20020130702A1 US 87781102 A US87781102 A US 87781102A US 2002130702 A1 US2002130702 A1 US 2002130702A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Definitions
- the present invention relates to the field of an integrated circuit device, and more particularly to a voltage boosting circuit for an integrated circuit device.
- Nonvolatile semiconductor memory devices for integrated circuit devices are expected to experience a sharp increase in market demand. That is because such devices (and especially flash memory devices) will be used in portable devices such as cellular phones and personal digital assistants (PDAs).
- PDAs personal digital assistants
- Portable devices are limited by their batteries. To reduce power consumption, portable devices strive to operate on lower power supply voltages. This extends their usage time from a single battery, and results in these devices becoming lighter.
- boosting circuits which use a boosting mechanism to generate a high voltage (hereinafter refer to as boosted voltage).
- One of the challenges is to maintain the boosted voltage uniform, even though the level of the external power supply voltage changes. If the boosted voltage is instead permitted to fluctuate, the applied voltage to MOS transistors also fluctuates. This causes serious problems in operating the integrated circuit device. For example, there may be a malfunction by applying an excessive high voltage. That is because a voltage higher than a breakdown voltage is applied to a p-n junction in the integrated circuit device. Further, there may also be a destruction of an insulation film in the MOS transistors, which would suddenly increase power consumption.
- FIG. 1 a method has been developed to reduce the fluctuation of a boosted voltage, when a power supply voltage is varied.
- the method is proposed in the paper titled “A 2.7V Only 8 Mb'16 NOR Flash Memory” (IEEE 1996 Symposium On VLSI Circuits Digest of Technical Papers, pp. 172-173).
- the voltage boosting circuit of the proposed paper is reproduced in FIG. 1.
- a conventional voltage boosting circuit is constructed of a booster 10 and a control logic 12 .
- the booster 10 includes two inverters 20 and 24 , two capacitors 22 and 26 , and a PMOS transistor 28 , connected as shown in FIG. 1.
- the booster 10 generates a boosted voltage VPP higher than a power supply voltage VCC, in response to a low-to-high transition of a control signal.
- the control logic 12 determines the number of capacitors to be used in the booster 10 by an alternative selection of inverters 20 and 24 in the booster 10 .
- a voltage level of the control signal Vcdet can be determined by a voltage divider (not shown), for dividing the boosted voltage VPP.
- the control logic 12 disables one of inverters 20 and 24 used in the booster 10 . Namely, the booster 10 operates by using one capacitor, and therefore the VPP is decreased by about a half. If the VPP becomes low, the control logic 12 enables a disabled inverter. The booster 10 then operates by using the two capacitors 22 , 26 , and therefore the VPP becomes high again.
- FIG. 2 is a graph showing a relation of fluctuation of the power supply voltage and variation of boosted voltage in a conventional voltage boosting circuit.
- the control logic 12 is designed to use both capacitors 22 and 26 of the booster 10 .
- the boosted voltage VPP from the booster 10 is positioned between VPP1 and VPP2 by a boosting operation using a couple of capacitors.
- the control logic 12 is designed to use one of capacitors 22 and 26 of the booster 10 .
- the boosted voltage VPP is positioned between VPP2 and VPP1 by a boosting operation using one capacitor.
- FIG. 2 is a graph VPP( 10 ), which shows a boosted voltage VPP having wide variations depending on variations in the power supply voltage VCC. It means that an integrated circuit device (which receives VPP as its power supply) has an unstable operation.
- the object of the present invention is to provide a voltage boosting circuit for an integrated circuit which outputs a boosted voltage with reduced fluctuations as a result of variations in the power supply voltage.
- the voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit.
- the booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal.
- the voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit.
- the voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage.
- the pulse generator generates a pulse signal responsive to the detected voltage signal.
- the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.
- FIG. 1 is a circuit diagram showing a voltage boosting circuit in the prior art
- FIG. 2 is a graph showing how the boosted voltage of the circuit of FIG. 1 fluctuates if there is a variation in the power supply voltage
- FIG. 3 is a block diagram of a voltage boosting circuit for an integrated circuit according to an embodiment of the present invention.
- FIG. 4 is a circuit diagram showing the preferred embodiment of the voltage boosting circuit of FIG. 3;
- FIG. 5 is a diagram illustrating waveforms of signals and voltages in the voltage boosting circuit of FIG. 4.
- FIG. 6 is a graph showing how the boosted voltage of the circuit of FIG. 4 fluctuates if there is a variation in the power supply voltage.
- FIGS. 3 - 6 a preferred embodiment of the present invention is described.
- FIG. 3 is a block diagram showing a voltage boosting circuit of an integrated circuit device in accordance with the present invention.
- a voltage boosting circuit 100 includes booster 110 and voltage clamp circuit 120 , which is also known as voltage stabilizer.
- the booster 110 operates in response to a boosting control signal PBST. It generates a boosted voltage VPP, which is higher than the externally the power supply voltage VCC, which is also called first supply voltage.
- the power supply voltage VCC is typically the one provided by the battery in a portable device.
- the booster 110 operates by using the first supply voltage VCC, and a second supply voltage lower than the VCC.
- the second supply voltage can be the ground voltage GND.
- the voltage clamp circuit 120 is connected to the VPP generated from the booster 110 .
- the voltage clamp circuit 120 clamps the VPP to a desired level in response to the boosting control signal PBST.
- the voltage clamp circuit 120 is constructed of a voltage detector 122 , a pulse generator 124 , and a discharge circuit 126 .
- the voltage detector 122 is connected so as to receive the boosted voltage VPP.
- the voltage detector 122 When the boosted voltage VPP is over a first predetermined threshold voltage, the voltage detector 122 generates a detected voltage signal VDET.
- Signal VDET has a voltage level representing an attribute of the boosted voltage.
- the attribute is a deviation of the instantaneous boosted voltage VPP from a desired preset voltage VPPd. Accordingly, the signal may have a magnitude proportional to that deviation.
- the pulse generator 124 generates a pulse signal PL, which is high (“activated”) while the voltage level of the VDET is higher than the predetermined threshold voltage. Pulse signal PL is input in the discharge circuit 126 .
- the discharge circuit 126 discharges to decrease gradually the VPP while the pulse signal from the pulse generator 124 is activated.
- the detected voltage signal VDET While the boosted voltage VPP is being gradually decreased, the detected voltage signal VDET is also being decreased commensurately. When the gradually decreasing boosted voltage VPP attains the desired level, the detected voltage signal VDET becomes such that the pulse signal PL is no longer generated. Thus, the discharge circuit 126 is disabled, and it stops discharging of the VPP. Thus the boosted voltage VPP becomes stable at the desired level.
- FIG. 4 shows a preferred embodiment of the voltage boosting circuit 100 according to the present invention.
- the components 110 , 122 , 124 , 126 are identifiable from FIG. 3.
- the booster 110 is proposed by “Quick Double Bootstrapping Scheme for Word Line of 1.8V Only 16 Mb Flash Memory” (The 6th Korean Conference for Semiconductor, February 1999 ). It includes inverters 406 , 414 , and 426 , PMOS transistors 408 , 416 , and 428 , NMOS transistors 410 and 424 , depletion-typed MOS transistors 418 and 430 , and capacitors 412 and 422 .
- the transistors 418 and 430 are designed to withstand high voltage.
- the voltage detector 122 includes an inverter 432 , a PMOS transistor 434 , and voltage divider 438 .
- the inverter 432 is supplied with the VPP as an operating voltage, and receives the boosting control signal PBST.
- the PMOS transistor 434 has a source connected for receiving the boosted voltage VPP and a drain connected to the voltage divider 438 . It also has a gate connected to the inverter 432 , for being turned on or off by the boosting control signal PBST.
- the voltage divider 438 is composed of three NMOS transistors 440 , 442 , and 444 , and a resistor 446 .
- the transistors 434 , 440 , 442 , and 444 are designed to be adapted to high voltage, and are connected so as to operate the NMOS transistors as diodes. Their current paths are connected between the drain of the PMOS transistor 434 and a node A.
- the PMOS transistor 434 When the boosting control signal PBST goes from a low level to a high level, the PMOS transistor 434 is turned on. As a result, the boosted voltage VPP is applied to the voltage detector 122 through the PMOS transistor 434 . If the VPP is lower than a voltage corresponding to sum of threshold voltages of the diode-connected NMOS transistors 440 , 442 , and 444 , then a current path through them is not turned on. On the other hand, if the VPP is higher than a voltage corresponding to sum of threshold voltages of the diode-connected NMOS transistors, the current path of the diode-connected NMOS transistors is turned on.
- a voltage at node A is a function of the VPP, by operation of the resistor 446 .
- the VPP is divided by the voltage divider 438 , and thereby the divided voltage VDET is provided as a detected value of VPP level to the pulse generator 124 .
- the pulse generator 124 includes at least one inverter. In the embodiment of FIG. 4, it includes a first inverter and a second inverter. These are formed as follows.
- the pulse generator 124 includes a resistor 452 , two PMOS transistors 454 and 462 , and two NMOS transistor 456 and 464 .
- the resistor 452 and transistors 454 and 456 compose the first inverter circuit, having an output terminal B.
- a current path of the resistor 452 , the PMOS transistor 454 , and the NMOS transistor 456 is connected between the power supply voltage VCC and the ground voltage GND in series. Both transistors 454 and 456 are controlled by the detected voltage signal VDET.
- the transistors 462 and 464 compose the second inverter circuit, having an output terminal C.
- a current path of the PMOS transistor 462 and the NMOS transistor 464 is connected between the VCC and the GND in series, and gates of the transistors 462 and 464 is commonly connected to output terminal B of the first inverter circuit.
- a logical threshold voltage (or triggering voltage) of the inverter circuit is accomplished by providing the VCC through the resistor 452 .
- a conductivity of a pull-up transistor (PMOS transistor) which connects the output terminal B with the power supply voltage VCC becomes low
- the logical threshold voltage of the first inverter circuit becomes lower than before.
- a conductivity of a pull-down transistor (NMOS transistor) which connects the output terminal B with the ground voltage GND becomes low
- the logical threshold voltage of the inverter circuit becomes higher.
- the resistor 452 is inserted at the pull-up terminal side, the logical threshold voltage of the inverter circuit becomes low, and thereby reduces fluctuation of the logical threshold voltage affected by variation of the VCC. More particularly, fluctuation of desired boosted voltage becomes reduced. Inserting a resistor at the pull-down terminal side can raise the logical threshold voltage of the inverter circuit.
- the second inverter circuit generates a pulse signal PL at node C, by inverting the output signal generated at node B from the first inverter circuit.
- the node A has a voltage level between that of the power supply voltage VCC and the ground voltage GND. Therefore, the output signal from the terminal B has a voltage level also between a high-leveled VCC and a low-leveled GND.
- the second inverter circuit prevents a possible instability of the voltage at node B from affecting the output.
- the discharge circuit 126 is composed of a NMOS transistor 468 having a current path formed between the VPP and the GND, and a gate connected so as to receive the pulse signal PL generated at node C of the pulse generator 124 .
- the transistor 468 is designed to withstand a high voltage.
- the discharge circuit 126 is turned on during an activation period of the pulse signal PL, and therefore the boosted voltage VPP is discharged while the discharge circuit 126 is turned on.
- FIG. 5 is a diagram illustrating waveforms of signals and voltages in the voltage boosting circuit of FIG. 4. Referring to the FIG. 5, the operation of the voltage boosting circuit will be described below.
- the boosting control signal PBST goes from a low level to a high level
- the booster 110 generates a boosted voltage VPP voltage, which may have a level Vpeak.
- the voltage detector 122 receives the Vpeak from the booster 110 in response to the PBST having a low-to-high transition.
- Level Vpeak may be higher than a desired boosted voltage VPPd. If that happens, then by proper design the inputted voltage of the voltage detector 122 is higher than the sum of the threshold voltages of NMOS transistors 440 , 442 , and 444 in the voltage divider 438 . Then the voltage detector 122 generates a detected voltage signal VDET having a voltage level determined by the input voltage VPP. Then, the pulse signal PL goes from a low level to a high level when the detected voltage signal VDET is over a logical threshold voltage VLT1 of the first inverter circuit 452 , 454 , and 456 corresponding to the low-to-high transition. The NMOS transistor 468 of the discharge circuit 126 is turned on by the pulse signal having a low-to-high transition, and thereby the boosted voltage VPP from the booster 110 becomes gradually low.
- VPP from the booster 110 is decreased down to the desired boosted voltage level VPPd, it is prevented from being reduced further. This takes place as follows.
- the detected voltage signal VDET at the node A is also being gradually and commensurately decreased. Then, the signal VDET crosses a logical threshold voltage VLT2 of the first inverter circuit 452 , 454 , and 456 in the pulse generator 124 corresponding to a high-to-low transition. Thus, the voltage at node B starts to increase gradually from the ground voltage GND. After a short while, the pulse signal PL from the node C goes from a high level of the power supply voltage VCC to a low level of the ground voltage GND. This causes the discharge circuit 126 to stop discharging. Thus, the VPP from the booster 110 is maintained to the desired boosting voltage VPPd.
- the voltage clamp circuit 120 helps the VPP reach equilibrium fast.
- the maximum voltage Vpeak or an initial voltage of the booster 110 can be reduced to be near the VPPd in less than about 21 nsec.
- FIG. 6 is a graph comparing the performance of the invention [line VPP( 100 )] with that of the prior art [line VP( 10 ), repeated from FIG. 2]. It will be observed that line VP( 100 ) is a lot smoother than line VP( 10 ), as a result of the voltage clamp circuit 120 of the present invention. Indeed, VPP( 100 ) varies from 5.31V to 5.67V, while VPP( 10 ) varies between 4.80V and 5.67V.
- the power supply voltage VCC assumes the values of 2.5V, 3V, 3.3V, 3.5V, 3.8V, and 4V.
- the one capacitor used in the booster 100 of the present invention occupies 6,498 mm2 of the voltage boosting circuit, which is exactly the same topological size as the capacitors 22 and 26 used in the prior art booster 10 of FIG. 1 (2*3,249 mm2).
- detecting the boosted voltage from the booster and discharging the boosted voltage in accordance with the detected voltage can be minimize the fluctuation of the boosted voltage affected by variation of the power supply voltage.
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Abstract
A voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.
Description
- This application claims the priority benefit of Korean Patent Application No. 2000-69982, filed on Nov. 23, 2000, the contents of which are herein incorporated by reference in their entirety.
- The present invention relates to the field of an integrated circuit device, and more particularly to a voltage boosting circuit for an integrated circuit device.
- Nonvolatile semiconductor memory devices for integrated circuit devices are expected to experience a sharp increase in market demand. That is because such devices (and especially flash memory devices) will be used in portable devices such as cellular phones and personal digital assistants (PDAs).
- Portable devices are limited by their batteries. To reduce power consumption, portable devices strive to operate on lower power supply voltages. This extends their usage time from a single battery, and results in these devices becoming lighter.
- While the available power supply voltages are becoming lower, the integrated circuit devices compensate for this by generating higher voltages internally. This is accomplished by boosting circuits, which use a boosting mechanism to generate a high voltage (hereinafter refer to as boosted voltage).
- One of the challenges is to maintain the boosted voltage uniform, even though the level of the external power supply voltage changes. If the boosted voltage is instead permitted to fluctuate, the applied voltage to MOS transistors also fluctuates. This causes serious problems in operating the integrated circuit device. For example, there may be a malfunction by applying an excessive high voltage. That is because a voltage higher than a breakdown voltage is applied to a p-n junction in the integrated circuit device. Further, there may also be a destruction of an insulation film in the MOS transistors, which would suddenly increase power consumption.
- Referring now to FIG. 1, a method has been developed to reduce the fluctuation of a boosted voltage, when a power supply voltage is varied. The method is proposed in the paper titled “A 2.7V Only 8 Mb'16 NOR Flash Memory” (IEEE 1996 Symposium On VLSI Circuits Digest of Technical Papers, pp. 172-173). The voltage boosting circuit of the proposed paper is reproduced in FIG. 1.
- Referring to FIG. 1, the essence of the method is to control the number of capacitors used in the boosting mechanism. A conventional voltage boosting circuit is constructed of a
booster 10 and acontrol logic 12. Thebooster 10 includes twoinverters capacitors - The
booster 10 generates a boosted voltage VPP higher than a power supply voltage VCC, in response to a low-to-high transition of a control signal. According to a control signal Vcdet, thecontrol logic 12 determines the number of capacitors to be used in thebooster 10 by an alternative selection ofinverters booster 10. A voltage level of the control signal Vcdet can be determined by a voltage divider (not shown), for dividing the boosted voltage VPP. - If the voltage level of the control signal Vcdet rises in accordance with an increase of the boosted voltage VPP, the
control logic 12 disables one ofinverters booster 10. Namely, thebooster 10 operates by using one capacitor, and therefore the VPP is decreased by about a half. If the VPP becomes low, thecontrol logic 12 enables a disabled inverter. Thebooster 10 then operates by using the twocapacitors - FIG. 2 is a graph showing a relation of fluctuation of the power supply voltage and variation of boosted voltage in a conventional voltage boosting circuit. If the power supply voltage is positioned between VCC1 and VCC2, the
control logic 12 is designed to use bothcapacitors booster 10. In this case, the boosted voltage VPP from thebooster 10 is positioned between VPP1 and VPP2 by a boosting operation using a couple of capacitors. If the power supply voltage is leveled between VCC2 and VCC3, thecontrol logic 12 is designed to use one ofcapacitors booster 10. In this case, the boosted voltage VPP is positioned between VPP2 and VPP1 by a boosting operation using one capacitor. - FIG. 2 is a graph VPP(10), which shows a boosted voltage VPP having wide variations depending on variations in the power supply voltage VCC. It means that an integrated circuit device (which receives VPP as its power supply) has an unstable operation.
- Therefore, to ensure a stable operation, there exists a need for a voltage boosting circuit that fluctuates very little due to variations in the power supply voltage.
- The object of the present invention is to provide a voltage boosting circuit for an integrated circuit which outputs a boosted voltage with reduced fluctuations as a result of variations in the power supply voltage.
- According to an aspect of the present invention, the voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.
- The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein:
- FIG. 1 is a circuit diagram showing a voltage boosting circuit in the prior art;
- FIG. 2 is a graph showing how the boosted voltage of the circuit of FIG. 1 fluctuates if there is a variation in the power supply voltage;
- FIG. 3 is a block diagram of a voltage boosting circuit for an integrated circuit according to an embodiment of the present invention;
- FIG. 4 is a circuit diagram showing the preferred embodiment of the voltage boosting circuit of FIG. 3;
- FIG. 5 is a diagram illustrating waveforms of signals and voltages in the voltage boosting circuit of FIG. 4; and
- FIG. 6 is a graph showing how the boosted voltage of the circuit of FIG. 4 fluctuates if there is a variation in the power supply voltage.
- Referring now to FIGS.3-6, a preferred embodiment of the present invention is described.
- FIG. 3 is a block diagram showing a voltage boosting circuit of an integrated circuit device in accordance with the present invention. A
voltage boosting circuit 100 includesbooster 110 andvoltage clamp circuit 120, which is also known as voltage stabilizer. - The
booster 110 operates in response to a boosting control signal PBST. It generates a boosted voltage VPP, which is higher than the externally the power supply voltage VCC, which is also called first supply voltage. The power supply voltage VCC is typically the one provided by the battery in a portable device. Thebooster 110 operates by using the first supply voltage VCC, and a second supply voltage lower than the VCC. The second supply voltage can be the ground voltage GND. - The
voltage clamp circuit 120 is connected to the VPP generated from thebooster 110. Thevoltage clamp circuit 120 clamps the VPP to a desired level in response to the boosting control signal PBST. - The
voltage clamp circuit 120 is constructed of avoltage detector 122, apulse generator 124, and adischarge circuit 126. - The
voltage detector 122 is connected so as to receive the boosted voltage VPP. When the boosted voltage VPP is over a first predetermined threshold voltage, thevoltage detector 122 generates a detected voltage signal VDET. Signal VDET has a voltage level representing an attribute of the boosted voltage. In the preferred embodiment, the attribute is a deviation of the instantaneous boosted voltage VPP from a desired preset voltage VPPd. Accordingly, the signal may have a magnitude proportional to that deviation. - The
pulse generator 124 generates a pulse signal PL, which is high (“activated”) while the voltage level of the VDET is higher than the predetermined threshold voltage. Pulse signal PL is input in thedischarge circuit 126. - The
discharge circuit 126 discharges to decrease gradually the VPP while the pulse signal from thepulse generator 124 is activated. - While the boosted voltage VPP is being gradually decreased, the detected voltage signal VDET is also being decreased commensurately. When the gradually decreasing boosted voltage VPP attains the desired level, the detected voltage signal VDET becomes such that the pulse signal PL is no longer generated. Thus, the
discharge circuit 126 is disabled, and it stops discharging of the VPP. Thus the boosted voltage VPP becomes stable at the desired level. - FIG. 4 shows a preferred embodiment of the
voltage boosting circuit 100 according to the present invention. Thecomponents - The
booster 110 is proposed by “Quick Double Bootstrapping Scheme for Word Line of 1.8V Only 16 Mb Flash Memory” (The 6th Korean Conference for Semiconductor, February 1999). It includesinverters PMOS transistors NMOS transistors MOS transistors capacitors transistors - The
voltage detector 122 includes aninverter 432, aPMOS transistor 434, andvoltage divider 438. Theinverter 432 is supplied with the VPP as an operating voltage, and receives the boosting control signal PBST. - The
PMOS transistor 434 has a source connected for receiving the boosted voltage VPP and a drain connected to thevoltage divider 438. It also has a gate connected to theinverter 432, for being turned on or off by the boosting control signal PBST. - The
voltage divider 438 is composed of threeNMOS transistors resistor 446. Thetransistors PMOS transistor 434 and a node A. - When the boosting control signal PBST goes from a low level to a high level, the
PMOS transistor 434 is turned on. As a result, the boosted voltage VPP is applied to thevoltage detector 122 through thePMOS transistor 434. If the VPP is lower than a voltage corresponding to sum of threshold voltages of the diode-connectedNMOS transistors resistor 446. Namely, the VPP is divided by thevoltage divider 438, and thereby the divided voltage VDET is provided as a detected value of VPP level to thepulse generator 124. - The
pulse generator 124 includes at least one inverter. In the embodiment of FIG. 4, it includes a first inverter and a second inverter. These are formed as follows. - The
pulse generator 124 includes aresistor 452, twoPMOS transistors NMOS transistor resistor 452 andtransistors resistor 452, thePMOS transistor 454, and theNMOS transistor 456 is connected between the power supply voltage VCC and the ground voltage GND in series. Bothtransistors - The
transistors PMOS transistor 462 and theNMOS transistor 464 is connected between the VCC and the GND in series, and gates of thetransistors - In the first inverter circuit, a logical threshold voltage (or triggering voltage) of the inverter circuit is accomplished by providing the VCC through the
resistor 452. As a conductivity of a pull-up transistor (PMOS transistor), which connects the output terminal B with the power supply voltage VCC becomes low, the logical threshold voltage of the first inverter circuit becomes lower than before. On the other hand, as a conductivity of a pull-down transistor (NMOS transistor), which connects the output terminal B with the ground voltage GND becomes low, the logical threshold voltage of the inverter circuit becomes higher. If theresistor 452 is inserted at the pull-up terminal side, the logical threshold voltage of the inverter circuit becomes low, and thereby reduces fluctuation of the logical threshold voltage affected by variation of the VCC. More particularly, fluctuation of desired boosted voltage becomes reduced. Inserting a resistor at the pull-down terminal side can raise the logical threshold voltage of the inverter circuit. - The second inverter circuit generates a pulse signal PL at node C, by inverting the output signal generated at node B from the first inverter circuit. When the boosted voltage VPP from the
booster 110 is completely stable, the node A has a voltage level between that of the power supply voltage VCC and the ground voltage GND. Therefore, the output signal from the terminal B has a voltage level also between a high-leveled VCC and a low-leveled GND. The second inverter circuit prevents a possible instability of the voltage at node B from affecting the output. - The
discharge circuit 126 is composed of aNMOS transistor 468 having a current path formed between the VPP and the GND, and a gate connected so as to receive the pulse signal PL generated at node C of thepulse generator 124. Thetransistor 468 is designed to withstand a high voltage. Thedischarge circuit 126 is turned on during an activation period of the pulse signal PL, and therefore the boosted voltage VPP is discharged while thedischarge circuit 126 is turned on. - FIG. 5 is a diagram illustrating waveforms of signals and voltages in the voltage boosting circuit of FIG. 4. Referring to the FIG. 5, the operation of the voltage boosting circuit will be described below. When the boosting control signal PBST goes from a low level to a high level, the
booster 110 generates a boosted voltage VPP voltage, which may have a level Vpeak. Simultaneously, thevoltage detector 122 receives the Vpeak from thebooster 110 in response to the PBST having a low-to-high transition. - Level Vpeak may be higher than a desired boosted voltage VPPd. If that happens, then by proper design the inputted voltage of the
voltage detector 122 is higher than the sum of the threshold voltages ofNMOS transistors voltage divider 438. Then thevoltage detector 122 generates a detected voltage signal VDET having a voltage level determined by the input voltage VPP. Then, the pulse signal PL goes from a low level to a high level when the detected voltage signal VDET is over a logical threshold voltage VLT1 of thefirst inverter circuit NMOS transistor 468 of thedischarge circuit 126 is turned on by the pulse signal having a low-to-high transition, and thereby the boosted voltage VPP from thebooster 110 becomes gradually low. - When the VPP from the
booster 110 is decreased down to the desired boosted voltage level VPPd, it is prevented from being reduced further. This takes place as follows. - As the VPP is approaching the VPPd level, the detected voltage signal VDET at the node A is also being gradually and commensurately decreased. Then, the signal VDET crosses a logical threshold voltage VLT2 of the
first inverter circuit pulse generator 124 corresponding to a high-to-low transition. Thus, the voltage at node B starts to increase gradually from the ground voltage GND. After a short while, the pulse signal PL from the node C goes from a high level of the power supply voltage VCC to a low level of the ground voltage GND. This causes thedischarge circuit 126 to stop discharging. Thus, the VPP from thebooster 110 is maintained to the desired boosting voltage VPPd. - As an additional advantage, the
voltage clamp circuit 120 helps the VPP reach equilibrium fast. The maximum voltage Vpeak or an initial voltage of thebooster 110 can be reduced to be near the VPPd in less than about 21 nsec. - FIG. 6 is a graph comparing the performance of the invention [line VPP(100)] with that of the prior art [line VP(10), repeated from FIG. 2]. It will be observed that line VP(100) is a lot smoother than line VP(10), as a result of the
voltage clamp circuit 120 of the present invention. Indeed, VPP(100) varies from 5.31V to 5.67V, while VPP(10) varies between 4.80V and 5.67V. - For FIG. 6, the power supply voltage VCC assumes the values of 2.5V, 3V, 3.3V, 3.5V, 3.8V, and 4V. The one capacitor used in the
booster 100 of the present invention occupies 6,498 mm2 of the voltage boosting circuit, which is exactly the same topological size as thecapacitors prior art booster 10 of FIG. 1 (2*3,249 mm2). - According to the present invention, detecting the boosted voltage from the booster and discharging the boosted voltage in accordance with the detected voltage can be minimize the fluctuation of the boosted voltage affected by variation of the power supply voltage.
Claims (10)
1. A voltage boosting circuit for an integrated circuit, comprising:
a booster for generating a boosted voltage higher than a first supply voltage by using a first supply voltage and a second supply voltage lower than the first supply voltage, in response to a boosting control signal;
a voltage detector for generating a detected voltage signal representing an attribute of the boosted voltage, in response to the boosting control signal;
a pulse generator for generating a pulse signal responsive to a voltage level of the detected voltage signal; and
a discharge circuit for providing a current path so as to discharge the boosted voltage during an activation period of the pulse signal.
2. The circuit of claim 1 , wherein the voltage detector senses a level of the boosted voltage.
3. The circuit of claim 1 , wherein the attribute is a deviation of the instantaneous boosted voltage from a desired preset voltage.
4. The circuit of claim 1 , wherein the voltage detector includes:
an inverter for inverting the boosting control signal;
a switch transistor having a first terminal connected to receive the boosted voltage, a gate terminal connected to receive an output signal from the inverter and a third terminal; and
a voltage divider connected between the third terminal of the switch transistor and the second supply voltage.
5. The circuit of claim 4 , wherein the inverter is operated from the boosted voltage.
6. The circuit of claim 4 , wherein the voltage divider includes:
a plurality of diode-connected transistors connected in series between the boosted voltage and an output terminal of the voltage divider; and
a resistor connected between the output terminal of the voltage divider and the second supply voltage.
7. The circuit of claim 6 , wherein the diode-connected transistors are formed of enhancement-type MOS transistors.
8. The circuit of claim 1 , wherein the pulse generator includes an inverter connected between the voltage detector and the discharge circuit.
9. The circuit of claim 1 , wherein
the pulse generator includes first and second inverters connected successively between the voltage detector and the discharge circuit in series, and
the first inverter receives the first supply voltage through a resistor.
10. The circuit of claim 1 , wherein the discharge circuit is formed of a NMOS transistor.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2000-69982 | 2000-11-23 | ||
KR1020000069982A KR100352907B1 (en) | 2000-11-23 | 2000-11-23 | Voltage boosting circuit for use in an integrated circuit device |
Publications (1)
Publication Number | Publication Date |
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US20020130702A1 true US20020130702A1 (en) | 2002-09-19 |
Family
ID=19700895
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/877,811 Expired - Fee Related US6590442B2 (en) | 2000-11-23 | 2001-10-11 | Voltage boosting circuit for an integrated circuit device |
US09/877,811 Granted US20020130702A1 (en) | 2000-11-23 | 2002-01-22 | Voltage boosting circuit for an integrated circuit device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/877,811 Expired - Fee Related US6590442B2 (en) | 2000-11-23 | 2001-10-11 | Voltage boosting circuit for an integrated circuit device |
Country Status (4)
Country | Link |
---|---|
US (2) | US6590442B2 (en) |
JP (1) | JP4485720B2 (en) |
KR (1) | KR100352907B1 (en) |
DE (1) | DE10155691A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040130382A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuit |
US20040130381A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuits |
US20040130383A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuits |
US20060170484A1 (en) * | 2005-01-31 | 2006-08-03 | Jong Ho Son | Semiconductor device |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7012456B1 (en) * | 2001-12-20 | 2006-03-14 | Cypress Semiconductor Corporation | Circuit and method for discharging high voltage signals |
JP4274786B2 (en) * | 2002-12-12 | 2009-06-10 | パナソニック株式会社 | Voltage generation circuit |
US20040207459A1 (en) * | 2003-03-07 | 2004-10-21 | Synqor, Inc. | Charge pump bypass |
KR20050041592A (en) * | 2003-10-31 | 2005-05-04 | 주식회사 하이닉스반도체 | Internal voltage generation device capable of temperature compensation |
DE102004053144B4 (en) * | 2004-11-03 | 2011-05-19 | Infineon Technologies Ag | Boost converter with improved dynamic behavior |
KR100772705B1 (en) * | 2005-09-29 | 2007-11-02 | 주식회사 하이닉스반도체 | Internal voltage generator |
KR100681880B1 (en) * | 2006-02-21 | 2007-02-15 | 주식회사 하이닉스반도체 | High voltage generator |
US20080012627A1 (en) * | 2006-07-13 | 2008-01-17 | Yosuke Kato | System and method for low voltage booster circuits |
US7760004B2 (en) * | 2008-10-30 | 2010-07-20 | Analog Devices, Inc. | Clamp networks to insure operation of integrated circuit chips |
US11606023B2 (en) * | 2020-10-08 | 2023-03-14 | Winbond Electronics Corp. | Discharge device for discharging internal power of electronic device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4130191C2 (en) * | 1991-09-30 | 1993-10-21 | Samsung Electronics Co Ltd | Constant voltage generator for a semiconductor device with cascaded charging or discharging circuit |
US5530640A (en) * | 1992-10-13 | 1996-06-25 | Mitsubishi Denki Kabushiki Kaisha | IC substrate and boosted voltage generation circuits |
JP3420606B2 (en) * | 1993-03-15 | 2003-06-30 | 株式会社東芝 | High voltage generator |
KR100293449B1 (en) * | 1998-05-04 | 2001-07-12 | 김영환 | High voltage generating circuit for a semiconductor memory circuit |
-
2000
- 2000-11-23 KR KR1020000069982A patent/KR100352907B1/en not_active IP Right Cessation
-
2001
- 2001-10-11 US US09/877,811 patent/US6590442B2/en not_active Expired - Fee Related
- 2001-10-23 JP JP2001325087A patent/JP4485720B2/en not_active Expired - Fee Related
- 2001-11-07 DE DE10155691A patent/DE10155691A1/en not_active Withdrawn
-
2002
- 2002-01-22 US US09/877,811 patent/US20020130702A1/en active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040130382A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuit |
US20040130381A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuits |
US20040130383A1 (en) * | 2003-01-06 | 2004-07-08 | Du Xiao Hong | CMOS voltage booster circuits |
US6864738B2 (en) * | 2003-01-06 | 2005-03-08 | Texas Instruments Incorporated | CMOS voltage booster circuits |
US6909318B2 (en) * | 2003-01-06 | 2005-06-21 | Texas Instruments Incorporated | CMOS voltage booster circuit |
US7233194B2 (en) * | 2003-01-06 | 2007-06-19 | Texas Instruments Incorporated | CMOS voltage booster circuits |
US20060170484A1 (en) * | 2005-01-31 | 2006-08-03 | Jong Ho Son | Semiconductor device |
US7250799B2 (en) * | 2005-01-31 | 2007-07-31 | Hynix Semiconductor Inc. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
DE10155691A1 (en) | 2002-08-14 |
KR20020040068A (en) | 2002-05-30 |
US6590442B2 (en) | 2003-07-08 |
JP4485720B2 (en) | 2010-06-23 |
JP2002199703A (en) | 2002-07-12 |
KR100352907B1 (en) | 2002-09-16 |
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