US20020108930A1 - Apparatus for removing native oxide layers from silicon wafers - Google Patents
Apparatus for removing native oxide layers from silicon wafers Download PDFInfo
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- US20020108930A1 US20020108930A1 US10/115,666 US11566602A US2002108930A1 US 20020108930 A1 US20020108930 A1 US 20020108930A1 US 11566602 A US11566602 A US 11566602A US 2002108930 A1 US2002108930 A1 US 2002108930A1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 48
- 239000010703 silicon Substances 0.000 title claims abstract description 48
- 235000012431 wafers Nutrition 0.000 title description 40
- 238000000034 method Methods 0.000 claims abstract description 52
- 230000005855 radiation Effects 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910002804 graphite Inorganic materials 0.000 claims description 8
- 239000010439 graphite Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 239000010453 quartz Substances 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 description 30
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000005108 dry cleaning Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 230000005802 health problem Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000003319 supportive effect Effects 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 231100000331 toxic Toxicity 0.000 description 1
- 230000002588 toxic effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B7/00—Cleaning by methods not provided for in a single other subclass or a single group in this subclass
- B08B7/0035—Cleaning by methods not provided for in a single other subclass or a single group in this subclass by radiant energy, e.g. UV, laser, light beam or the like
- B08B7/0057—Cleaning by methods not provided for in a single other subclass or a single group in this subclass by radiant energy, e.g. UV, laser, light beam or the like by ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Definitions
- the present invention relates to a method and apparatus for selectively removing native oxide layers from silicon wafers without significantly affecting the underlying silicon, or without significantly removing other materials, such as polysilicon or thermal oxide depositions, that may be thereon.
- Such a process is of substantial importance to the semiconductor industry since the selective removal of native oxide from silicon wafers is among the most frequently performed processes in fabricating silicon semiconductor devices.
- a native oxide layer tends to form on the silicon wafer.
- Such native oxide layers would deleteriously affect the subsequent processing steps performed on the silicon wafer, and therefore must be cleanly and quickly removed without disturbing other depositions, such as, polysilicon or thermal oxide depositions, on the silicon wafer.
- a dry cleaning process is more effective and less damaging to the silicon surface than a wet cleaning process.
- Narita U.S. Pat. No. 4,985,372 describes a dry cleaning process wherein the silicon wafer surface is exposed to an echant gas including NF 3 and H 2 , or N 2 in place of the H 2 .
- the process described in that patent requires the generation of a plasma in the chamber at the time the wafer is exposed to the etchant gas.
- An object of the present invention is to provide a method for selectively removing a native oxide layer from a silicon wafer having advantages over the above-described methods known in the prior art.
- Another object of the invention is to provide apparatus for removing native oxide layers in accordance with the novel method.
- a method of selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on comprising exposing the silicon wafer to an etchant gas including NF 3 while simultaneously exposing the wafer to ultraviolet radiation and heating the wafer to a temperature of 100-400° C.
- the process should be performed at a temperature of 250-350° C., particularly good results having been obtained at a temperature of about 300° C.
- elevating the process temperature as described above substantially increases the removal rate of the native oxide without losing the selectivity achieved at room temperature until the higher end of above-described temperature range is reached At higher temperatures, the native oxide removal rate may increase further, but it was found that selectivity is lost.
- the etchant gas also includes N 2
- the example described below includes N 2 in approximately equal proportions by volume as the NF 3 .
- the partial pressure of the etchant gas is preferably within the moderate pressure range, of 10-300 Torr.
- the higher partial pressures would be expected to produce faster reaction rates, but would result in a number of disadvantages.
- higher pressures in the reactor increase the danger of leakage of NF 3 from the reactor to the atmosphere, which can cause a serious health problem since NF 3 is highly toxic.
- a high pressure in the reactor increases the danger of particles depositing on the silicon wafer being treated which will cause problems in subsequent processing of the wafer.
- a higher pressure in the reactor increases the wafer processing time in single-wafer processing apparatus, since the NF 3 must be completely removed from the chamber prior to transferring the wafer to the next process module.
- a low process pressure saves time by requiring less pump down time at the end of the process, and less time for pressure and flow stabilization at the beginning of the process.
- the pressure should be below 100 Torr. optimally about 30-60 Torr.
- the partial pressure of the NF 3 was 30 Torr and the partial pressure of the N 2 was 30 Torr.
- apparatus for removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on comprising a heating chamber including a supporting member for supporting the wafer from which the native oxide layer is to be selectively removed; a heater for heating a wafer on the supportive member to a temperature of 100-400° C.; a gas supply for introducing into the chamber an etchant gas including NF 3 ; and an ultraviolet source for irradiating the water with ultraviolet radiation while the wafer is exposed to the etchant gas and is heated to the temperature of 100-400° C.
- FIG. 1 is a side view illustrating one form of apparatus constructed in accordance with the present invention
- FIG. 2 is an axial view of the apparatus of FIG. 1;
- FIG. 3 sets forth the results a number of experiments in selectively removing native oxide layers from a silicon wafer in accordance with the present invention.
- FIGS. 1 and 2 schematically illustrate one form of apparatus constructed in accordance with the present invention for cleaning silicon wafers by selectively removing a native oxide layer from the silicon wafer without significantly affecting the underlying silicon, or a polysilicon or thermal oxide deposition that may be thereon.
- the apparatus illustrated in FIGS. 1 and 2 includes a reactor, generally designated 2 , consisting of a horizontal quartz tube defining an internal reactor chamber 3 .
- the horizontal quartz tube may be about 85 mm in length, about 15 mm in diameter, and about 2 mm wall thickness.
- the lower half of reactor chamber 3 is occupied by a half-cylinder shaped graphite susceptor 4 which supports one of more silicon wafers SW to be processed within the reactor chamber.
- an infrared lamp 5 Externally of and below reactor chamber 3 is an infrared lamp 5 which heats the graphite susceptor 4 from below.
- the graphite susceptor has a thermo-couple 6 embedded within it for temperature measurement, which measurement is outputted via lead 6 a .
- reactor 2 Externally above reactor 2 is a low-pressure mercury lamp 7 which generates ultra-violet light for radiating the silicon wafers SW supported on the graphite susceptor 4 .
- the upstream end of reactor 2 includes a gas supply manifold 8 for supplying the etchant gas; and the down-stream end of the reactor includes a gas discharge assembly 9 for removing the etchant gas Gas discharge assembly 9 may be a roughing pump connected to the downstream end of the reactor chamber by a series of steel pipes.
- the reactor 2 is only schematically shown in FIGS. 1 and 2. Preferably it would be of the structure described in U.S. Pat. No. 5,228,206, which description is hereby incorporated by reference.
- the silicon wafers SW to be cleaned are supported on the upper flat surface of the graphite susceptor 4 , as shown in FIGS. 1 and 2. Preferably, this is done by supporting it on three supporting pins spacing the wafer from the susceptor to minimize the contact of the wafer with the susceptor.
- the infrared lamp heater 5 is energized to heat the graphite susceptor to a predetermined temperature as measured by thermo-couple 6 embedded within the graphite susceptor.
- the silicon wafers SW are also irradiated with ultraviolet light from the ultraviolet lamp 7 overlying the reactor 2 . While the silicon wafers SW are thus heated by heater 5 and irradiated with ultraviolet light by ultraviolet lamp 7 . They are exposed to a flow of etchant gas introduced via the inlet manifold 8 and exhausted via the gas discharge assembly 9 .
- the etchant is NF 3 mixed with N 2 .
- Each gas is supplied at a partial pressure of 30 Torr (total pressure 60 Torr) with a gas flow of 200 cm 3 /sec. in this example, the process time was three minutes.
- a number of silicon wafer samples were thus treated by the etchant while heated by infrared lamps 5 to a predetermined high temperature, ranging from room temperature 27° C. to 600° C., and while exposed to the ultraviolet light from the UV (ultra violet) lamp 7 .
- the samples were removed from the reactor chamber and immediately analyzed with an ellipsometer to measure the thickness of the various layers. It was possible to calculate the amount of material removed during each process from each sample by comparing the ellipsometer measurements made with respect to each sample before being processed, with those made after the sample was processed.
- FIG. 3 is a table setting forth the results obtained when three silicon wafer samples (a), (b) and (c) were processed as described above at 27° C. (room temperature), 300° C. without ultraviolet radiation, 300° C. with ultraviolet radiation, 450° C. without ultraviolet radiation, and 600° C. without ultraviolet radiation.
- Sample (a) was a silicon single crystal wafer with a native oxide layer
- sample (b) was a silicon wafer having a 4000 A layer of polysilicon and a 1000 A layer of thermal oxide
- sample (c) was a silicon wafer having a 1000 A layer of thermal oxide.
- the treatment in all cases was carried out for three minutes, and included the etchant gas of NF 3 and N 2 as described above.
- An important advantage of the process of the present invention is that it achieves a significantly increased etch rate at the low pressure desirable for such process for reasons set forth earlier.
- P NF3 30 Torr
- the room temperature process reported by Torek K Torek, PhD thesis, Penn State University. 1996) referred to above, gave an etch rate of only 0.7 A/min at this NF3 pressure and room temperature. It is to be noted that the higher etch rate given by the elevated temperature process does not harm the selectivity of native oxide etch over thermal oxide and silicon, which are not etched.
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Inorganic Chemistry (AREA)
- Optics & Photonics (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A method and apparatus for selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other material, that may be thereon, by exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation, and heating the wafer to a temperature of 100-400° C.
Description
- This application is related to Provisional Application No. 60/086,635, filed May 20, 1998 and claims its priority date.
- The present invention relates to a method and apparatus for selectively removing native oxide layers from silicon wafers without significantly affecting the underlying silicon, or without significantly removing other materials, such as polysilicon or thermal oxide depositions, that may be thereon. Such a process is of substantial importance to the semiconductor industry since the selective removal of native oxide from silicon wafers is among the most frequently performed processes in fabricating silicon semiconductor devices.
- Whenever a silicon wafer is exposed to an oxidizing environment, a native oxide layer tends to form on the silicon wafer. Such native oxide layers would deleteriously affect the subsequent processing steps performed on the silicon wafer, and therefore must be cleanly and quickly removed without disturbing other depositions, such as, polysilicon or thermal oxide depositions, on the silicon wafer. Generally speaking, a dry cleaning process is more effective and less damaging to the silicon surface than a wet cleaning process.
- Narita U.S. Pat. No. 4,985,372 describes a dry cleaning process wherein the silicon wafer surface is exposed to an echant gas including NF3 and H2, or N2 in place of the H2. The process described in that patent requires the generation of a plasma in the chamber at the time the wafer is exposed to the etchant gas.
- Another cleaning technique is described in a PhD Thesis by Kevin J. Torek, University of Pennsylvania, May 1996. One described process involves exposing the silicon wafer to NF3 gas and to ultraviolet radiation while at room temperature (20° C.). According to the data set forth in that Thesis (FIG. 8. page 47), the native oxide was etched at a relatively low rate of between 0.7 A/min (at 80 Torr) to 4A/min (at 760 Torr) The native oxide removal was selective over depositions on the silicon wafer produced by sputtoring, chemical vapor deposition, steam-thermal deposition, and dry-thermal oxide deposition.
- This Thesis described another process (FIG. 10, page 50) which included heating the wafer while exposing it to NF3 in the presence of ultraviolet light and H2O. However, such a process involves completely different chemistry since the addition of H2O causes the formation of HF and completely changes the reaction rates and selectivities.
- An object of the present invention is to provide a method for selectively removing a native oxide layer from a silicon wafer having advantages over the above-described methods known in the prior art. Another object of the invention is to provide apparatus for removing native oxide layers in accordance with the novel method.
- According to one aspect of the present invention, there is provided a method of selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on, comprising exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation and heating the wafer to a temperature of 100-400° C.
- Preferably, the process should be performed at a temperature of 250-350° C., particularly good results having been obtained at a temperature of about 300° C. As will be described more particularly below, it has been found that elevating the process temperature as described above substantially increases the removal rate of the native oxide without losing the selectivity achieved at room temperature until the higher end of above-described temperature range is reached At higher temperatures, the native oxide removal rate may increase further, but it was found that selectivity is lost.
- According to further features in the preferred embodiment of the invention described below, the etchant gas also includes N2 The example described below includes N2 in approximately equal proportions by volume as the NF3.
- According to still further features in the described preferred embodiment, the partial pressure of the etchant gas is preferably within the moderate pressure range, of 10-300 Torr. The higher partial pressures would be expected to produce faster reaction rates, but would result in a number of disadvantages. Thus, higher pressures in the reactor increase the danger of leakage of NF3 from the reactor to the atmosphere, which can cause a serious health problem since NF3 is highly toxic. In addition, a high pressure in the reactor increases the danger of particles depositing on the silicon wafer being treated which will cause problems in subsequent processing of the wafer. Further, a higher pressure in the reactor increases the wafer processing time in single-wafer processing apparatus, since the NF3 must be completely removed from the chamber prior to transferring the wafer to the next process module. Thus, a low process pressure saves time by requiring less pump down time at the end of the process, and less time for pressure and flow stabilization at the beginning of the process.
- Preferably, therefore, the pressure should be below 100 Torr. optimally about 30-60 Torr. In the example described below, the partial pressure of the NF3 was 30 Torr and the partial pressure of the N2 was 30 Torr.
- According to another aspect of the present invention, there is provided apparatus for removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on, comprising a heating chamber including a supporting member for supporting the wafer from which the native oxide layer is to be selectively removed; a heater for heating a wafer on the supportive member to a temperature of 100-400° C.; a gas supply for introducing into the chamber an etchant gas including NF3; and an ultraviolet source for irradiating the water with ultraviolet radiation while the wafer is exposed to the etchant gas and is heated to the temperature of 100-400° C.
- Further features and advantages of the invention will be apparent from the description below
- The invention is herein described, somewhat diagramatically and by way of example only, with reference to the accompanying drawings, wherein:
- FIG. 1 is a side view illustrating one form of apparatus constructed in accordance with the present invention;
- FIG. 2 is an axial view of the apparatus of FIG. 1; and
- FIG. 3 sets forth the results a number of experiments in selectively removing native oxide layers from a silicon wafer in accordance with the present invention.
- FIGS. 1 and 2 schematically illustrate one form of apparatus constructed in accordance with the present invention for cleaning silicon wafers by selectively removing a native oxide layer from the silicon wafer without significantly affecting the underlying silicon, or a polysilicon or thermal oxide deposition that may be thereon.
- The apparatus illustrated in FIGS. 1 and 2 includes a reactor, generally designated2, consisting of a horizontal quartz tube defining an
internal reactor chamber 3. The horizontal quartz tube may be about 85 mm in length, about 15 mm in diameter, and about 2 mm wall thickness. The lower half ofreactor chamber 3 is occupied by a half-cylinder shapedgraphite susceptor 4 which supports one of more silicon wafers SW to be processed within the reactor chamber. Externally of and belowreactor chamber 3 is aninfrared lamp 5 which heats thegraphite susceptor 4 from below. The graphite susceptor has a thermo-couple 6 embedded within it for temperature measurement, which measurement is outputted via lead 6 a. Externally abovereactor 2 is a low-pressure mercury lamp 7 which generates ultra-violet light for radiating the silicon wafers SW supported on thegraphite susceptor 4. The upstream end ofreactor 2 includes agas supply manifold 8 for supplying the etchant gas; and the down-stream end of the reactor includes a gas discharge assembly 9 for removing the etchant gas Gas discharge assembly 9 may be a roughing pump connected to the downstream end of the reactor chamber by a series of steel pipes. - The
reactor 2 is only schematically shown in FIGS. 1 and 2. Preferably it would be of the structure described in U.S. Pat. No. 5,228,206, which description is hereby incorporated by reference. - The silicon wafers SW to be cleaned are supported on the upper flat surface of the
graphite susceptor 4, as shown in FIGS. 1 and 2. Preferably, this is done by supporting it on three supporting pins spacing the wafer from the susceptor to minimize the contact of the wafer with the susceptor. Theinfrared lamp heater 5 is energized to heat the graphite susceptor to a predetermined temperature as measured by thermo-couple 6 embedded within the graphite susceptor. The silicon wafers SW are also irradiated with ultraviolet light from theultraviolet lamp 7 overlying thereactor 2. While the silicon wafers SW are thus heated byheater 5 and irradiated with ultraviolet light byultraviolet lamp 7. They are exposed to a flow of etchant gas introduced via theinlet manifold 8 and exhausted via the gas discharge assembly 9. - As one example, the etchant is NF3 mixed with N2. Each gas is supplied at a partial pressure of 30 Torr (total pressure 60 Torr) with a gas flow of 200 cm3/sec. in this example, the process time was three minutes.
- A number of silicon wafer samples were thus treated by the etchant while heated by
infrared lamps 5 to a predetermined high temperature, ranging from room temperature 27° C. to 600° C., and while exposed to the ultraviolet light from the UV (ultra violet)lamp 7. After the process had been completed, the samples were removed from the reactor chamber and immediately analyzed with an ellipsometer to measure the thickness of the various layers. It was possible to calculate the amount of material removed during each process from each sample by comparing the ellipsometer measurements made with respect to each sample before being processed, with those made after the sample was processed. - FIG. 3 is a table setting forth the results obtained when three silicon wafer samples (a), (b) and (c) were processed as described above at 27° C. (room temperature), 300° C. without ultraviolet radiation, 300° C. with ultraviolet radiation, 450° C. without ultraviolet radiation, and 600° C. without ultraviolet radiation. Sample (a) was a silicon single crystal wafer with a native oxide layer; sample (b) was a silicon wafer having a4000 A layer of polysilicon and a 1000 A layer of thermal oxide; and sample (c) was a silicon wafer having a 1000 A layer of thermal oxide. The treatment in all cases was carried out for three minutes, and included the etchant gas of NF3 and N2 as described above.
- As can be seen from the data set forth in the table of FIG. 3, no significant etching of any of the layers was noted when the process was performed at 27° C. with ultraviolet radiation, or at 300° C. without ultraviolet radiation.
- However, when the process was performed at 300° C. with ultraviolet radiation, the native oxide layer was completely removed from sample (a); but neither the polysilicon layer nor the thermal oxide layer was removed from sample (b), nor was the thermal oxide layer removed from sample (c).
- When the process was performed at 450° C., even without ultraviolet radiation, the native oxide from sample (a) was completely removed, but the polysilicon from sample (b) was also completely removed. Similarly, when the process was performed at 600° C., the native oxide was removed from sample (a), but the polysilicon and thermal oxide layers were also completely removed from sample (b), and the thermal oxide layer was removed from sample (c). The removal of the polysilicon and thermal oxide layers from samples (b) and (c) would of course destroy the selectivity of the etching process; moreover had the samples also been irradiated with ultraviolet light when heated to those very high temperatures 450° C. and 600° C., it would be expected that the undesired removal of the polysilicon and thermal oxide layers would even have been accelerated.
- Accordingly, among the temperatures and other conditions tested in the above-described experiments, it is clear that best results were obtained in rate of removal and selectivity when the process is performed at a temperature approximately 300° C. while accompanied with ultraviolet radiation.
- It is believed that the selectivity can be explained by the nature of the reaction involved of the etchant gas with silicon dioxide and silicon. Thus, without ultraviolet radiation, when the temperature is less than 600° C., the process is controlled by the thermally-activated reaction of NF3 with silicon.
- 4NF 3↑+3Si→3SiF 4↑2N 3 556 (1)
- With UV photon activation, a controlled quantity of F-radicals can be obtained, which interact with SiO2.
- 4F+SiO 2 →SiF 4 ↑+O 2↑(2)
- This reaction is less temperature dependent and occurs rather fast (native oxide removed for 3 min) at the temperature lower than those required for the reaction (2).
- When the temperature is above 600° C., a thermal decomposition of NF3 to F-radicals takes place. Both reactions therefore occur, and the selectivity is lost.
- An important advantage of the process of the present invention is that it achieves a significantly increased etch rate at the low pressure desirable for such process for reasons set forth earlier. For example, at PNF3=30 Torr (and Pn2b =30 Torr) the described process at 300° C. gives a native oxide etch rate of over 5 A/min., while the room temperature process reported by Torek (K Torek, PhD thesis, Penn State University. 1996) referred to above, gave an etch rate of only 0.7 A/min at this NF3 pressure and room temperature. It is to be noted that the higher etch rate given by the elevated temperature process does not harm the selectivity of native oxide etch over thermal oxide and silicon, which are not etched.
- While the invention has been described with respect to one preferred embodiment, it will be appreciated that this is set forth merely for purposes of example, and that many other variations, modifications and applications of the invention may be made.
Claims (24)
1. A method of selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be there on, comprising exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation and heating the wafer to a temperature of 100-400° C.
2. The method according to claim 1 wherein the wafer is heated to a temperature of 250-350° C.
3. The method according to claim 1 , wherein the wafer is heated to a temperature of approximately 300° C.
4. The method according to claim 1 , wherein said etchant gas also includes N2.
5. The method according to claim 4 , wherein said etchant gas includes N2 in approximately equal proportions by volume with NF3.
6. The method according to claim 1 , wherein the partial pressure of the etchant gas is 10-300 Torr.
7. The method according to claim 1 , wherein the partial pressure of the etchant gas is below 100 Torr.
8. The method according to claim 7 , wherein the partial pressure of the etchant gas is 30-60 Torr.
9. A method of selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon, or without significantly removing a polysilicon or thermal oxide deposition that may be thereon, comprising: exposing the silicon wafer to an etchant gas including NF3at a partial pressure of 10 to 300 Torr, while exposing the wafer to ultraviolet radiation, and while heating the wafer to a temperature of 100-400° C.
10. The method according to claim 9 , wherein the wafer is heated to a temperature of 250-350° C.
11. The method according to claim 10 , wherein the wafer is heated to a temperature of approximately 300° C.
12. The method according to claim 9 , wherein said etchant gas also includes N2.
13. The method according to claim 12 , wherein said etchant gas includes N2 in approximately equal proportions by volume with NF3.
14. The method according to claim 9 , wherein the partial pressure of the etchant gas is 30-60 Torr.
15. Apparatus for selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon of other materials that may be there on, comprising:
a heating chamber including a supporting member for supporting the wafer from which native oxide layer is to be selectively removed;
a heater for heating a wafer on the supporting member to a temperature of 100-400° C.;
a gas supply for introducing into said chamber an etchant gas including NF3;
and an ultraviolet source for irradiating the wafer with ultraviolet radiation while the wafer is exposed to said etchant gas and is heated to said temperature of 100-400° C.
16. The apparatus according to claim 15 , wherein said heater heats the wafer to a temperature of 250-350° C.
17. The apparatus according to claim 15 , wherein said heater heats the wafer to a temperature of approximately 300° C.
18. The apparatus according to claim 15 , wherein said gas supply introduces N2 with said NF3.
19. The method according to claim 15 , wherein the partial pressure of the etchant gas is 10-300 Torr.
20. The apparatus according to claim 20 , wherein the partial pressure of the etchant gas is 30-60 Torr.
21. The apparatus according to claim 15 , wherein said heater is an infrared lamp heater.
22. The apparatus according to claim 15 , wherein said wafer supporting member is of graphite.
23. The apparatus according to claim 15 , wherein said chamber is of quartz.
24. The apparatus according to claim 23 wherein said heater is an infrared lamp heater and is located externally of said quartz chamber below said wafer supporting member, and said ultraviolet source is an ultraviolet lamp located externally of said chamber above said wafer supporting member.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/115,666 US20020108930A1 (en) | 1998-05-26 | 2002-04-04 | Apparatus for removing native oxide layers from silicon wafers |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US8665598P | 1998-05-26 | 1998-05-26 | |
US8663598P | 1998-05-26 | 1998-05-26 | |
US09/318,608 US6395192B1 (en) | 1998-05-26 | 1999-05-26 | Method and apparatus for removing native oxide layers from silicon wafers |
US10/115,666 US20020108930A1 (en) | 1998-05-26 | 2002-04-04 | Apparatus for removing native oxide layers from silicon wafers |
Related Parent Applications (1)
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US09/318,608 Division US6395192B1 (en) | 1998-05-26 | 1999-05-26 | Method and apparatus for removing native oxide layers from silicon wafers |
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US20020108930A1 true US20020108930A1 (en) | 2002-08-15 |
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US09/318,608 Expired - Fee Related US6395192B1 (en) | 1998-05-26 | 1999-05-26 | Method and apparatus for removing native oxide layers from silicon wafers |
US10/115,666 Abandoned US20020108930A1 (en) | 1998-05-26 | 2002-04-04 | Apparatus for removing native oxide layers from silicon wafers |
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US09/318,608 Expired - Fee Related US6395192B1 (en) | 1998-05-26 | 1999-05-26 | Method and apparatus for removing native oxide layers from silicon wafers |
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US (2) | US6395192B1 (en) |
Cited By (7)
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US20070272355A1 (en) * | 2006-05-29 | 2007-11-29 | Nec Lcd Technologies, Ltd. | Apparatus for processing substrate and method of doing the same |
US20080066778A1 (en) * | 2006-09-19 | 2008-03-20 | Asm Japan K.K. | Method of cleaning uv irradiation chamber |
US20080289650A1 (en) * | 2007-05-24 | 2008-11-27 | Asm America, Inc. | Low-temperature cleaning of native oxide |
US7871937B2 (en) | 2008-05-16 | 2011-01-18 | Asm America, Inc. | Process and apparatus for treating wafers |
US9299557B2 (en) | 2014-03-19 | 2016-03-29 | Asm Ip Holding B.V. | Plasma pre-clean module and process |
US9474163B2 (en) | 2014-12-30 | 2016-10-18 | Asm Ip Holding B.V. | Germanium oxide pre-clean module and process |
US10373850B2 (en) | 2015-03-11 | 2019-08-06 | Asm Ip Holding B.V. | Pre-clean chamber and process with substrate tray for changing substrate temperature |
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US6184132B1 (en) * | 1999-08-03 | 2001-02-06 | International Business Machines Corporation | Integrated cobalt silicide process for semiconductor devices |
US11469109B2 (en) * | 2019-03-14 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having metal contact features and method for forming the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4985372A (en) | 1989-02-17 | 1991-01-15 | Tokyo Electron Limited | Method of forming conductive layer including removal of native oxide |
US5022961B1 (en) * | 1989-07-26 | 1997-05-27 | Dainippon Screen Mfg | Method for removing a film on a silicon layer surface |
JPH07109825B2 (en) * | 1992-01-13 | 1995-11-22 | 富士通株式会社 | Dry cleaning method for semiconductor substrate surface or thin film surface |
US5228206A (en) | 1992-01-15 | 1993-07-20 | Submicron Systems, Inc. | Cluster tool dry cleaning system |
US5439553A (en) * | 1994-03-30 | 1995-08-08 | Penn State Research Foundation | Controlled etching of oxides via gas phase reactions |
US6165273A (en) * | 1997-10-21 | 2000-12-26 | Fsi International Inc. | Equipment for UV wafer heating and photochemistry |
-
1999
- 1999-05-26 US US09/318,608 patent/US6395192B1/en not_active Expired - Fee Related
-
2002
- 2002-04-04 US US10/115,666 patent/US20020108930A1/en not_active Abandoned
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US20070272355A1 (en) * | 2006-05-29 | 2007-11-29 | Nec Lcd Technologies, Ltd. | Apparatus for processing substrate and method of doing the same |
US20080066778A1 (en) * | 2006-09-19 | 2008-03-20 | Asm Japan K.K. | Method of cleaning uv irradiation chamber |
US7789965B2 (en) | 2006-09-19 | 2010-09-07 | Asm Japan K.K. | Method of cleaning UV irradiation chamber |
US20080289650A1 (en) * | 2007-05-24 | 2008-11-27 | Asm America, Inc. | Low-temperature cleaning of native oxide |
US7871937B2 (en) | 2008-05-16 | 2011-01-18 | Asm America, Inc. | Process and apparatus for treating wafers |
US9299557B2 (en) | 2014-03-19 | 2016-03-29 | Asm Ip Holding B.V. | Plasma pre-clean module and process |
US9514927B2 (en) | 2014-03-19 | 2016-12-06 | Asm Ip Holding B.V. | Plasma pre-clean module and process |
US9474163B2 (en) | 2014-12-30 | 2016-10-18 | Asm Ip Holding B.V. | Germanium oxide pre-clean module and process |
US10373850B2 (en) | 2015-03-11 | 2019-08-06 | Asm Ip Holding B.V. | Pre-clean chamber and process with substrate tray for changing substrate temperature |
US11264255B2 (en) | 2015-03-11 | 2022-03-01 | Asm Ip Holding B.V. | Pre-clean chamber and process with substrate tray for changing substrate temperature |
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