US20020084828A1 - Triple well no body effect negative charge pump - Google Patents
Triple well no body effect negative charge pump Download PDFInfo
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- US20020084828A1 US20020084828A1 US09/751,695 US75169500A US2002084828A1 US 20020084828 A1 US20020084828 A1 US 20020084828A1 US 75169500 A US75169500 A US 75169500A US 2002084828 A1 US2002084828 A1 US 2002084828A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/078—Charge pumps of the Schenkel-type with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters
Definitions
- the present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to a triple well no body effect negative charge pump.
- Nonvolatile memories are advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data.
- Flash memory can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device in one relatively rapid operation. The flash memory may then be programmed with new code or data.
- Flash memories have been used in portable computers and similar circuitry as both read only memory and as long term storage which may be both read and written.
- the tendency has been to reduce the power requirements of such portable computers to make systems lighter and to increase the length of use between recharging. This has required that the voltage potentials available to program the flash memory arrays be reduced. Flash memories must be able to operate in systems where a VCC supply voltage of 5V, 3V, or an even smaller voltage is available to circuit components.
- FIG. 1 is one embodiment of a computer system utilizing a triple well no body effect negative charge pump
- FIG. 2 is a flash memory circuit using a triple well no body effect negative charge pump of one embodiment
- FIG. 3 is a circuit diagram of a four stage triple well no body effect negative charge pump of one embodiment
- FIG. 4 shows a timing diagram of the pump clocking waveforms used in connection with the negative charge pump of FIG. 3;
- FIG. 5 is a plot of the output of one stage of the negative charge pump embodiment of FIG. 3.
- FIG. 6 is a flow diagram illustrating the method of eliminating body effect in a negative charge pump for one embodiment.
- a method and apparatus for a triple well no body effect negative charge pump is disclosed.
- the embodiments described herein are described in the context of a memory, but are not so limited. Although the following embodiments are described with reference to flash memory, other embodiments are applicable to other integrated circuits or logic devices. The same techniques and teachings of the present invention can easily be applied to other types of circuits or semiconductor devices that use charge pumps.
- Embodiments of the present invention relate to a triple well no body effect NMOS negative charge pump.
- Current negative charge pumps are created with P type transistor devices.
- negative charge pumps can be implemented with N type transistors devices also.
- the negative charge pump embodiments described below use triple well N channel high mobility transistor devices with the deep N wells grounded, instead of regular P channel low mobility transistor devices.
- the parasitic bipolar transistors are avoided such that the charge transfer occurs mainly in the channel of the transistor device.
- the triple N channel devices provide twice the mobility of regular P channel devices.
- P type transistor devices typically have a strong body effect, which negatively impacts the mobility. With the increased mobility of the N type devices, embodiments of the negative charge pumps using N type transistors can be more efficient and more current can be available.
- System 100 includes a component, such as a processor, employing a triple well no body effect negative charge pump in accordance with the present invention, such as in the embodiment described herein.
- System 100 is representative of processing systems based on the PENTIUM®Pro, PENTIUM®II, PENTIUM®III, Itanium®microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used.
- sample system 100 may be executing a version of the WINDOWSTM operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems and graphical user interfaces, for example, may also be used.
- WINDOWSTM operating system available from Microsoft Corporation of Redmond, Wash.
- other operating systems and graphical user interfaces for example, may also be used.
- the present invention is not limited to any specific combination of hardware circuitry and software.
- the present enhancement is not limited to computer systems.
- Alternative embodiments of the present invention can be used in other devices such as, for example, handheld devices and embedded applications.
- Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs.
- Embedded applications can include a microcontroller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system which uses a charge pump for other embodiments.
- DSP digital signal processor
- NetPC network computers
- Set-top boxes network hubs
- WAN wide area network
- FIG. 1 is a block diagram of one embodiment of a system 100 .
- System 100 is an example of a hub architecture.
- the computer system 100 includes a processor 102 that processes data signals.
- the processor 102 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or other processor device, such as a digital signal processor, for example.
- FIG. 1 shows an example of an embodiment of the present invention implemented in a single processor system 100 . However, it is understood that other embodiments may alternatively be implemented as systems having multiple processors.
- Processor 102 is coupled to a processor bus 110 that transmits data signals between processor 102 and other components in the system 100 .
- the elements of system 100 perform their conventional functions well known in the art.
- System 100 includes a memory 120 .
- Memory 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device.
- Memory 120 may store instructions and/or data represented by data signals that may be executed by processor 102 .
- a cache memory 104 can reside inside processor 102 that stores data signals stored in memory 120 . Alternatively, in another embodiment, the cache memory may reside external to the processor.
- a system logic chip 116 is coupled to the processor bus 110 and memory 120 .
- the system logic chip 116 in the illustrated embodiment is a memory controller hub (MCH).
- the processor 102 communicates to the MCH 116 via a processor bus 110 .
- the MCH 116 provides a high bandwidth memory path 118 to memory 120 for instruction and data storage and for storage of graphics commands, data and textures.
- the MCH 116 directs data signals between processor 102 , memory 120 , and other components in the system 100 and bridges the data signals between processor bus 110 , memory 120 , and system I/O 122 .
- the system logic chip 116 provides a graphics port for coupling to a graphics controller 112 .
- the MCH 116 is coupled to memory 120 through a memory interface 118 .
- the graphics card 112 is coupled to the MCH 116 through an Accelerated Graphics Port (AGP) interconnect 114 .
- AGP Accelerated Graphics Port
- System 100 uses a proprietary hub interface bus 122 to couple the MCH 116 to the I/O controller hub (ICH) 130 .
- the ICH 130 provides direct connections to some I/O devices. Some examples are the audio controller, firmware hub (BIOS) 128 , data storage 124 , legacy 1 / 0 controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and a network controller 134 .
- the data storage device 124 can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.
- a triple well no body effect negative charge pump 126 also resides in flash memory BIOS 128 .
- Alternate embodiments of a triple well no body effect negative charge pump 106 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits.
- one implementation of a charge pump can be used with a system on a chip.
- One embodiment of a system on a chip comprises of a processor and a memory.
- the memory for one system is a flash memory.
- the flash memory can be located on the same die as the processor and other system components. Additionally, other logic blocks such as a memory controller or graphics controller can also be located on a system on a chip.
- the flash memory can be enabled to program and erase flash memory cells without requiring a high voltage pin on the system on a chip pin-out. The needed high voltage potentials can be generated on the same die.
- FIG. 2 is a flash memory circuit 200 using a triple well no body effect negative charge pump of one embodiment.
- Reference generator 220 provides a reference voltage 225 to the positive pump 240 .
- the positive pump 240 provides a regulated voltage of approximately five volts over decoder supply line 245 to the X-decoders 250 of the memory array 260 .
- the negative charge pump 240 is a triple well no body effect negative charge pump.
- the negative pump provides a voltage of approximately negative five volts over decoder supply line 235 to the X-decoders of memory array 260 .
- a first oscillator 210 provides a clock signal 212 that periodically pulses or enables the negative pump 230 during a standby mode.
- a second oscillator 213 provides clock signals 214 , 216 that periodically pulse or enable the positive pump 240 and the reference generator 220 , respectively, when they are in a standby mode.
- the clock signals 212 , 214 , 216 may each have a different frequency.
- FIG. 3 is a simplified circuit diagram of a four stage triple well no body effect negative charge pump architecture of one embodiment.
- the four state negative charge pump 300 of this embodiment comprises of four pump stages.
- the embodiment of FIG. 3 includes switching transistors N 14 310 , N 24 330 , N 34 350 , N 44 370 connected in series between ground 382 and VOUT 341 .
- the switching transistors N 14 310 , N 24 330 , N 34 350 , N 44 370 are preferably triple well N type field effect transistors.
- the embodiment of FIG. 3 further includes pull-down transistors N 13 308 , N 23 328 , N 33 348 , N 43 368 .
- the pull-down transistors N 13 308 , N 23 328 , N 33 348 , N 43 368 are triple well N type field effect transistors in this embodiment.
- the source terminal of pull-down transistor N 13 308 , N 23 328 , N 33 348 , N 43 368 is connected to the gate terminal of switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the pull-down transistors N 13 308 , N 23 328 , N 33 348 , N 43 368 are diode connected, with the drain terminal and the gate terminal of each pull-down transistor N 13 308 , N 23 328 , N 33 348 , N 43 368 connected to the drain terminal of the respective switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 .
- the embodiment of FIG. 3 further includes pull-up transistors N 12 306 , N 22 326 , N 32 346 , N 42 366 .
- the pull-up transistors N 12 306 , N 22 326 , N 32 346 , N 42 366 of this embodiment are triple well N type field effect transistors.
- the drain terminal of the pull-up transistor N 12 306 , N 22 326 , N 32 346 , N 42 366 is connected to the gate terminal of the switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the source terminal of the pull-up transistor N 12 306 , N 22 326 , N 32 346 , N 42 366 is connected to the drain terminal of the switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the gate terminal of the pull-up transistor N 12 306 , N 22 326 , N 32 346 , N 42 366 is connected to the source terminal of control device N 11 304 , N 21 324 , N 31 344 , N 41 364 , respectively.
- Some existing charge pumps such as a charge pump apparatus with diode connected pull-down on boot nodes, have pull-up devices whose gates are connected to the same boot node.
- the charge passing device or switching transistor cannot maintain its gate terminal voltage level when its drain terminal voltage drops down during charge transfer.
- the pull-up diode is gradually turned on in the process. This causes insufficient charge transfer for pump stages that have relatively low threshold voltage switching transistors.
- One solution is to turn off the pull-up transistor or pull-up diode during charge transfer so that the gate voltage of the switching transistor can be maintained.
- a control device serves as a switch between the gate and drain terminals of the pull-up transistor.
- the control device switches the pull-up transistor from being diode connected or not.
- Control devices N 11 304 , N 21 324 , N 31 344 , N 41 364 are N type field effect transistors in this embodiment.
- the drain terminal of control device N 11 304 , N 21 324 , N 31 344 , N 41 364 is connected to the gate terminal of switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the gate terminal of control device N 11 304 , N 21 324 , N 31 344 , N 41 364 is connected to the source terminal of switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- Control devices N 11 304 , N 21 324 , N 31 344 , N 41 364 separate the boot node 305 , 325 , 345 , 365 from the diode connected pull-up device N 12 306 , N 22 326 , N 32 346 , N 42 366 respectively.
- the gate terminal of the triple well N device N 11 304 , N 21 324 , N 31 344 , N 41 364 connect to the next higher pump node 301 , 311 , 331 , 351 , respectively, and stops the formerly diode connected N 12 306 , N 22 326 , N 32 346 , N 42 366 from discharging the boot node 305 , 325 , 345 , 365 while the node is being booted by CLOCK 1 386 or CLOCK 3 392 , respectively.
- storage capacitors C 12 312 , C 22 332 , C 32 352 , C 42 372 are also included in the embodiment of FIG. 3 .
- Storage capacitor C 12 312 is connected between a CLOCK 2 388 signal and the source terminal of switching transistor N 14 310 .
- Storage capacitor C 22 332 is connected between a CLOCK 4 392 signal and the source terminal of the switching transistor N 24 330 .
- Storage capacitor C 32 352 is connected between a CLOCK 2 388 signal and the source terminal of switching transistor N 34 350 .
- Storage capacitor C 42 372 is connected between a CLOCK 4 392 signal and the source terminal of switching transistor N 44 370 .
- the embodiment of FIG. 3 further includes boot node capacitors C 11 302 , C 21 322 , C 31 342 , C 41 362 .
- Boot node capacitor C 11 302 is connected between a CLOCK 1 386 signal and the gate terminal of N 14 310 .
- Boot node capacitor C 21 322 is connected between a CLOCK 3 392 signal and the gate of N 24 330 .
- Boot node capacitor C 31 342 is connected between a CLOCK 1 386 signal and the gate of N 34 350 .
- Boot node capacitor C 41 362 is connected between a CLOCK 3 392 signal and the gate of N 44 370 .
- the clock signals 386 , 388 , 392 , 394 are generated by a four phase clock driver which takes its input from an oscillator circuit as in FIG. 2.
- the triple negative well no body effect negative charge pump 300 of this embodiment includes well biasing devices N 15 314 , N 16 316 , N 25 334 , N 26 336 , N 35 354 , N 36 356 , N 45 374 , N 46 376 .
- the well biasing devices switching and initiate the P well potential of the triple well N type devices to eliminate body effect.
- the P well switching can also prevent P-N junctions from being turned on to induce latch up.
- the Vt N drop is 0.6 volts versus the Vt p of 2.2 volts with a 12 volt body effect when outputting ⁇ 12V.
- the drain terminals of the well biasing devices in each individual pump stage are tied together with the substrate terminals of the N type devices of that stage.
- the substrate terminals described in this embodiment are also referred to as the P-well connection of the N type devices.
- the drain terminals of N 15 314 and N 16 316 are coupled together with the substrate terminals of N 11 304 , N 12 306 , N 13 308 , N 14 310 , N 15 314 , and N 16 316 in the first pump stage 390 .
- the drain terminals of N 25 334 and N 26 336 are coupled together with the substrate terminals of N 21 324 , N 22 326 , N 23 328 , N 24 330 , N 25 334 , and N 26 336 in the second pump stage.
- the drain terminals of N 35 354 and N 36 356 are coupled together with the substrate terminals of N 31 344 , N 32 346 , N 33 348 , N 34 350 , N 35 354 , and N 36 356 in the third pump stage.
- the drain terminals of N 45 374 and N 46 376 are coupled together with the substrate terminals of N 41 364 , N 42 366 , N 43 368 , N 44 370 , N 45 374 , and N 46 376 in the fourth pump stage.
- the gate terminal of N 15 314 , N 25 334 , N 35 354 , N 45 374 is connected to the gate terminal of switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the gate terminal of N 16 316 , N 26 336 , N 36 356 , N 46 376 is connected to the source terminal of switching transistor N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the source terminal of N 15 314 , N 25 334 , N 35 354 , N 45 374 is connected to the source terminal of switching device N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the source terminal of N 16 316 , N 26 336 , N 36 356 , N 46 376 is connected to the drain terminal of switching device N 14 310 , N 24 330 , N 34 350 , N 44 370 , respectively.
- the well biasing devices N 15 314 , N 25 334 , N 35 354 , N 45 374 and N 16 316 , N 26 336 , N 36 356 , N 46 376 alternately switch the potential on the substrates terminals between the voltage potential at the drain terminal and that at the source terminal of the respective switching device of that pump stage.
- Use of a triple well can reduce the stress voltage inside one embodiment of a negative pump cell to ⁇ 13 volts in comparison with the - 16 volt stress of some existing pump cells.
- Nodes 301 , 311 , 331 , 351 are shown in FIG. 3.
- Node 301 is defined by the connection of storage capacitor C 12 312 , the source terminal of switching transistor N 14 310 , the gate terminal of control device N 11 304 , and the gate and drain terminals of transistor N 1 396 .
- Ground 382 is connected to the source terminal of N 1 396 .
- Node 311 is defined by the connection of C 22 332 , the source terminal of N 24 330 , the gate terminal of N 21 324 , the drain terminal of N 14 310 , the gate and drain terminals of N 13 308 , and the source terminal of N 12 306 .
- Node 331 is defined by the connection of C 32 352 , the source terminal of N 34 350 , the gate terminal of N 31 344 , the drain terminal of N 24 330 , the gate and drain terminals of N 23 328 , and the source terminal of N 22 326 .
- Node 351 is defined by the connection of C 42 372 , the source terminal of N 34 350 , the gate terminal of N 41 364 , the drain terminal of N 34 350 , the gate and drain terminals of N 33 348 , and the source terminal of N 32 346 .
- Node 371 is defined by the connection of the source terminal of N 44 370 , the gate and drain terminals of N 43 368 , and the source terminal of N 42 366 .
- Boot nodes 305 , 325 , 345 , 365 are also shown in FIG. 3.
- Boot node 305 is defined by the connection of the boot capacitor C 11 302 , the gate terminal of switching transistor N 14 310 , the source terminal of pull-down transistor N 13 308 , the drain terminal of pull-up transistor N 12 306 , and the drain terminal of control device N 11 304 .
- Boot node 325 is defined by the connection of C 21 322 , the gate terminal of N 24 330 , the source terminal of N 23 328 , the drain terminal of N 22 326 , and the drain terminal of N 21 324 .
- Boot node 345 is defined by the connection of C 31 342 , the gate terminal of N 34 350 , the source terminal of N 33 348 , the drain terminal of N 32 346 , and the drain terminal of N 31 344 .
- Boot node 365 is defined by the connection of C 41 362 , the gate terminal of N 44 370 , the source terminal of N 43 368 , the drain terminal of N 42 366 , and the drain terminal of N 41 364 .
- the embodiment of FIG. 3 includes four negative charge pump stages.
- stage 390 includes the storage capacitor C 12 312 , the switching transistor N 14 310 , the pull-down transistor N 13 308 , the pull-up transistor N 12 306 , the control device N 11 304 , and the boot node capacitor C 11 302 .
- Stage 390 receives its input from ground 386 via diode connected transistor N 1 396 .
- the output of this charge pump embodiment is labeled as VOUT 371 . Positive charge is transferred in the direction from node 371 to ground 382 .
- the negative charge pump embodiment of FIG. 3 includes four stages, other numbers of stages are possible. Furthermore, the same techniques and teachings of the present invention can be applied to other applications wherein a negative voltage potential is needed to be generated internally.
- the present invention can be used in a variety of charge pumps to improve the output current and pumping efficiency. The increased output and efficiency may also lead to die size savings if the pump area of the charge pumps can be reduced as a result.
- Embodiments of the triple well negative pump architecture of the present invention may also offer power savings over existing pump designs.
- FIG. 4 shows a timing diagram of the pump clocking waveforms used in connection with the negative charge pump of FIG. 3.
- the clock signals CLOCK 1 410 , CLOCK 2420 , CLOCK 3 430 , CLOCK 4 440 control the operation of this embodiment of a triple well negative charge pump 300 .
- all of the clock signals 410 , 420 , 430 , 440 are at VCC level when high and at ground potential when low. VCC level varies depending on the particular embodiment and could possibly be 3V, 1.8V, or 1.55V.
- an embodiment of the present pump architecture no longer needs to have a positive charge pump to supply the negative pump for boot clocking when operating at a 1.55 volt power supply.
- the pumping operation can be abbreviated as the following steps and the repeat of those steps to generate currents.
- the following discussion will concentrate on the operation of pump 300 beginning with the first low-to-high transition of CLOCK 4 440 at time T 1 .
- CLOCK 4 440 is high, the potential at node 351 is boosted high.
- the high potential at node 351 pre-charges the boot node 345 of the third stage through N 33 348 and turns on N 41 364 .
- N 42 366 is activated to discharge boot node 365 of the fourth stage and turn off N 44 370 to prevent back conductance between node 351 and node 371 .
- N 46 376 is turned on to short P well terminals 369 to node 371 , which prevents the P well to N diffusion junctions of the triple well devices N 42 366 , N 43 368 , N 44 370 , N 46 376 from turning on.
- CLOCK 2 420 transitions low, the voltage potential at node 331 drops low to be ready to receive charge from C 42 372 at node 351 and turns off N 31 344 .
- boot node 345 goes high and N 34 350 gets turned on. Charge is transferred from C 42 372 at node 351 through N 34 350 to C 32 352 at node 331 .
- the voltage potential at node 351 decreases while the potential at node 331 increases.
- N 35 354 is turned on to short P well terminals 349 to node 331 , which prevents the P well to N diffusion junctions of the triple well devices N 34 350 , N 35 354 from turning on.
- CLOCK 1 410 transitions back to a logic low, the charge transfer from node 351 to node 331 stops and the voltage level on the nodes level out.
- boot node 325 of the second stage also goes high.
- a high CLOCK 3 430 turns on switching transistor N 24 330 .
- Charge is transferred from C 32 352 through N 24 330 to C 22 332 , causing the voltage potential on node 331 to drop and the potential on node 311 to rise.
- N 25 334 is turned on to short P well terminals 329 to node 311 , which prevents the P well to N diffusion junctions of the triple well devices N 24 330 , N 25 334 from turning on.
- CLOCK 3 430 goes low during time T 4 , the charge transfer stops.
- the potentials on node 331 and node 311 level out.
- the cycle repeats with the low to high transition of CLOCK 4 440 at time T 4 .
- the embodiment of FIG. 3 eliminates of the requirement of overlapping clock periods typically found with prior charge pump circuits. Overlapping clock periods are not required in the embodiment of FIG. 3 because the voltage on the boot nodes 305 , 325 , 345 , 365 are dependent on the voltages on the nodes 311 , 331 , 351 , 371 , respectively, and not on the voltage present at the prior stage, as is the case with prior pump circuits.
- the elimination of the overlapping clocks allows for an increase in clock frequency, which improves pump circuit performance.
- clocks signals 410 , 420 , 430 , 440 of FIG. 4 are shown to overlap, in other words no two clock edges are shown to occur simultaneously, there is no requirement for the clocks to overlap. Clock edges may occur nearly simultaneously, although a small overlap, preferably approximately 2 nanoseconds for one embodiment, may be used in order to account for the non-vertical nature of clock edges.
- FIG. 5 is a plot of the voltage potential outputted from the fourth stage of the negative charge pump embodiment 300 of FIG. 3.
- the plot indicates the voltage potential at node 351 during the operation of the pump 300 .
- the resulting output waveform from node 351 corresponds to the operation of pump 300 with the clock signals 410 , 420 , 430 , 440 of FIG. 4.
- the voltage ramp labeled V 351 indicates the potential transferred from VOLT 371 to node 351 when N 44 370 is turned on by a high CLOCK 3 386 . Note that when CLOCK 3 386 is high, node 351 is charged up to a VCC level. As CLOCK 4 388 goes high, node 351 is boosted from a VCC to 2VCC.
- N 34 350 turns on to transfer charge from node 351 to node 331 .
- the voltage drop labeled by ⁇ V indicates the amount of potential that is transferred from the fourth stage 590 to the third stage.
- CLOCK 4 388 goes low, node 351 is no longer boosted and the potential drops back to a low value. The cycle then repeats.
- FIG. 6 is a flow diagram illustrating the method of eliminating body effect in a negative charge pump for one embodiment.
- This example generally describes the operation of one negative pump stage.
- a boot node is precharged.
- the boot node discharge mechanism is disabled at step 604 .
- This discharge mechanism can be viewed as the pull-down device as in the pump cells of FIG. 3.
- the substrate of one or more of the N type transistor devices in the pump cell is biased at step 606 . This biasing prevents the P well to N diffusion junctions in the N type device from turning on during charge transfer.
- a logic high level is driven on the boot node to allow charge transfer to occur.
- This charge transfer can be related to the charge being passed from a storage capacitor of an earlier stage through a switching device over to a storage capacitor of a subsequent stage.
- a logic low level is driven on the boot node at step 610 to stop the charge transfer.
- the boot node discharge mechanism is enabled to fully turn off the charge passing device.
- the substrate of one or more of the N type transistor devices in the subsequent pump cell is biased to prevent the P well to N diffusion junctions in those N type devices from turning on during charge transfer in that cell.
- step 602 to step 614 repeat again and again to continually pass charge from the input of the pump cell to the output of the pump cell.
- the operation of subsequent pump cells in the charge pump operate in a similar manner, but the clocking are timed differently between adjacent cells in order to properly pump up the voltage.
Abstract
Description
- The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to a triple well no body effect negative charge pump.
- Many of today's computing applications such as cellular phones, digital cameras, and personal computers, use nonvolatile memories to store data or code. Nonvolatility is advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data.
- One example of a nonvolatile memory device is the flash Electrically Erasable Programmable Read-only Memory (flash EEPROM or flash memory). Flash memory can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device in one relatively rapid operation. The flash memory may then be programmed with new code or data.
- Flash memories have been used in portable computers and similar circuitry as both read only memory and as long term storage which may be both read and written. However, the tendency has been to reduce the power requirements of such portable computers to make systems lighter and to increase the length of use between recharging. This has required that the voltage potentials available to program the flash memory arrays be reduced. Flash memories must be able to operate in systems where a VCC supply voltage of 5V, 3V, or an even smaller voltage is available to circuit components.
- However, performing program and erase operations in flash memory components requires that greater voltage than that supplied to the component be applied to the flash memory cells. For example, an erase operation may require that approximately −10.5V be applied to a memory cell. In order to achieve this voltage, a charge pump circuit is required in the flash memory component. A negative charge pump creates a negative voltage sufficient for erase operations. The charge pump must also be able to deliver sufficient current at the required voltage levels.
- Furthermore, as the electronic applications and devices that use integrated circuit components move to lower and lower power, the flash memory components in these applications also have to be more power efficient. One possible area for optimization is the charge pump circuitry.
- The present invention is illustrated by way of example and not limitations in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
- FIG. 1 is one embodiment of a computer system utilizing a triple well no body effect negative charge pump;
- FIG. 2 is a flash memory circuit using a triple well no body effect negative charge pump of one embodiment;
- FIG. 3 is a circuit diagram of a four stage triple well no body effect negative charge pump of one embodiment;
- FIG. 4 shows a timing diagram of the pump clocking waveforms used in connection with the negative charge pump of FIG. 3;
- FIG. 5 is a plot of the output of one stage of the negative charge pump embodiment of FIG. 3; and
- FIG. 6 is a flow diagram illustrating the method of eliminating body effect in a negative charge pump for one embodiment.
- A method and apparatus for a triple well no body effect negative charge pump is disclosed. The embodiments described herein are described in the context of a memory, but are not so limited. Although the following embodiments are described with reference to flash memory, other embodiments are applicable to other integrated circuits or logic devices. The same techniques and teachings of the present invention can easily be applied to other types of circuits or semiconductor devices that use charge pumps.
- In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. One of ordinary skill in the art, however, will appreciate that these specific details are not necessary in order to practice the present invention. In other instances, well known electrical structures and circuits have not been set forth in particular detail in order to not necessarily obscure the present invention.
- Embodiments of the present invention relate to a triple well no body effect NMOS negative charge pump. Current negative charge pumps are created with P type transistor devices. With the use of a triple well semiconductor manufacturing process, negative charge pumps can be implemented with N type transistors devices also. The negative charge pump embodiments described below use triple well N channel high mobility transistor devices with the deep N wells grounded, instead of regular P channel low mobility transistor devices. The parasitic bipolar transistors are avoided such that the charge transfer occurs mainly in the channel of the transistor device. In one embodiment, the triple N channel devices provide twice the mobility of regular P channel devices. P type transistor devices typically have a strong body effect, which negatively impacts the mobility. With the increased mobility of the N type devices, embodiments of the negative charge pumps using N type transistors can be more efficient and more current can be available.
- Referring now to FIG. 1, an
exemplary computer system 100 is shown.System 100 includes a component, such as a processor, employing a triple well no body effect negative charge pump in accordance with the present invention, such as in the embodiment described herein.System 100 is representative of processing systems based on the PENTIUM®Pro, PENTIUM®II, PENTIUM®III, Itanium®microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In one embodiment,sample system 100 may be executing a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems and graphical user interfaces, for example, may also be used. Thus, the present invention is not limited to any specific combination of hardware circuitry and software. - The present enhancement is not limited to computer systems. Alternative embodiments of the present invention can be used in other devices such as, for example, handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include a microcontroller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system which uses a charge pump for other embodiments.
- FIG. 1 is a block diagram of one embodiment of a
system 100.System 100 is an example of a hub architecture. Thecomputer system 100 includes aprocessor 102 that processes data signals. Theprocessor 102 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or other processor device, such as a digital signal processor, for example. FIG. 1 shows an example of an embodiment of the present invention implemented in asingle processor system 100. However, it is understood that other embodiments may alternatively be implemented as systems having multiple processors.Processor 102 is coupled to aprocessor bus 110 that transmits data signals betweenprocessor 102 and other components in thesystem 100. The elements ofsystem 100 perform their conventional functions well known in the art. -
System 100 includes amemory 120.Memory 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device.Memory 120 may store instructions and/or data represented by data signals that may be executed byprocessor 102. Acache memory 104 can reside insideprocessor 102 that stores data signals stored inmemory 120. Alternatively, in another embodiment, the cache memory may reside external to the processor. - A
system logic chip 116 is coupled to theprocessor bus 110 andmemory 120. Thesystem logic chip 116 in the illustrated embodiment is a memory controller hub (MCH). Theprocessor 102 communicates to theMCH 116 via aprocessor bus 110. TheMCH 116 provides a highbandwidth memory path 118 tomemory 120 for instruction and data storage and for storage of graphics commands, data and textures. TheMCH 116 directs data signals betweenprocessor 102,memory 120, and other components in thesystem 100 and bridges the data signals betweenprocessor bus 110,memory 120, and system I/O 122. In some embodiments, thesystem logic chip 116 provides a graphics port for coupling to agraphics controller 112. TheMCH 116 is coupled tomemory 120 through amemory interface 118. Thegraphics card 112 is coupled to theMCH 116 through an Accelerated Graphics Port (AGP)interconnect 114. -
System 100 uses a proprietaryhub interface bus 122 to couple theMCH 116 to the I/O controller hub (ICH) 130. TheICH 130 provides direct connections to some I/O devices. Some examples are the audio controller, firmware hub (BIOS) 128,data storage 124,legacy 1/0 controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and anetwork controller 134. Thedata storage device 124 can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. - A triple well no body effect
negative charge pump 126 also resides inflash memory BIOS 128. Alternate embodiments of a triple well no body effect negative charge pump 106 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. - For another embodiment of a system, one implementation of a charge pump can be used with a system on a chip. One embodiment of a system on a chip comprises of a processor and a memory. The memory for one system is a flash memory. The flash memory can be located on the same die as the processor and other system components. Additionally, other logic blocks such as a memory controller or graphics controller can also be located on a system on a chip. By including one embodiment of the present invention on the system on a chip, the flash memory can be enabled to program and erase flash memory cells without requiring a high voltage pin on the system on a chip pin-out. The needed high voltage potentials can be generated on the same die.
- FIG. 2 is a
flash memory circuit 200 using a triple well no body effect negative charge pump of one embodiment.Reference generator 220 provides areference voltage 225 to thepositive pump 240. Thepositive pump 240 provides a regulated voltage of approximately five volts overdecoder supply line 245 to theX-decoders 250 of thememory array 260. For one embodiment, thenegative charge pump 240 is a triple well no body effect negative charge pump. The negative pump provides a voltage of approximately negative five volts overdecoder supply line 235 to the X-decoders ofmemory array 260. Afirst oscillator 210 provides aclock signal 212 that periodically pulses or enables thenegative pump 230 during a standby mode. Asecond oscillator 213 provides clock signals 214, 216 that periodically pulse or enable thepositive pump 240 and thereference generator 220, respectively, when they are in a standby mode. The clock signals 212, 214, 216 may each have a different frequency. - FIG. 3 is a simplified circuit diagram of a four stage triple well no body effect negative charge pump architecture of one embodiment. The four state
negative charge pump 300 of this embodiment comprises of four pump stages. The embodiment of FIG. 3 includes switchingtransistors N14 310,N24 330,N34 350,N44 370 connected in series betweenground 382 and VOUT 341. The switchingtransistors N14 310,N24 330,N34 350,N44 370 are preferably triple well N type field effect transistors. - The embodiment of FIG. 3 further includes pull-
down transistors N13 308,N23 328,N33 348,N43 368. The pull-down transistors N13 308,N23 328,N33 348,N43 368 are triple well N type field effect transistors in this embodiment. The source terminal of pull-down transistor N13 308,N23 328,N33 348,N43 368 is connected to the gate terminal of switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The pull-down transistors N13 308,N23 328,N33 348,N43 368 are diode connected, with the drain terminal and the gate terminal of each pull-down transistor N13 308,N23 328,N33 348,N43 368 connected to the drain terminal of the respectiveswitching transistor N14 310,N24 330,N34 350,N44 370. - The embodiment of FIG. 3 further includes pull-up
transistors N12 306,N22 326,N32 346,N42 366. The pull-uptransistors N12 306,N22 326,N32 346,N42 366 of this embodiment are triple well N type field effect transistors. The drain terminal of the pull-uptransistor N12 306,N22 326,N32 346,N42 366 is connected to the gate terminal of the switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The source terminal of the pull-uptransistor N12 306,N22 326,N32 346,N42 366 is connected to the drain terminal of the switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The gate terminal of the pull-uptransistor N12 306,N22 326,N32 346,N42 366 is connected to the source terminal ofcontrol device N11 304,N21 324,N31 344,N41 364, respectively. - Some existing charge pumps, such as a charge pump apparatus with diode connected pull-down on boot nodes, have pull-up devices whose gates are connected to the same boot node. In an existing pump scheme, the charge passing device or switching transistor cannot maintain its gate terminal voltage level when its drain terminal voltage drops down during charge transfer. The pull-up diode is gradually turned on in the process. This causes insufficient charge transfer for pump stages that have relatively low threshold voltage switching transistors. One solution is to turn off the pull-up transistor or pull-up diode during charge transfer so that the gate voltage of the switching transistor can be maintained.
- For this embodiment of the present invention, a control device serves as a switch between the gate and drain terminals of the pull-up transistor. The control device switches the pull-up transistor from being diode connected or not.
Control devices N11 304,N21 324,N31 344,N41 364 are N type field effect transistors in this embodiment. The drain terminal ofcontrol device N11 304,N21 324,N31 344,N41 364 is connected to the gate terminal of switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The gate terminal ofcontrol device N11 304,N21 324,N31 344,N41 364 is connected to the source terminal of switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. -
Control devices N11 304,N21 324,N31 344,N41 364 separate theboot node device N12 306,N22 326,N32 346,N42 366 respectively. The gate terminal of the triple wellN device N11 304,N21 324,N31 344,N41 364 connect to the nexthigher pump node N12 306,N22 326,N32 346,N42 366 from discharging theboot node CLOCK 1 386 orCLOCK 3 392, respectively. By controlling the discharge ofboot node device N12 306,N22 326,N32 346,N42 366, respectively, more gate drive is available to the chargetransfer device N14 310,N24 330,N34 350,N44 370. Thus more charge can be passed from one pump stage to the next high pump stage. - Also included in the embodiment of FIG. 3 are
storage capacitors C12 312,C22 332,C32 352,C42 372.Storage capacitor C12 312 is connected between aCLOCK 2 388 signal and the source terminal of switchingtransistor N14 310.Storage capacitor C22 332 is connected between aCLOCK 4 392 signal and the source terminal of the switchingtransistor N24 330.Storage capacitor C32 352 is connected between aCLOCK 2 388 signal and the source terminal of switchingtransistor N34 350.Storage capacitor C42 372 is connected between aCLOCK 4 392 signal and the source terminal of switchingtransistor N44 370. - The embodiment of FIG. 3 further includes boot
node capacitors C11 302,C21 322,C31 342,C41 362. Bootnode capacitor C11 302 is connected between aCLOCK 1 386 signal and the gate terminal ofN14 310. Bootnode capacitor C21 322 is connected between aCLOCK 3 392 signal and the gate ofN24 330. Bootnode capacitor C31 342 is connected between aCLOCK 1 386 signal and the gate ofN34 350. Bootnode capacitor C41 362 is connected between aCLOCK 3 392 signal and the gate ofN44 370. For this embodiment, the clock signals 386, 388, 392, 394 are generated by a four phase clock driver which takes its input from an oscillator circuit as in FIG. 2. - The triple negative well no body effect
negative charge pump 300 of this embodiment includes well biasingdevices N15 314,N16 316,N25 334,N26 336,N35 354,N36 356,N45 374,N46 376. The well biasing devices switching and initiate the P well potential of the triple well N type devices to eliminate body effect. The P well switching can also prevent P-N junctions from being turned on to induce latch up. For semiconductor process of one embodiment, the VtN drop is 0.6 volts versus the Vtp of 2.2 volts with a 12 volt body effect when outputting −12V. The drain terminals of the well biasing devices in each individual pump stage are tied together with the substrate terminals of the N type devices of that stage. The substrate terminals described in this embodiment are also referred to as the P-well connection of the N type devices. - The drain terminals of
N15 314 andN16 316 are coupled together with the substrate terminals ofN11 304,N12 306,N13 308,N14 310,N15 314, andN16 316 in thefirst pump stage 390. The drain terminals ofN25 334 andN26 336 are coupled together with the substrate terminals ofN21 324,N22 326,N23 328,N24 330,N25 334, andN26 336 in the second pump stage. The drain terminals ofN35 354 andN36 356 are coupled together with the substrate terminals ofN31 344,N32 346,N33 348,N34 350,N35 354, andN36 356 in the third pump stage. The drain terminals ofN45 374 andN46 376 are coupled together with the substrate terminals ofN41 364,N42 366,N43 368,N44 370,N45 374, andN46 376 in the fourth pump stage. - The gate terminal of
N15 314,N25 334,N35 354,N45 374 is connected to the gate terminal of switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The gate terminal ofN16 316,N26 336,N36 356,N46 376 is connected to the source terminal of switchingtransistor N14 310,N24 330,N34 350,N44 370, respectively. The source terminal ofN15 314,N25 334,N35 354,N45 374 is connected to the source terminal of switchingdevice N14 310,N24 330,N34 350,N44 370, respectively. The source terminal ofN16 316,N26 336,N36 356,N46 376 is connected to the drain terminal of switchingdevice N14 310,N24 330,N34 350,N44 370, respectively. The wellbiasing devices N15 314,N25 334,N35 354,N45 374 andN16 316,N26 336,N36 356,N46 376 alternately switch the potential on the substrates terminals between the voltage potential at the drain terminal and that at the source terminal of the respective switching device of that pump stage. Use of a triple well can reduce the stress voltage inside one embodiment of a negative pump cell to −13 volts in comparison with the -16 volt stress of some existing pump cells. -
Nodes Node 301 is defined by the connection ofstorage capacitor C12 312, the source terminal of switchingtransistor N14 310, the gate terminal ofcontrol device N11 304, and the gate and drain terminals oftransistor N1 396.Ground 382 is connected to the source terminal ofN1 396.Node 311 is defined by the connection ofC22 332, the source terminal ofN24 330, the gate terminal ofN21 324, the drain terminal ofN14 310, the gate and drain terminals ofN13 308, and the source terminal ofN12 306.Node 331 is defined by the connection ofC32 352, the source terminal ofN34 350, the gate terminal ofN31 344, the drain terminal ofN24 330, the gate and drain terminals ofN23 328, and the source terminal ofN22 326.Node 351 is defined by the connection ofC42 372, the source terminal ofN34 350, the gate terminal ofN41 364, the drain terminal ofN34 350, the gate and drain terminals ofN33 348, and the source terminal ofN32 346.Node 371 is defined by the connection of the source terminal ofN44 370, the gate and drain terminals ofN43 368, and the source terminal ofN42 366. -
Boot nodes Boot node 305 is defined by the connection of theboot capacitor C11 302, the gate terminal of switchingtransistor N14 310, the source terminal of pull-down transistor N13 308, the drain terminal of pull-uptransistor N12 306, and the drain terminal ofcontrol device N11 304.Boot node 325 is defined by the connection ofC21 322, the gate terminal ofN24 330, the source terminal ofN23 328, the drain terminal ofN22 326, and the drain terminal ofN21 324.Boot node 345 is defined by the connection ofC31 342, the gate terminal ofN34 350, the source terminal ofN33 348, the drain terminal ofN32 346, and the drain terminal ofN31 344.Boot node 365 is defined by the connection ofC41 362, the gate terminal ofN44 370, the source terminal ofN43 368, the drain terminal ofN42 366, and the drain terminal ofN41 364. - The embodiment of FIG. 3 includes four negative charge pump stages. One of these stages is labeled as
stage 390, and includes thestorage capacitor C12 312, the switchingtransistor N14 310, the pull-down transistor N13 308, the pull-uptransistor N12 306, thecontrol device N11 304, and the bootnode capacitor C11 302.Stage 390 receives its input fromground 386 via diode connectedtransistor N1 396. The output of this charge pump embodiment is labeled asVOUT 371. Positive charge is transferred in the direction fromnode 371 toground 382. - Although the negative charge pump embodiment of FIG. 3 includes four stages, other numbers of stages are possible. Furthermore, the same techniques and teachings of the present invention can be applied to other applications wherein a negative voltage potential is needed to be generated internally. The present invention can be used in a variety of charge pumps to improve the output current and pumping efficiency. The increased output and efficiency may also lead to die size savings if the pump area of the charge pumps can be reduced as a result. Embodiments of the triple well negative pump architecture of the present invention may also offer power savings over existing pump designs.
- FIG. 4 shows a timing diagram of the pump clocking waveforms used in connection with the negative charge pump of FIG. 3. The clock signals
CLOCK 1 410, CLOCK 2420,CLOCK 3 430,CLOCK4 440 control the operation of this embodiment of a triple wellnegative charge pump 300. For this embodiment, all of the clock signals 410, 420, 430, 440 are at VCC level when high and at ground potential when low. VCC level varies depending on the particular embodiment and could possibly be 3V, 1.8V, or 1.55V. Unlike other negative charge pumps, an embodiment of the present pump architecture no longer needs to have a positive charge pump to supply the negative pump for boot clocking when operating at a 1.55 volt power supply. - The pumping operation can be abbreviated as the following steps and the repeat of those steps to generate currents. The following discussion will concentrate on the operation of
pump 300 beginning with the first low-to-high transition ofCLOCK 4 440 at time T1. WhenCLOCK4 440 is high, the potential atnode 351 is boosted high. The high potential atnode 351 pre-charges theboot node 345 of the third stage throughN33 348 and turns onN41 364. AsN41 364 turns on,N42 366 is activated to dischargeboot node 365 of the fourth stage and turn offN44 370 to prevent back conductance betweennode 351 andnode 371.N46 376 is turned on to short Pwell terminals 369 tonode 371, which prevents the P well to N diffusion junctions of the triplewell devices N42 366,N43 368,N44 370,N46 376 from turning on. WhenCLOCK 2 420 transitions low, the voltage potential atnode 331 drops low to be ready to receive charge fromC42 372 atnode 351 and turns offN31 344. WhenCLOCK 1 410 transitions high,boot node 345 goes high andN34 350 gets turned on. Charge is transferred fromC42 372 atnode 351 throughN34 350 toC32 352 atnode 331. The voltage potential atnode 351 decreases while the potential atnode 331 increases.N35 354 is turned on to short Pwell terminals 349 tonode 331, which prevents the P well to N diffusion junctions of the triplewell devices N34 350,N35 354 from turning on. AsCLOCK 1 410 transitions back to a logic low, the charge transfer fromnode 351 tonode 331 stops and the voltage level on the nodes level out. - When
CLOCK 2 420 goes high, the voltage potential atnode 331 also goes high.C21 322 onboot node 325 is pre-charged byC32 352 throughN23 328. The high potential onnode 331 also turns onN31 344, which activatesN32 346 to dischargeboot node 345. Dischargingboot node 345 turns offN34 350 to prevent back conductance betweennode 331 andnode 351.N36 356 is turned on to short Pwell terminals 349 tonode 331, which prevents the P well to N diffusion junctions of the triplewell devices N32 346,N33 348,N34 350,N35 356 from turning on. WhenCLOCK 4 440 transitions low at time T3, the voltage potential onC22 332 atnode 311 drops low in order to be ready to receive charge fromC32 352 atnode 331. A low onCLOCK 4 440 also turns offN21 324. - As
CLOCK 3 430 transitions high during time T3,boot node 325 of the second stage also goes high. Ahigh CLOCK 3 430 turns on switchingtransistor N24 330. Charge is transferred fromC32 352 throughN24 330 toC22 332, causing the voltage potential onnode 331 to drop and the potential onnode 311 to rise.N25 334 is turned on to short Pwell terminals 329 tonode 311, which prevents the P well to N diffusion junctions of the triplewell devices N24 330,N25 334 from turning on. WhenCLOCK 3 430 goes low during time T4, the charge transfer stops. The potentials onnode 331 andnode 311 level out. The cycle repeats with the low to high transition ofCLOCK 4 440 at time T4. - The embodiment of FIG. 3 eliminates of the requirement of overlapping clock periods typically found with prior charge pump circuits. Overlapping clock periods are not required in the embodiment of FIG. 3 because the voltage on the
boot nodes nodes - Although the clocks signals410, 420, 430, 440 of FIG. 4 are shown to overlap, in other words no two clock edges are shown to occur simultaneously, there is no requirement for the clocks to overlap. Clock edges may occur nearly simultaneously, although a small overlap, preferably approximately 2 nanoseconds for one embodiment, may be used in order to account for the non-vertical nature of clock edges.
- FIG. 5 is a plot of the voltage potential outputted from the fourth stage of the negative
charge pump embodiment 300 of FIG. 3. The plot indicates the voltage potential atnode 351 during the operation of thepump 300. The resulting output waveform fromnode 351 corresponds to the operation ofpump 300 with the clock signals 410, 420, 430, 440 of FIG. 4. The voltage ramp labeled V351 indicates the potential transferred fromVOLT 371 tonode 351 whenN44 370 is turned on by ahigh CLOCK 3 386. Note that whenCLOCK 3 386 is high,node 351 is charged up to a VCC level. AsCLOCK 4 388 goes high,node 351 is boosted from a VCC to 2VCC. WhenCLOCK 1 391 goes high,N34 350 turns on to transfer charge fromnode 351 tonode 331. The voltage drop labeled by ΔV indicates the amount of potential that is transferred from the fourth stage 590 to the third stage. AsCLOCK 4 388 goes low,node 351 is no longer boosted and the potential drops back to a low value. The cycle then repeats. - FIG. 6 is a flow diagram illustrating the method of eliminating body effect in a negative charge pump for one embodiment. This example generally describes the operation of one negative pump stage. At
step 602, a boot node is precharged. The boot node discharge mechanism is disabled atstep 604. This discharge mechanism can be viewed as the pull-down device as in the pump cells of FIG. 3. The substrate of one or more of the N type transistor devices in the pump cell is biased atstep 606. This biasing prevents the P well to N diffusion junctions in the N type device from turning on during charge transfer. Atstep 608, a logic high level is driven on the boot node to allow charge transfer to occur. This charge transfer can be related to the charge being passed from a storage capacitor of an earlier stage through a switching device over to a storage capacitor of a subsequent stage. A logic low level is driven on the boot node atstep 610 to stop the charge transfer. Atstep 612, the boot node discharge mechanism is enabled to fully turn off the charge passing device. Atstep 614, the substrate of one or more of the N type transistor devices in the subsequent pump cell is biased to prevent the P well to N diffusion junctions in those N type devices from turning on during charge transfer in that cell. - The cycle from
step 602 to step 614 repeat again and again to continually pass charge from the input of the pump cell to the output of the pump cell. The operation of subsequent pump cells in the charge pump operate in a similar manner, but the clocking are timed differently between adjacent cells in order to properly pump up the voltage. - In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereof without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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