US20020068378A1 - Metal foil laminated ic package - Google Patents
Metal foil laminated ic package Download PDFInfo
- Publication number
- US20020068378A1 US20020068378A1 US09/730,440 US73044000A US2002068378A1 US 20020068378 A1 US20020068378 A1 US 20020068378A1 US 73044000 A US73044000 A US 73044000A US 2002068378 A1 US2002068378 A1 US 2002068378A1
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- US
- United States
- Prior art keywords
- contact pads
- ring
- etching
- plating
- dies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 13
- 239000011888 foil Substances 0.000 title description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 27
- 239000010949 copper Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000007747 plating Methods 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 238000003491 array Methods 0.000 claims abstract description 5
- 239000011889 copper foil Substances 0.000 claims abstract description 5
- 239000011152 fibreglass Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract 7
- 238000010030 laminating Methods 0.000 claims abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 21
- 239000004593 Epoxy Substances 0.000 claims description 9
- 238000003486 chemical etching Methods 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 238000010276 construction Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present invention relates generally to packaging for integrated circuit (IC) devices, and in particular to a method of fabricating a metal foil laminated package for ball grid arrays.
- PBGA Pin-Ball Grid Array
- TBGA Tape Ball Grid Array
- Additional prior art packages include the well known Super BGA package which has an organic substrate attached to a metal backing.
- the organic layer between the I/O balls and the thermal grounding of the heatsink results in severe limitations to the conduction of heat flowing to the balls from the metal backing.
- the prior art ProlinxTM BGA and STITM BGA are built up structures over metal backings wherein the built up layered structures include silver filled epoxy to act as a layer-to-layer interconnect.
- the built up layered structures include silver filled epoxy to act as a layer-to-layer interconnect.
- they require machined cavities and complex routing techniques which reduce cost effectiveness. From a cost point of view, these products are considered to be expensive, and require very specialized construction techniques to fabricate them.
- an IC package having a laminate substrate design built using copper sheet instead of the glass reinforced resin normally used.
- the metal foil laminated package of the present invention eliminates the requirement for expensive polyimide tape.
- a further advantage of the IC package of the present invention is that the accuracy of the artwork relative to the die attach cavity is an inherent feature of the way the package is manufactured. This precludes any alignment inaccuracies of tape to heatsink attachment which can cause problems in prior art.
- multiple trace layers are provided for interconnection between levels by means of laser drilled vias and a post plating interconnect.
- some of the external I/O balls of the package are short circuited to the heatsink to act as a close loop ground.
- the ground path is short circuited via wire bond to the ground trace on the routed metal of the interconnect structure of the package and also to the ground pads of the IC device.
- FIGS. 1 and 2 show the fabrication of a three-layer laminated carrier according to a first step in creating the IC package of the present invention
- FIGS. 3 shows the three-layer laminated carrier of FIG. 2 subjected to a standard image transfer process for defining contact pads
- FIGS. 4A and 4B show the three-layer laminated carrier of FIG. 2 incorporating a close loop ground with etched vias at the pad on the ball and ring area (FIG. 4A), or a via constituting the entire ring (FIG. 4B);
- FIGS. 5A and 5B show the structures of FIGS. 4A and 4B, respectively, having the blind via holes plated up with copper and then filled with epoxy ink;
- FIGS. 6A and 6B show the structures of FIGS. 4A and 4B, respectively, subjected to a standard image transfer process for defining contact pads
- FIGS. 7, 7A and 7 B show the structures of FIGS. 3, 6A and 6 B, respectively, with application of a solder mask and plating up for subsequent wire bonding;
- FIGS. 8, 8A and 8 B show the formation of window openings and singulation of the structures of FIGS. 7, 7A and 7 B, respectively, and attachment of a heat sink thereto;
- FIGS. 9, 9A and 9 B show the finished packages for FIGS. 8, 8A and 8 B after die attach, wire bonding, encapsulation, and solder ball attach;
- FIG. 10 shows an alternative one-piece construction of the IC package according to the present invention.
- a copper plate 1 is laminated with copper foil and B stage epoxy in fiberglass prepreg format. This is similar to the preparation for printed circuit boards in PCB industry with the exception that PCB industry laminates the copper foils on fiberglass backings rather than copper sheet material.
- An additional step may include lamination of the copper sheet with a RCC (resin coated copper) foil. Again, this is similar to PCB assembly practice. In any event a three-layer laminated carrier results (FIG. 2).
- process flow may proceed either immediately to a standard image transfer process (FIG. 3), or to a closed loop construction wherein vias are etched at the contact pads on the ball and ring area (FIG. 4A), or vias forming a direct ring on the copper plate 1 , as shown in FIG. 4B).
- a standard image transfer process FIG. 3
- a closed loop construction wherein vias are etched at the contact pads on the ball and ring area (FIG. 4A), or vias forming a direct ring on the copper plate 1 , as shown in FIG. 4B).
- laser ablation is used to create the vias followed by plating up the blind via holes with copper and then filling of the holes with epoxy ink (either conductive or non-conductive), as shown in FIGS. 5A and 5B.
- the image transfer process is applied, resulting in the closed loop configurations of FIGS. 6A and 6B
- FIGS. 7, 7A and 7 B (which follow FIGS. 3, 6A and 6 B, respectively), a solder mask is applied and all exposed areas are plated up with Ni/Au or other wire bondable metal surface (e.g. silver) for subsequent wire bonding and solder ball joints.
- the exposed ring on the copper plate is also Ni/Au plated (i.e. the ring functions as a direct GND ring).
- FIGS. 8, 8A and 8 B the process flow continues with formation of window openings.
- the window cavities may be created either by chemical etching, mechanical milling, or mechanical down-set.
- a standard assembly process is then followed, including die attach, wire bonding, encapsulation, and solder ball attach, resulting in the finished packages of FIG. 9 (standard configuration with no vias), FIG. 9A (close loop configuration with ring on substrate short circuited to heat sink through vias), and FIG. 9B (close loop configuration with ring directly on heat sink).
- the entire substrate is attached via epoxy or adhesive film to a piece of black oxidized copper or similar plate 7 , which functions as a heat spreader.
- FIGS. 1 - 9 It will be understood by a person of ordinary skill in the art that, for ease of illustration only a single IC package is depicted in FIGS. 1 - 9 , whereas in practice a matrix of such IC packages are gang fabricated on the black oxide heat spreader 7 using the lamination and etching steps set forth above. The gang fabricated product is thereafter singulated into individual IC packages either by sawing, routing or punching.
- FIG. 10 According to the alternative embodiment of FIG. 10, a one-piece construction is provided which is identical to the two-piece construction of FIGS. 1 - 9 , with the exception that the copper plate 1 is much thicker so that a separate copper heat spreader 7 is not required.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
- The present invention relates generally to packaging for integrated circuit (IC) devices, and in particular to a method of fabricating a metal foil laminated package for ball grid arrays.
- As thermal and electrical requirements of IC packages become more demanding, advanced forms of package construction have been developed. In general, array packaging such as Pin-Ball Grid Array (PBGA) provides for a high density of interconnects relative to the surface area of the package. However, typical PBGA packages are characterized by a convoluted signal path, giving rise to high impedances and an inefficient thermal path which results in low thermal dissipation performance.
- Applicants' prior Tape Ball Grid Array (TBGA) product is an advanced IC package having straight signal paths and a copper backed, die down construction which enjoys enhanced performance over prior art PBGA packages. However, this TBGA design suffers from complex construction in which heatsinks are precisely laminated to the substrate with expensive polyimide tape in a post etch operation. Further, the presence of polyimide between the heatsink and the copper traces of the tape minimizes the effectiveness of routing the traces in close proximity to the grounded heatsink.
- Additional prior art packages include the well known Super BGA package which has an organic substrate attached to a metal backing. However, the organic layer between the I/O balls and the thermal grounding of the heatsink results in severe limitations to the conduction of heat flowing to the balls from the metal backing.
- Similarly, the prior art Prolinx™ BGA and STI™ BGA are built up structures over metal backings wherein the built up layered structures include silver filled epoxy to act as a layer-to-layer interconnect. However, they require machined cavities and complex routing techniques which reduce cost effectiveness. From a cost point of view, these products are considered to be expensive, and require very specialized construction techniques to fabricate them. p Further examples of prior art Tab Grid Arrays are described in:
- U.S. Pat. No. 5,397,921 issued Mar. 14, 1995;
- U.S. Pat. No. 5,409,865 issued Apr. 25, 1995;
- U.S. Pat. No. 5,843,808 issued Dec. 1, 1998.
- According to one aspect of the present invention there is provided an IC package having a laminate substrate design built using copper sheet instead of the glass reinforced resin normally used. The metal foil laminated package of the present invention eliminates the requirement for expensive polyimide tape. A further advantage of the IC package of the present invention is that the accuracy of the artwork relative to the die attach cavity is an inherent feature of the way the package is manufactured. This precludes any alignment inaccuracies of tape to heatsink attachment which can cause problems in prior art. According to a further aspect of the invention, multiple trace layers are provided for interconnection between levels by means of laser drilled vias and a post plating interconnect. These features offer enhanced routing density and electrical performance when compared to single layer designs.
- In one embodiment, some of the external I/O balls of the package are short circuited to the heatsink to act as a close loop ground. The ground path is short circuited via wire bond to the ground trace on the routed metal of the interconnect structure of the package and also to the ground pads of the IC device.
- A preferred embodiment of the present invention will now be described more fully with reference to the following Figures, in which:
- FIGS. 1 and 2 show the fabrication of a three-layer laminated carrier according to a first step in creating the IC package of the present invention;
- FIGS.3 shows the three-layer laminated carrier of FIG. 2 subjected to a standard image transfer process for defining contact pads;
- FIGS. 4A and 4B show the three-layer laminated carrier of FIG. 2 incorporating a close loop ground with etched vias at the pad on the ball and ring area (FIG. 4A), or a via constituting the entire ring (FIG. 4B);
- FIGS. 5A and 5B show the structures of FIGS. 4A and 4B, respectively, having the blind via holes plated up with copper and then filled with epoxy ink;
- FIGS. 6A and 6B show the structures of FIGS. 4A and 4B, respectively, subjected to a standard image transfer process for defining contact pads;
- FIGS. 7, 7A and7B show the structures of FIGS. 3, 6A and 6B, respectively, with application of a solder mask and plating up for subsequent wire bonding;
- FIGS. 8, 8A and8B show the formation of window openings and singulation of the structures of FIGS. 7, 7A and 7B, respectively, and attachment of a heat sink thereto;
- FIGS. 9, 9A and9B show the finished packages for FIGS. 8, 8A and 8B after die attach, wire bonding, encapsulation, and solder ball attach; and
- FIG. 10 shows an alternative one-piece construction of the IC package according to the present invention.
- With reference to FIG. 1, a
copper plate 1 is laminated with copper foil and B stage epoxy in fiberglass prepreg format. This is similar to the preparation for printed circuit boards in PCB industry with the exception that PCB industry laminates the copper foils on fiberglass backings rather than copper sheet material. An additional step may include lamination of the copper sheet with a RCC (resin coated copper) foil. Again, this is similar to PCB assembly practice. In any event a three-layer laminated carrier results (FIG. 2). - From this laminated structure, process flow may proceed either immediately to a standard image transfer process (FIG. 3), or to a closed loop construction wherein vias are etched at the contact pads on the ball and ring area (FIG. 4A), or vias forming a direct ring on the
copper plate 1, as shown in FIG. 4B). For the closed loop construction of FIGS. 4A and 4B, laser ablation is used to create the vias followed by plating up the blind via holes with copper and then filling of the holes with epoxy ink (either conductive or non-conductive), as shown in FIGS. 5A and 5B. Next, the image transfer process is applied, resulting in the closed loop configurations of FIGS. 6A and 6B - In FIGS. 7, 7A and7B (which follow FIGS. 3, 6A and 6B, respectively), a solder mask is applied and all exposed areas are plated up with Ni/Au or other wire bondable metal surface (e.g. silver) for subsequent wire bonding and solder ball joints. For the close loop configuration of FIGS. 7A and 7B, the exposed ring on the copper plate is also Ni/Au plated (i.e. the ring functions as a direct GND ring).
- In FIGS. 8, 8A and8B, the process flow continues with formation of window openings. The window cavities may be created either by chemical etching, mechanical milling, or mechanical down-set. A standard assembly process is then followed, including die attach, wire bonding, encapsulation, and solder ball attach, resulting in the finished packages of FIG. 9 (standard configuration with no vias), FIG. 9A (close loop configuration with ring on substrate short circuited to heat sink through vias), and FIG. 9B (close loop configuration with ring directly on heat sink). The entire substrate is attached via epoxy or adhesive film to a piece of black oxidized copper or similar plate 7, which functions as a heat spreader.
- It will be understood by a person of ordinary skill in the art that, for ease of illustration only a single IC package is depicted in FIGS.1-9, whereas in practice a matrix of such IC packages are gang fabricated on the black oxide heat spreader 7 using the lamination and etching steps set forth above. The gang fabricated product is thereafter singulated into individual IC packages either by sawing, routing or punching.
- According to the alternative embodiment of FIG. 10, a one-piece construction is provided which is identical to the two-piece construction of FIGS.1-9, with the exception that the
copper plate 1 is much thicker so that a separate copper heat spreader 7 is not required. - Alternatives and variations of the invention are possible. All such embodiments and modifications are believed to be within the sphere and scope of the invention as defined by the claims appended hereto.
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/730,440 US6429048B1 (en) | 2000-12-05 | 2000-12-05 | Metal foil laminated IC package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US09/730,440 US6429048B1 (en) | 2000-12-05 | 2000-12-05 | Metal foil laminated IC package |
Publications (2)
Publication Number | Publication Date |
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US20020068378A1 true US20020068378A1 (en) | 2002-06-06 |
US6429048B1 US6429048B1 (en) | 2002-08-06 |
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Family Applications (1)
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US09/730,440 Expired - Lifetime US6429048B1 (en) | 2000-12-05 | 2000-12-05 | Metal foil laminated IC package |
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US (1) | US6429048B1 (en) |
Cited By (4)
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US20020093025A1 (en) * | 2000-12-29 | 2002-07-18 | Malone Joshua J. | Laminated micromirror package |
US20070066045A1 (en) * | 2005-09-22 | 2007-03-22 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing substrate with cavity |
CN102427667A (en) * | 2011-11-09 | 2012-04-25 | 金悦通电子(翁源)有限公司 | Machining process of half-pore plate |
US9559036B1 (en) | 2014-08-01 | 2017-01-31 | Altera Corporation | Integrated circuit package with plated heat spreader |
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US7015072B2 (en) | 2001-07-11 | 2006-03-21 | Asat Limited | Method of manufacturing an enhanced thermal dissipation integrated circuit package |
US6734552B2 (en) | 2001-07-11 | 2004-05-11 | Asat Limited | Enhanced thermal dissipation integrated circuit package |
US6790710B2 (en) * | 2002-01-31 | 2004-09-14 | Asat Limited | Method of manufacturing an integrated circuit package |
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US8492906B2 (en) | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
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US8461694B1 (en) | 2006-04-28 | 2013-06-11 | Utac Thai Limited | Lead frame ball grid array with traces under die having interlocking features |
US8013437B1 (en) | 2006-09-26 | 2011-09-06 | Utac Thai Limited | Package with heat transfer |
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US5843808A (en) | 1996-01-11 | 1998-12-01 | Asat, Limited | Structure and method for automated assembly of a tab grid array package |
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Cited By (12)
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US20020093025A1 (en) * | 2000-12-29 | 2002-07-18 | Malone Joshua J. | Laminated micromirror package |
US6917461B2 (en) * | 2000-12-29 | 2005-07-12 | Texas Instruments Incorporated | Laminated package |
US20050237598A1 (en) * | 2000-12-29 | 2005-10-27 | Malone Joshua J | Laminated package |
US7345807B2 (en) | 2000-12-29 | 2008-03-18 | Texas Instruments Incorporated | Laminated package |
US7843643B2 (en) | 2000-12-29 | 2010-11-30 | Texas Instruments Incorporated | Laminated micromirror package |
US20110058246A1 (en) * | 2000-12-29 | 2011-03-10 | Texas Instruments Incorported | Laminated Micromirror Package |
US8792179B2 (en) | 2000-12-29 | 2014-07-29 | Texas Instruments Incorporated | Laminated micromirror package |
US20070066045A1 (en) * | 2005-09-22 | 2007-03-22 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing substrate with cavity |
US7498205B2 (en) | 2005-09-22 | 2009-03-03 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing substrate with cavity |
DE102006044369B4 (en) * | 2005-09-22 | 2010-01-07 | Samsung Electro-Mechanics Co., Ltd., Suwon | Method for producing a substrate with a cavity |
CN102427667A (en) * | 2011-11-09 | 2012-04-25 | 金悦通电子(翁源)有限公司 | Machining process of half-pore plate |
US9559036B1 (en) | 2014-08-01 | 2017-01-31 | Altera Corporation | Integrated circuit package with plated heat spreader |
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