US20020067632A1 - Dram cam cell with hidden refresh - Google Patents
Dram cam cell with hidden refresh Download PDFInfo
- Publication number
- US20020067632A1 US20020067632A1 US09/730,673 US73067300A US2002067632A1 US 20020067632 A1 US20020067632 A1 US 20020067632A1 US 73067300 A US73067300 A US 73067300A US 2002067632 A1 US2002067632 A1 US 2002067632A1
- Authority
- US
- United States
- Prior art keywords
- pass
- cam
- bit
- line
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001066 destructive effect Effects 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000001514 detection method Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 45
- 238000013500 data storage Methods 0.000 claims description 40
- 238000003860 storage Methods 0.000 claims description 17
- 230000002452 interceptive effect Effects 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 1
- 210000004027 cell Anatomy 0.000 description 94
- 230000005055 memory storage Effects 0.000 description 16
- 230000006870 function Effects 0.000 description 15
- 238000012546 transfer Methods 0.000 description 15
- 210000000352 storage cell Anatomy 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 101100153525 Homo sapiens TNFRSF25 gene Proteins 0.000 description 7
- 102100022203 Tumor necrosis factor receptor superfamily member 25 Human genes 0.000 description 7
- 102000000582 Retinoblastoma-Like Protein p107 Human genes 0.000 description 3
- 108010002342 Retinoblastoma-Like Protein p107 Proteins 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 208000023514 Barrett esophagus Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
- G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Definitions
- the invention relates generally to semiconductor memory devices, and more specifically to a Dynamic Content Addressable Memory (DCAM) Cell.
- DCAM Dynamic Content Addressable Memory
- Modern telecommunication networks comprise digital data networks that transmit data in packets or blocks containing address fields for dynamically routing the data packets or blocks through the network (e.g., to the destination address) at high speeds.
- the fastest searching of stored data may be accomplished using a Content Addressable Memory (CAM).
- CAM Content Addressable Memory
- CAM arrays of the related art are generally implemented with either conventional Static RAM (SRAM) or conventional destructive-read Dynamic RAM (DRAM) hardware designs, and therefore have all the disadvantages and limitations of one such hardware design or the other.
- SRAM Static RAM
- DRAM destructive-read Dynamic RAM
- a typical ternary Static CAM (SCAM) of the relate art contains two six-transistor SRAM storage cells plus an XNOR functional group containing four additional transistors, thus a total of 16 transistors per SCAM cell.
- An SCAM is generally more vulnerable than a DCAM to corruption of stored data by Soft-Errors (e.g., stored data errors due to exposure of circuits to ambient radiation).
- a typical ternary Dynamic CAM (DCAM) cell of the related art may contain fewer transistors than an SCAM, but may have disadvantages including destructive-reads and slower performance.
- a typical ternary DCAM of the related art includes two data storage capacitors that must be periodically read and refreshed by charge-transfer via pass-transistors that are also used for reading and writing data by charge-transfer, in addition to an XNOR comparison circuit containing four transistors.
- the charge stored in the data storage capacitors of a DCAM cell is gradually dissipated by leakages within the cell. For this reason, the information stored in the leaking capacitors must be periodically “refreshed,” i.e., the charge is read and then re-written back into the storage cell.
- the related art provides various DCAM cell structures that are limited in that refresh-reads proceed by charge-transfer thus destroying the data stored in the data-storage capacitors, making the DCAM cell temporarily unavailable for CAM searches until the data is written back into the DCAM cell by a refresh-write.
- the entire refresh read-write period thereof generally occupies time during which CAM searches can not be performed.
- limitations of the ability to sense the relatively small charge-transfer from the storage capacitor to a capacitive bit-line coupled thereto limits the maximum array population on such bit-lines, and/or requires larger storage capacitors.
- FIG. 1 An example of such a destructive-read DCAM is disclosed in U.S. Pat. No. 5,949,696 issued to Threewitt.
- a read operation for a refresh of the DCAM circuit of the related art depicted in FIG. 1 is performed by charge transfer of the charge stored in a data storage capacitor (e.g. SB 0 or SB 1 ) through a pass-transistor (e.g., T 0 R or T 1 R, respectively) and through a bit line (e.g. NBIT or BIT, respectively).
- a data storage capacitor e.g. SB 0 or SB 1
- a pass-transistor e.g., T 0 R or T 1 R, respectively
- bit line e.g. NBIT or
- the present invention provides, among other things, an improved Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer than the 16 transistors of the typical Static Content Addressable Memory (SCAM) of the related art, but that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance.
- DCAM Dynamic Content Addressable Memory
- SCAM Static Content Addressable Memory
- the inventive DCAM achieves its search performance by simultaneously comparing all entries stored in the memory with an externally applied “comparand.” Words stored in entries in the CAM, which “match” the comparand result in maintaining the non-conductive barrier preventing charge transfer between their respective Match Lines and ground.
- Embodiments of the invention provide a non-destructive read operation, such that the stored-data does not have to be written back because of a refresh-read operation; and a reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back.
- Soft-error detection processes well known to persons skilled in the art may be performed on each CAM entry during the pendency of the refresh cycle (or independent of the refresh cycle) without delaying or interrupting CAM search operations.
- Embodiments of the invention provide CAM cell circuit topologies that can allow more CAM cells to be tied to a read-bit-line of a CAM array than may be tied to a read-bit-line of a DCAM array the related art, thus resulting in greater array utilization.
- a first aspect of the invention provides a digital system that performs the function of a network router, and a CAM array having a CAM cell including: a data storage device; a pass-gate including a stack of first and a second pass-switches, the First Pass-Switch being coupled to in series with the Second Pass-Switch at a Node; a Data Storage Device operatively controlling the Second Pass-Switch; and a Third Pass-Switch connected to the Node for detecting the logic state of the Data Storage Device.
- a second aspect of the invention provides a method for performing a plurality of CAM searches in a CAM array having a CAM entry that has a word of searchable data stored in a plurality of storage capacitors, comprising the steps of performing a non-destructive determination of the word and subsequently performing a CAM search.
- FIG. 1 is a block circuit diagram of a destructive-read DCAM cell of the related art.
- FIG. 2A is a circuit diagram of a DCAM cell that supports non-destructive reads and “hidden” refresh of searchable stored data in accordance with embodiments of the invention.
- FIG. 2B is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing.
- FIG. 2C is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing, and separate search lines are provided.
- FIG. 3 is a timing diagram illustrating the timing relationships among devices, data and control signals and illustrating methods of operating the inventive DCAM cell of FIG. 2A.
- FIG. 4 depicts a representative digital system including a CAM array comprising a DCAM cell depicted in FIGS. 2A, 2B, or 2 C.
- FIG. 2A depicts a circuit diagram of a ternary Dynamic Content Addressable Memory (DCAM) cell 200 a in accordance with an embodiment of the present invention.
- the inventive ternary DCAM cell 200 a includes two capacitors (SB 0 and SB 1 ) that function as data storage devices. Each of these capacitors is independently charged High to store a logical One (“1”) or discharged Low to store a logical Zero (“0”).
- the ternary DCAM cell 200 a stores a “mask” state which allows a local mask logic value to be stored within a given word entry.
- each DCAM cell e.g., 200 a
- the ability to store a “mask” logic state in each DCAM cell (e.g., 200 a ) in a DCAM entry allows bit-level masking of data stored in an CAM array of DCAM cells.
- the bit-level masking facilitates and/or enables the storing and comparing of an address range using the present invention and is beneficial in, inter alia, network address filtering applications.
- Embodiments of the inventive DCAM cell comprise an Exclusive Negative OR (XNOR) logic function implemented by an XNOR Gate 202 (as shown in FIGS. 2A, 2B, 2 C) including four (4) transistors arranged in two parallel stacks of two (2) stacked transistors.
- Each transistor stack includes a first pass-switch (e.g. NFET transistor T 2 or T 3 ) and a second pass-switch (e.g. NFET transistor T 4 or T 5 ), the first pass-switch being coupled to in series with the second pass-switch at a node (e.g., N 0 or N 1 respectively).
- a node e.g., N 0 or N 1 respectively.
- each transistor stack (e.g., T 0 -T 2 and T 1 -T 3 ) of the XNOR Gate 202 functions physically independently of the other, is not necessary for proper logical operation of the DCAM that the two transistor stacks (e.g., T 0 -T 2 and T 1 -T 3 ) of one ternary DCAM cell 200 a be located physically adjacent to one another on the integrated circuit (IC) chip.
- the ternary DCAM cell 200 a may therefore be “split” in to “halves” (with other halved-DCAM cells disposed in between each such half), provided that all such half-DCAM cells are connected to the same Match Line of the CAM entry.
- the XNOR transistors coupled conductively to the Match Line are ideally OFF while the Match Line is pre-charged High, prior to each CAM search, the non-destructive read through pass-transistors (e.g., T 2 -T 7 , T 3 -T 6 ) may be performed prior to a CAM search and while the XNOR transistors coupled conductively to the Match Line (T 4 , T 5 ) are OFF.
- a non-destructive refresh-read operation may be “hidden” from the CAM search cycle in the sense that a refresh-read performed does not delay or prevent a subsequent CAM-search from being performed.
- a refresh-write can be performed following such a non-destructive refresh-read either, before, during or after the performance of a CAM search.
- connection of the DCAM cell's XNOR stacks to ground can be a direct connection as shown in FIG. 2A, or this connection can be selectively interruptible by the pass-switch (e.g. pass-transistor) of a “global” bit-mask (not shown).
- a “global” bit mask coupled to the XNOR circuit functions such that when a global bit-mask signal is asserted the corresponding bit position in every word stored in the CAM array is eliminated from the compare function (i.e., it becomes a global “don't care” (forced match) logic value for every word in the CAM array).
- Such global masking is useful in comparing or searching for ranges of data values stored in the CAM entries.
- the plurality of parallel transistor stacks (e.g., T 2 -T 4 and T 3 -T 5 ) of all the XNOR comparison circuits of all the CAM cells in a CAM entry form a Match-Line Pass-Gate.
- the Match Line Pass-Gate operates such that a pre-charged High Match Line will remain High in the case of a MATCH-ing entry, but will be discharged to or near ground voltage level (indicating a Miss) if any one or more ternary bits stored in the CAM entry mis-matches the corresponding bit of the comparand.
- the Match Line Pass-Gate and the DCAM cell of the present invention will also support a pre-charged-Low Match Line in a match-detection system, such as is disclosed in U.S. patent application of Towler et. als., Ser. No. ______ filed, ______, 2000, the relevant portions of which are incorporated herein by reference, wherein the subject matter and the claimed invention were at the time the invention was made, owned by, or subject to, an obligation for assignment to International Business Machines Corp, which is the assignee of the present invention.
- the writing and reading of data into or from the memory storage cells ( 210 a and 211 a ) can be performed by charge-transfer, as in the related art DCAMs, through the bit lines (BL 0 and BL 1 respectively) and through pass-transistors (T 0 and T 1 respectively) held ON (i.e., conducting) when the Word-Line WL is held High.
- the method of writing or reading data by charge-transfer in the present invention is the same or similar as the method of writing and reading by charge-transfer used in DCAMs of the related art.
- reading by charge-transfer is unnecessary in embodiments of the present invention because the present invention enables the reading of stored data without destructive charge-transfer of the charge stored in the data storage capacitors (e.g., SB 0 and SB 1 ).
- a non-destructive read may be performed at each memory storage cell (e.g., 210 a , 211 a ) of DCAM cell 200 a , while the respective search line (e.g., SLC or SLT) is held Low, by pre-charging the respective Bit-Line (e.g., BL 0 , BL 1 respectively) to a High logic voltage, and then turning the pass-transistor (e.g., T 7 , T 6 respectively) ON (i.e., conducting) by asserting a High logic voltage on the gate thereof (e.g., by asserting a High logic voltage on the Read-Word Line (RWL)), and then sensing a current and/or a voltage on the respective Bit-Line (e.g., BL 0 , BL 1 ) that is representative of the state of the respective data storage device (e.g., SB 0 and SB 1 respectively).
- the respective search line e.g., SLC or SLT
- the Bit-Lines may be pre-charged High through a plurality of pass-switches (e.g., P-type pass-transistors P 0 and P 1 ) connected between the supply voltage and the respective Bit-Lines, and that are operatively controlled by a Bit-Line-PreCHarGe signal (BLPCHG).
- P-type pass-transistors P 0 and P 1 e.g., P-type pass-transistors P 0 and P 1
- BLPCHG Bit-Line-PreCHarGe signal
- the pre-charged High bit-line e.g., BL 0
- pass-transistors e.g., T 2 and T 7
- the pre-charged High bit-line e.g., BL 0
- pass-transistors e.g., T 2 and T 7
- a non-destructive read of an entire entry comprised of a plurality of the inventive DCAM cells may be performed, while all of the Search Lines (e.g., SLC and SLT) are held Low, by pre-charging all the Bit-lines (e.g., BL 0 , BL 1 ) to a High logic voltage, and then turning ON all the pass-transistors (e.g., T 7 , T 6 ) by asserting a High logic voltage on the Read-Word Line (RWL), and then sensing a current and/or a voltage on all the Bit-lines (e.g., BL 0 and BL 1 ).
- SLC and SLT Search Lines
- RWL Read-Word Line
- a non-destructive-read of the entire CAM entry may be a refresh-read performed, while all the XNOR transistors coupled directly to the MATCH-LINE (e.g., T 4 , T 5 ) are OFF, performed for the purpose of ultimately refreshing the contents of the data storage devices (e.g, capacitors SB 0 and SB 1 ).
- the stored data word is determined (e.g., read inverted) from the DCAM entry via the read-only pass-transistors (e.g., T 7 and T 6 ) and via the bit-lines (e.g., BL 0 , BL 1 ).
- the data thus read from the data storage devices may then be asserted (re-inversion may first be necessary) and stored on the bit-lines (e.g., BL 0 and BL 1 ) themselves until the Word Line (WL) is asserted to perform a refresh-write of the stored data asserted on the bit-lines.
- a binary Buffer or a Register external to the CAM array may be used to temporarily store one stored-data word (either inverted or non-inverted) or to store a plurality of such stored-data words that have been read from a plurality of DCAM entries, until written-back into the same entr(ies).
- the non-destructive read of the entire CAM entry may also be performed as a Random Access (i.e., a RAM memory-access), whenever all the XNOR transistors coupled directly to the MATCH-LINE (e.g., T 4 , T 5 respectively) of the CAM entry being read are OFF (i.e., all Search Lines in the CAM array, e.g., SLC, SLT, are Low).
- a Random Access i.e., a RAM memory-access
- any storage capacitor in the CAM entry may be explained by reference to an example of reading data stored in storage capacitor SB 0 in FIG. 2A. If the storage capacitor (e.g., SB 0 ) is storing a logic ONE represented by a logic High voltage level stored in the capacitor, the transistor T 2 of the XNOR circuit 202 will be ON (because its gate is being held High by the capacitor SB 0 ), and a current can flow from the pre-charged High bit-line (e.g., BL 0 ) through T 2 to ground, having the effect of pulling the voltage level of bit-line BL 0 towards ground.
- the storage capacitor e.g., SB 0
- the transistor T 2 of the XNOR circuit 202 will be ON (because its gate is being held High by the capacitor SB 0 ), and a current can flow from the pre-charged High bit-line (e.g., BL 0 ) through T 2 to ground, having the effect of pulling the voltage level of bit-line BL 0 towards ground.
- This current and/or the attendant drop of voltage on bit-line BL 0 may be sensed by any appropriate sensing circuit known to persons skilled in the art coupled to the bit-line (BL 0 ), and may be registered as indicating that a logic ONE is stored in the data storage device (i.e., capacitor SB 0 ). Conversely, the lack of such a current, or the lack of such a voltage drop on BL 0 , may be sensed and registered as indicating that a logic Zero is stored in the data storage device (i.e., capacitor SB 0 ).
- the DCAM's support circuitry allows the system hardware to read the data stored in the DCAM's memory storage cells ( 210 a and 211 a ), and write to the DCAM's memory storage cells.
- the DCAM's support circuitry also provides refresh timing circuitry to periodically refresh the DCAM entry's leaking data storage capacitors. A logical ONE stored as a charge in any of the DCAM entry's capacitors will eventually discharge to a logical Zero unless the Refresh circuitry recharges the capacitor periodically.
- the DCAM's support circuitry may include: Sense amplifiers to detect the state of (e.g., to amplify the signal or charge stored) on a data storage device (e.g.
- RAM storage capacitor SB 0
- Bit-line e.g., BL 0
- Address logic to select rows and columns
- Row Address Select (RAS) and Column Address Select (CAS) logic to latch and resolve the row and column addresses and to initiate and terminate random access read and write operations
- Read and write circuitry to Write (i.e., store) information in the memory's storage cells (e.g., 210 a and 211 a ) or to Read that which is stored there; Internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as needed;
- Output logic to assert the address of a MATCH-ing CAM entry (e.g, a HIT) when found by a CAM search.
- MATCH-ing CAM entry e.g, a HIT
- a voltage sense amplifier may be used to detect the logic state of the data storage device (e.g., capacitor SB 0 ), even before the bit-line (BL 0 ) is able to drop fully from rail to rail (i.e., from a pre-charged High voltage to ground).
- a brief strobing signal e.g. a pulse SETSA, See FIG. 3
- SA voltage-sensing circuit
- the sensing strobe signal (e.g., SETSA) may be pulsed at an optimal time by a circuit that includes a Dummy-Bit-Line as a timing model and implemented on the same integrated circuit chip, or by any other method known to persons skilled in the art.
- the sensing of the state of the data storage device (e.g., capacitor SB 0 ) may be thereby performed in a brief time interval immediately before either one of the search lines of the DCAM entry (e.g., SLT and SLC) has been raised to the full High voltage level to effect a CAM search.
- SLT and SLC search lines of the DCAM entry
- FIG. 3 is a timing diagram that depicts exemplary timing relationships of signals and functions on lines coupled to the inventive ternary DCAM cell 200 a of FIG. 2A during a span of time including three consecutive CAM search cycles ( 310 , 320 , 330 ).
- Each CAM search cycle (e.g., 310 , 320 , 330 ) comprises a CAM-search period (i.e.
- a period during which the stored-data in every entry of the CAM array is compared to a comparand) e.g., 313 , 323 , 333 respectively
- a Match Line Pre-Charge period e.g., 318 , 328 , 338 respectively
- a CAM search is performed when one bit of the comparand and that comparand bit's logical complement are asserted respectively on the two search-lines (e.g., SLT and SLC) of each DCAM cell (e.g., 200 a ) of the CAM entry.
- the two search-lines e.g., SLT and SLC
- one search line e.g., SLC
- the other search line e.g., SLT
- the first CAM search cycle 310 depicted in FIG. 3 illustrates an exemplary timing of signals in the inventive ternary DCAM CELL 200 a during a refresh-read (within period 318 plus 312 ) and a subsequent refresh-write performed within the CAM search period ( 313 ).
- the first search cycle ( 313 ) happens to illustrate the case where the CAM cell 200 a is within a MISS-ing entry of a CAM array, the ability to perform a refresh-read and/or a refresh-write within a CAM search cycle (e.g. 310 ) is not dependent upon the data stored in the entry, and is not dependent upon whether the CAM entry happens to be MISS-ing entry or a MATCH-ing entry.
- a given CAM entry will be either a MISS-ing entry, or a MATCH-ing entry based upon a comparison of the data word stored in the entry compared with the (unmasked) bits of the comparand being asserted during that particular CAM search. Because a different comparand and/or a different comparand-mask (e.g., a global bit mask) may be asserted to the CAM array during each CAM search cycle, a given CAM entry may be a MISS-ing entry during one CAM search cycle, and the same CAM entry may be a MATCH-ing entry during the very next or any subsequent CAM search cycle, or vice versa.
- a comparand and/or a different comparand-mask e.g., a global bit mask
- a MISS-ing ternary CAM entry is a CAM entry that happens to be storing a ternary data word that is not logically the same as the unmasked bits of the comparand being asserted during a particular CAM search.
- a MATCH-ing CAM entry is a CAM entry that happens to be storing a ternary data word that is logically the same as the unmasked bits of the comparand being asserted during a particular CAM search.
- the inventive DCAM cell's data-comparand comparison function is performed by four pass-switches (e.g., N-channel pass-transistors T 2 , T 3 , T 4 , T 5 ) arranged in two parallel stacks (T 2 -T 4 and T 3 -T 5 ) forming the XNOR Gate 202 .
- Each of the lower pass-switches i.e., each of transistors T 2 and T 3
- a current-conducting connection between the MATCH LINE and ground will be established through one or more pass-transistor stacks (e.g., T 2 -T 4 , and/or T 3 -T 5 ) of the XNOR circuit 202 . Accordingly, in embodiments of the invention the pre-charged-High MATCH LINE voltage of a MISS-ing entry will drop to a Low (e.g., nearly ground) voltage level, thus indicating the MISS.
- a Low e.g., nearly ground
- the MATCH LINE voltage of a MATCH-ing entry will remain at the pre-charged High voltage level, and this High HIT-event voltage can be detected and therefore a MATCH or HIT may be associated with the unique address of such a MATCH-ing CAM entry.
- the second search cycle 320 depicted in FIG. 3 illustrates the timing of signals in the inventive ternary DCAM CELL 200 a during a non-destructive read (occurring within periods 328 and 322 ) and a subsequent CAM search 323 in the case where the DCAM cell 200 a happens to be within a MISS-ing entry of a CAM array.
- the second search cycle 320 illustrates that a reliable CAM search ( 323 ) can be performed in the CAM array immediately after a nondestructive read has been performed in embodiments of an inventive CAM entry (e.g., comprising CAM cells 200 a , 200 b and/or 200 c ) without having refresh-written the read-data back into the data storage devices (e.g., SB 0 and SB 1 ) in the CAM entry that was read-from.
- an inventive CAM entry e.g., comprising CAM cells 200 a , 200 b and/or 200 c
- the data storage devices e.g., SB 0 and SB 1
- the third search cycle 330 depicted in FIG. 3 illustrates the timing of signals in the inventive ternary DCAM CELL 200 a during a refresh-write (occurring within the CAM search period 333 ) subsequent to a refresh-read (e.g., occurring in a prior CAM search cycle 320 ) in the case where the DCAM cell 200 a happens to be within a MATCH-ing entry of a CAM array.
- the third search cycle 330 illustrates that the refresh-write can be delayed following a refresh-read, allow processing time to perform error (e.g., soft-error) detection analysis on the refresh-read data prior to the refresh-write, without preventing or delaying regular periodic CAM search cycles and reliable CAM searches therein.
- error e.g., soft-error
- the Match Line is pre-charged (either High or Low in accordance with Match-Line Controller design, as previously described), through a pass-switch (e.g., pass-transistor TPCHG) connected to the Match Line that is controlled by a Match Line Pre-Charge control signal MLPCHG.
- a pass-switch e.g., pass-transistor TPCHG
- MLPCHG Match Line Pre-Charge control signal
- both search lines i.e., SLT and SLC
- both DCAM cell e.g., 200 a
- both pass-transistors e.g.
- the detection of the state of the memory storage devices i.e., a non-destructive read of the data stored in the capacitors
- any inventive DCAM entry may be performed within a period of time during which all search lines of the DCAM entry are held Low, (e.g. within the Match Line pre-charge periods 318 , 328 , 338 , 348 ), through the Bit-Lines (e.g. BL 0 and BL 1 ) and through pass-switches (e.g., pass-transistors T 6 and T 7 ).
- each memory storage device e.g., capacitors SB 0 and SB 1
- every DCAM cell e.g., 200 a
- each Match Line Pre-Charge period e.g., 318 , 328 , 338 , 348
- the DCAM cell e.g., 200 a , 200 b , or 200 c
- the state of (e.g., changing the charge contained in) the memory storage devices e.g., SB 0 and SB 1 ).
- a refresh-read performed entirely within or performed substantially within such an ordinary and necessary Match Line Pre-Charge period does not add significant time to any CAM search cycle (e.g., 310 and 320 ), and may be said to be a “hidden” refresh-read.
- a non-destructive read may be performed by the following sequence of steps: First, pre-charging High the Bit-Lines (e.g. BL 0 and BL 1 ) of all DCAM cells (e.g. 200 a ) of the DCAM array within the Match Line Pre-Charge period (e.g. 318 ) or before the Match Line Pre-Charge period; Second, asserting (e.g. High) the Read-Word-Line RWL of the CAM entry-to-be-read in order to turn ON (i.e.
- the pass-transistors e.g., T 6 and T 7
- the pass-transistors T 0 and T 1 coupled to the data storage devices SB 0 and SB 1 in DCAM 200 a are OFF
- a CAM search period e.g. 313
- the state of each of the memory storage devices e.g.
- SB 0 and SB 1 as thus detected may be asserted and/or stored (e.g. stored on the Bit-Lines BL 0 and BL 1 before 312 or during 314 or after the subsequent CAM search 314 and until the next Bit-Line Pre-Charge) and then ( 316 ) written-back into the same data storage devices (e.g. SB 0 and SB 1 ).
- the Bit-Lines can be pre-charged High through a plurality of Bit-Line Pre-CHarGe pass-switches (e.g., p-channel pass-transistors P 0 and p 1 in FIG. 2A) coupled to a logic High voltage level (e.g. the power supply voltage) and controlled by a Bit-Line PreCHarGe control signal BLPCHG.
- a Bit-Line e.g. BL 0 or BL 1
- the Bit-Line can be pre-charged High for non-destructive reading during Match Line Precharging periods (e.g.
- the Non-Destructive Read Bit-Line (e.g. RBL 0 in FIGS. 2B and 2C) may be pre-charged High before or even while a write operation is being performed on the same or on another DCAM entry in the CAM array.
- separate lines e.g. RBL 0 , WBL 0
- each memory storage cell e.g.
- a refresh-reading operation and a refresh-writing operation can be performed at the same time, or during overlapping time periods during a Match Line Pre-Charge period within a CAM search cycle.
- a non-destructive read of an entire CAM entry can be “hidden” (i.e., performed without interrupting the periodic Search cycles of the CAM entry) if it is performed during a time interval within a CAM Search Cycle period (e.g., 316 ) during which all Search Lines coupled to the CAM cell are held Low, e.g., Match Line Pre-Charge period 318 ).
- a CAM Search Cycle period e.g., 316
- Match Line Pre-Charge period 318 e.g., Match Line Pre-Charge period 318 .
- all the search lines will ordinarily be held Low prior to each CAM search in order to Pre-Charge the Match-Line High.
- time interval e.g.
- a “hidden” read may be performed on the entire CAM entry.
- the sensing of the state of the data storage devices may be thereby performed in the brief time interval (e.g., 304 and/or 312 ) before either one of the search lines (SLT and SLC) shall have been raised to the High voltage level to perform a CAM search ( 323 ).
- a CAM search may be performed immediately ( 313 ) thereafter without first completing a refresh-write (e.g., 316 ).
- the non-destructively read data (acquired during period 318 ) may be refresh-written back before, while ( 316 ), or after ( 336 ) the post-read CAM search ( 313 ) is performed.
- the writing of data into the data storage devices (e.g., capacitors SB 0 and SB 1 ) of the DCAM cells 200 a , 200 b and 200 c of FIGS. 2A, 2B and 2 C, is performed (e.g., while RWL in 200 a is Low) by asserting a High voltage on the Word-Line (WL) and asserting the logical voltage representing bits of the data word on the respective write-enabling lines (e.g., BL 0 , BL 1 in DCAM 200 a ; WSL 0 and WSL 1 in DCAM 200 b ; WBL 0 and WBL 1 in DCAM 200 c ).
- the data represented by voltages thus asserted on the data-bit lines then charges (or discharges according to the data) each data storage capacitors (e.g., SB 0 and SB 1 ) of the DCAM cell (e.g., 200 a , 200 b and 200 c ).
- the write-enabling lines may then be used for other purposes, (such as for asserting the bits of the comparand during a CAM search as in 200 b in FIG. 2B; or for performing nondestructive reads as described above in DCAM cell 200 a in FIG.
- the write-enabling lines e.g., BL 0 , BL 1 in DCAM 200 a ; WSL 0 and WSL 1 in DCAM 200 b ; WBL 0 and WBL 1 in DCAM 200 c
- the write-enabling lines can be used alternatively for performing destructive-reads of the stored-memory in accordance with conventional methods of the related art, unless the array utilization of the particular DCAM array manufactured in accordance with embodiments of the present invention is too large to support such destructive charge-transfer type reads.
- a feature of the inventive DCAM cell is that the refresh-write may begin before, while ( 316 ) or after ( 336 ) the post-read CAM search ( 313 ) is performed, and therefore without delaying the post-read CAM search ( 313 ).
- embodiments of the invention provide a “hidden” refresh-write in addition to a “hidden” refresh-read.
- the inventive DCAM cell may therefore be said to provide a “hidden refresh.”
- the DCAM's memory refresh-cycle which is ordinarily performed from time to time on each entire word (e.g., entry) of the inventive CAM array, includes a refresh-read operation (e.g. performed within a Match Line Pre-Charge period 318 ) followed by a refresh-write operation (e.g. performed during a CAM search) both of which may be performed within the same CAM search cycle (e.g. 310 ).
- a CAM search operation (e.g. 313 ), or even a plurality (i.e., N, wherein N is a positive integer) of CAM search operations, may be performed between the time that such a non-destructive read operation (e.g.
- the inventive DCAM's refresh cycle does not need to be completed within one conventional DCAM's refresh cycle, and can instead be begun and completed during a period that spreads across the boundaries of a plurality N of CAM search cycles.
- This flexibility provides a variety of opportunities, including the opportunity to begin and complete the refresh cycle during periods that do not interfere with other activities of the DCAM cell.
- the flexibility of the inventive DCAM cell may support the ability to perform error (e.g., soft-error) detection analysis (e.g., using stored parity bits) and perhaps even error-correction algorithms before writing-back the data.
- error-detection during data refresh and without interfering (e.g., delaying) CAM searches may in turn enable the increase of CAM circuit density, such as by allowing for a reduction of hardware and/or device sizes (e.g. large trench capacitors) that may otherwise be provided to prevent such errors.
- a stored data error (e.g., soft-error) is detected in an inventive DCAM entry
- data may be corrected and immediately written back, or CAM searches can be suspended until the error can be corrected and correct data is written-back to the entry, or alternatively other measures can be taken to insure reliable CAM search results (such as writing to the entry such data or null-data that will not produce erroneous CAM search results).
- the inventive DCAM cell may also utilize a parasitic capacitance (e.g. from the source-substrate) rather than an explicit (e.g., trench) capacitor to decrease the cost of the storage element.
- the parasitic capacitance in transistors allows an overall simplification of the manufacturing process of the storage elements (e.g. SB 0 and SB 1 ), thus, facilitating the use of a relatively lower cost SCAM-like process.
- a lower storage capacitance may be utilized with a relatively higher refresh rate and/or a higer error-detection sampling rate.
- the optimal parasitic capacitance (or total effective capacitance) and the required refresh interval may depend on the particular fabrication process used to make the DCAM of the present invention. Optimization techniques that balance the interrelated factors of circuit density and refresh rate are well known in the art.
- the Writing of random data (i.e., data not read-from the same entry) into an entry may be performed whenever no CAM search is being performed and no read operation is being performed.
- the writing of random data into each storage capacitor (e.g., SB 0 ) is performed in the manner described above by charge-transfer from a voltage asserted on the respective write-enabling lines (e.g., BL 0 and BL 1 ) through pass-switches (e.g., pass-transistors T 0 and T 1 ) which are operatively controlled by the Word Line (WL).
- WL Word Line
- the MATCH LINE coupled to a CAM entry including the inventive CAM cell may be pre-charged to a logic High voltage level by holding all search lines (e.g., SLC, SLT) of the entry Low, thereby turning OFF (i.e., non-conducting) all transistor stacks (e.g., T 2 -T 4 and T 3 -T 5 ) of all the XNOR circuits (e.g., 202 ) thereof and then asserting a logic High voltage on the pre-charge transistor TPCHG coupled to the MATCH LINE, thereby conductively connecting the MATCH LINE to the supply voltage (e.g., logic High voltage) level.
- all search lines e.g., SLC, SLT
- all transistor stacks e.g., T 2 -T 4 and T 3 -T 5
- the XNOR circuits e.g., 202
- FIG. 2C is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing, and separate search lines are provided.
- FIG. 2B depicts a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading (e.g., RBL 0 and RBL 1 ) and for writing (e.g. WSL 0 and WSL 1 ).
- the inventive ternary DCAM cell ( 200 b ) enables a read (e.g., a nondestructive refresh-read) to be performed at each memory storage cell (e.g., 210 b , 211 b ) thereof, by operation of pass-transistors (e.g., T 2 -T 7 , T 3 -T 6 ) and through a Non-Destructive Read Bit-Lines (e.g., RBL 0 , RBL 1 ).
- a read e.g., a nondestructive refresh-read
- the refresh-read operation can be performed to read the contents of the entire entry (e.g., comprised of a plurality of DCAM cell 200 b ) via the Read enabling Bit-Lines (e.g., RWBL 0 , RWBL 1 ) whenever the Read-Word Line (RWL) coupled to the pass-transistors (e.g., T 7 and T 6 respectively) is asserted High, while all the Search Lines (e.g., WSL 0 and WSL 1 respectively) controlling the XNOR stack transistors coupled to the MATCH LINE (e.g., T 4 , and T 5 respectively) are held Low.
- RWL Read-Word Line
- one of the two individual bits stored in each DCAM cell e.g., a bit stored in CELLO of DCAM cell 200 b
- a DCAM cell 200 b can be reliably read during a CAM search, since during a CAM search operation one of the two complementary Search Lines (e.g., either WSL 0 or WSL 1 ) will be Low.
- a hidden-refresh-write may be performed through a pass-transistor (e.g., T 0 , T 1 ; controlled by a Word Line, WL) and through the separate Write Bit-Lines (e.g., WSL 0 , WSL 1 ) which also function as the DCAM's Search Lines. Because the Write Bit-Lines (e.g., WSL 0 , WSL 1 which also function as the DCAM's Search Lines, it is impracticable in this alternative embodiment to perform refresh-writes while CAM searches are being performed.
- FIG. 2C depicts a circuit diagram of an alternative embodiment of the inventive DCAM cells of FIGS. 2A and 2B wherein separate bit-lines are provided for reading (e.g., RBL 0 and RBL 1 ) and for writing (e.g. WBL 0 and WBL 1 ) and the Search Lines (SLC and SLT) are separate from the bit lines.
- the inventive ternary DCAM cell 200 c of FIG. 2C enables nondestructive reads same manner as described for DCAM cell 200 b in FIG. 2B.
- a hidden-refresh-write may be performed in the DCAM cell 200 c of FIG. 2C in the same manner as described for DCAM cell 200 b in FIG. 2B, however because the write bit lines (WBL 0 and WBL 1 ) are separate from the Search Lines (SLC and SLT) a refresh-write may be performed in the DCAM cell 200 c of FIG. 2C at the same time that a CAM search is proceeding (just as in the DCAM cell 200 a in FIG. 2A).
- the inventive DCAM cell may comprise solely NFETS (e.g., N-Channel MOSFETS) as disclosed and depicted in the embodiments shown in FIGS. 2A, 2B, and 2 C.
- NFETS e.g., N-Channel MOSFETS
- PFETs may be substituted for NFETs (e.g., T 0 , T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , or T 7 ) if control signals etc. are accordingly complemented.
- All-P-Channel embodiments of the inventive DCAM cell are also within the scope of the present invention.
- FIG. 4 depicts a representative digital system including a CAM array comprising a DCAM cell depicted in FIGS. 2A, 2B, or 2 C.
- the digital system may be for example, a computer, or a network router, comprising a digital processor operatively coupled to a CAM array; the CAM array comprising embodiments of the inventive DCAM cells disclosed herein above.
Landscapes
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
- 1. Technical Field
- The invention relates generally to semiconductor memory devices, and more specifically to a Dynamic Content Addressable Memory (DCAM) Cell.
- 2. Related Art
- Modern telecommunication networks comprise digital data networks that transmit data in packets or blocks containing address fields for dynamically routing the data packets or blocks through the network (e.g., to the destination address) at high speeds. The fastest searching of stored data may be accomplished using a Content Addressable Memory (CAM).
- As the size of networks (e.g., intranets and the Internet) increase the need for larger CAM arrays increases, and accordingly, the need to attach more CAM cells to a common bit line increases. Content Addressable Memory (CAM) arrays of the related art are generally implemented with either conventional Static RAM (SRAM) or conventional destructive-read Dynamic RAM (DRAM) hardware designs, and therefore have all the disadvantages and limitations of one such hardware design or the other.
- A typical ternary Static CAM (SCAM) of the relate art contains two six-transistor SRAM storage cells plus an XNOR functional group containing four additional transistors, thus a total of 16 transistors per SCAM cell. An SCAM is generally more vulnerable than a DCAM to corruption of stored data by Soft-Errors (e.g., stored data errors due to exposure of circuits to ambient radiation).
- A typical ternary Dynamic CAM (DCAM) cell of the related art may contain fewer transistors than an SCAM, but may have disadvantages including destructive-reads and slower performance. A typical ternary DCAM of the related art includes two data storage capacitors that must be periodically read and refreshed by charge-transfer via pass-transistors that are also used for reading and writing data by charge-transfer, in addition to an XNOR comparison circuit containing four transistors. The charge stored in the data storage capacitors of a DCAM cell is gradually dissipated by leakages within the cell. For this reason, the information stored in the leaking capacitors must be periodically “refreshed,” i.e., the charge is read and then re-written back into the storage cell. The related art provides various DCAM cell structures that are limited in that refresh-reads proceed by charge-transfer thus destroying the data stored in the data-storage capacitors, making the DCAM cell temporarily unavailable for CAM searches until the data is written back into the DCAM cell by a refresh-write. The entire refresh read-write period thereof generally occupies time during which CAM searches can not be performed. Also, limitations of the ability to sense the relatively small charge-transfer from the storage capacitor to a capacitive bit-line coupled thereto limits the maximum array population on such bit-lines, and/or requires larger storage capacitors.
- An example of such a destructive-read DCAM is disclosed in U.S. Pat. No. 5,949,696 issued to Threewitt. A variation on the ternary CAM cell disclosed by Threewitt that provides a separate search-line and a separate bit-line for each data storage capacitor of the CAM entry, is depicted in FIG. 1, and is similarly limited by an inherently-destructive read. A read operation for a refresh of the DCAM circuit of the related art depicted in FIG. 1 is performed by charge transfer of the charge stored in a data storage capacitor (e.g. SB0 or SB1) through a pass-transistor (e.g., T0R or T1R, respectively) and through a bit line (e.g. NBIT or BIT, respectively).
- In implementing CAMs, it is desirable to minimize the transistor count and/or CAM cell size, and to increase array utilization. In implementing DCAMs it is desirable to perform the refresh of stored data with minimal delay of or interference with CAM search operation.
- Accordingly, the present invention provides, among other things, an improved Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer than the 16 transistors of the typical Static Content Addressable Memory (SCAM) of the related art, but that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. The inventive DCAM achieves its search performance by simultaneously comparing all entries stored in the memory with an externally applied “comparand.” Words stored in entries in the CAM, which “match” the comparand result in maintaining the non-conductive barrier preventing charge transfer between their respective Match Lines and ground. Conversely, all words stored in entries that contain even a single bit that mismatches (i.e., does not match) the corresponding comparand bit results in a conducting path between each of their Match Lines and ground. Embodiments of the invention provide a non-destructive read operation, such that the stored-data does not have to be written back because of a refresh-read operation; and a reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes well known to persons skilled in the art may be performed on each CAM entry during the pendency of the refresh cycle (or independent of the refresh cycle) without delaying or interrupting CAM search operations. Embodiments of the invention provide CAM cell circuit topologies that can allow more CAM cells to be tied to a read-bit-line of a CAM array than may be tied to a read-bit-line of a DCAM array the related art, thus resulting in greater array utilization.
- A first aspect of the invention provides a digital system that performs the function of a network router, and a CAM array having a CAM cell including: a data storage device; a pass-gate including a stack of first and a second pass-switches, the First Pass-Switch being coupled to in series with the Second Pass-Switch at a Node; a Data Storage Device operatively controlling the Second Pass-Switch; and a Third Pass-Switch connected to the Node for detecting the logic state of the Data Storage Device.
- A second aspect of the invention provides a method for performing a plurality of CAM searches in a CAM array having a CAM entry that has a word of searchable data stored in a plurality of storage capacitors, comprising the steps of performing a non-destructive determination of the word and subsequently performing a CAM search.
- The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.
- Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and wherein:
- FIG. 1 is a block circuit diagram of a destructive-read DCAM cell of the related art.
- FIG. 2A is a circuit diagram of a DCAM cell that supports non-destructive reads and “hidden” refresh of searchable stored data in accordance with embodiments of the invention.
- FIG. 2B is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing.
- FIG. 2C is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing, and separate search lines are provided.
- FIG. 3 is a timing diagram illustrating the timing relationships among devices, data and control signals and illustrating methods of operating the inventive DCAM cell of FIG. 2A.
- FIG. 4 depicts a representative digital system including a CAM array comprising a DCAM cell depicted in FIGS. 2A, 2B, or2C.
- FIG. 2A depicts a circuit diagram of a ternary Dynamic Content Addressable Memory (DCAM) cell200 a in accordance with an embodiment of the present invention. The inventive ternary DCAM cell 200 a includes two capacitors (SB0 and SB1) that function as data storage devices. Each of these capacitors is independently charged High to store a logical One (“1”) or discharged Low to store a logical Zero (“0”).
- Ternary DCAM200 a further comprises two memory storage cells (CELL0=210 a, CELL1=211 a) each of which is merged with one of the two transistor stacks (T2-T4 and T3-T5 respectively) of the
XNOR comparison circuit 202 that is connected between the MATCH LINE and ground. By storing a “1,” or a “1” (preferably a “0”) in both memory storage cells (e.g., 210 a and 211 a), the ternary DCAM cell 200 a stores a “mask” state which allows a local mask logic value to be stored within a given word entry. The ability to store a “mask” logic state in each DCAM cell (e.g., 200 a) in a DCAM entry allows bit-level masking of data stored in an CAM array of DCAM cells. The bit-level masking facilitates and/or enables the storing and comparing of an address range using the present invention and is beneficial in, inter alia, network address filtering applications. - Embodiments of the inventive DCAM cell comprise an Exclusive Negative OR (XNOR) logic function implemented by an XNOR Gate202 (as shown in FIGS. 2A, 2B, 2C) including four (4) transistors arranged in two parallel stacks of two (2) stacked transistors. Each transistor stack includes a first pass-switch (e.g. NFET transistor T2 or T3) and a second pass-switch (e.g. NFET transistor T4 or T5), the first pass-switch being coupled to in series with the second pass-switch at a node (e.g., N0 or N1 respectively). Because each transistor stack (e.g., T0-T2 and T1-T3) of the XNOR
Gate 202 functions physically independently of the other, is not necessary for proper logical operation of the DCAM that the two transistor stacks (e.g., T0-T2 and T1-T3) of one ternary DCAM cell 200 a be located physically adjacent to one another on the integrated circuit (IC) chip. The ternary DCAM cell 200 a may therefore be “split” in to “halves” (with other halved-DCAM cells disposed in between each such half), provided that all such half-DCAM cells are connected to the same Match Line of the CAM entry. For example all of the “True halves” of the DCAM cell of an entry can be segregated on one end of the entry's Match Line, while all of the “Complement halves” of the DCAM cell of an entry can be segregated on the opposite end of the entry's Match Line. Search lines and bit lines would be similarly segregated to follow the respective halves of the DCAM cell. - Because, the XNOR transistors coupled conductively to the Match Line (i.e, T4, T5 in XNOR 202) are ideally OFF while the Match Line is pre-charged High, prior to each CAM search, the non-destructive read through pass-transistors (e.g., T2-T7, T3-T6) may be performed prior to a CAM search and while the XNOR transistors coupled conductively to the Match Line (T4, T5) are OFF. Because the non-destructive read inherently leaves the contents of the data storage devices (e.g., capacitors SB0, SB1) undisturbed, a CAM search operation can be afterwards performed without the necessity of first writing-back the data read-from the storage capacitor. Therefore, in embodiments of the invention, a non-destructive refresh-read operation may be “hidden” from the CAM search cycle in the sense that a refresh-read performed does not delay or prevent a subsequent CAM-search from being performed. A refresh-write can be performed following such a non-destructive refresh-read either, before, during or after the performance of a CAM search.
- Persons skilled in the art will recognize that the connection of the DCAM cell's XNOR stacks to ground can be a direct connection as shown in FIG. 2A, or this connection can be selectively interruptible by the pass-switch (e.g. pass-transistor) of a “global” bit-mask (not shown). A “global” bit mask coupled to the XNOR circuit functions such that when a global bit-mask signal is asserted the corresponding bit position in every word stored in the CAM array is eliminated from the compare function (i.e., it becomes a global “don't care” (forced match) logic value for every word in the CAM array). Such global masking is useful in comparing or searching for ranges of data values stored in the CAM entries.
- The plurality of parallel transistor stacks (e.g., T2-T4 and T3-T5) of all the XNOR comparison circuits of all the CAM cells in a CAM entry form a Match-Line Pass-Gate. The Match Line Pass-Gate operates such that a pre-charged High Match Line will remain High in the case of a MATCH-ing entry, but will be discharged to or near ground voltage level (indicating a Miss) if any one or more ternary bits stored in the CAM entry mis-matches the corresponding bit of the comparand. Alternatively, the Match Line Pass-Gate and the DCAM cell of the present invention will also support a pre-charged-Low Match Line in a match-detection system, such as is disclosed in U.S. patent application of Towler et. als., Ser. No. ______ filed, ______, 2000, the relevant portions of which are incorporated herein by reference, wherein the subject matter and the claimed invention were at the time the invention was made, owned by, or subject to, an obligation for assignment to International Business Machines Corp, which is the assignee of the present invention.
- The writing and reading of data into or from the memory storage cells (210 a and 211 a) can be performed by charge-transfer, as in the related art DCAMs, through the bit lines (BL0 and BL1 respectively) and through pass-transistors (T0 and T1 respectively) held ON (i.e., conducting) when the Word-Line WL is held High. The method of writing or reading data by charge-transfer in the present invention is the same or similar as the method of writing and reading by charge-transfer used in DCAMs of the related art. However, reading by charge-transfer is unnecessary in embodiments of the present invention because the present invention enables the reading of stored data without destructive charge-transfer of the charge stored in the data storage capacitors (e.g., SB0 and SB1).
- A non-destructive read may be performed at each memory storage cell (e.g.,210 a, 211 a) of DCAM cell 200 a, while the respective search line (e.g., SLC or SLT) is held Low, by pre-charging the respective Bit-Line (e.g., BL0, BL1 respectively) to a High logic voltage, and then turning the pass-transistor (e.g., T7, T6 respectively) ON (i.e., conducting) by asserting a High logic voltage on the gate thereof (e.g., by asserting a High logic voltage on the Read-Word Line (RWL)), and then sensing a current and/or a voltage on the respective Bit-Line (e.g., BL0, BL1) that is representative of the state of the respective data storage device (e.g., SB0 and SB1 respectively). The Bit-Lines may be pre-charged High through a plurality of pass-switches (e.g., P-type pass-transistors P0 and P1) connected between the supply voltage and the respective Bit-Lines, and that are operatively controlled by a Bit-Line-PreCHarGe signal (BLPCHG). If the capacitor SB0 stores a logic High voltage, the pre-charged High bit-line (e.g., BL0) operatively coupled to pass-transistors (e.g., T2 and T7) will drop to or towards a Low voltage level during the non-destructive read operation, due to charge-transfer from the pre-charged bit-line (e.g., BL0) to ground through the ON (i.e., current conducting) pass-transistors (T2 and T7). If the capacitor SB0 stores a logic Low voltage, the pre-charged High bit-line (e.g., BL0) operatively coupled to pass-transistors (e.g., T2 and T7) will remain at the pre-charged High voltage level during the non-destructive read operation, due to lack of charge-transfer from the pre-charged bit-line (e.g., BL0) to ground through said OFF (i.e., non-conducting) pass-transistors (T2 and T7).
- A non-destructive read of an entire entry comprised of a plurality of the inventive DCAM cells (e.g.200 a) may be performed, while all of the Search Lines (e.g., SLC and SLT) are held Low, by pre-charging all the Bit-lines (e.g., BL0, BL1) to a High logic voltage, and then turning ON all the pass-transistors (e.g., T7, T6) by asserting a High logic voltage on the Read-Word Line (RWL), and then sensing a current and/or a voltage on all the Bit-lines (e.g., BL0 and BL1). A non-destructive-read of the entire CAM entry may be a refresh-read performed, while all the XNOR transistors coupled directly to the MATCH-LINE (e.g., T4, T5) are OFF, performed for the purpose of ultimately refreshing the contents of the data storage devices (e.g, capacitors SB0 and SB1). In this case, the stored data word is determined (e.g., read inverted) from the DCAM entry via the read-only pass-transistors (e.g., T7 and T6) and via the bit-lines (e.g., BL0, BL1). The data thus read from the data storage devices may then be asserted (re-inversion may first be necessary) and stored on the bit-lines (e.g., BL0 and BL1) themselves until the Word Line (WL) is asserted to perform a refresh-write of the stored data asserted on the bit-lines. Alternatively, a binary Buffer or a Register external to the CAM array may be used to temporarily store one stored-data word (either inverted or non-inverted) or to store a plurality of such stored-data words that have been read from a plurality of DCAM entries, until written-back into the same entr(ies).
- The non-destructive read of the entire CAM entry may also be performed as a Random Access (i.e., a RAM memory-access), whenever all the XNOR transistors coupled directly to the MATCH-LINE (e.g., T4, T5 respectively) of the CAM entry being read are OFF (i.e., all Search Lines in the CAM array, e.g., SLC, SLT, are Low).
- Further details of the non-destructive-read operation of any storage capacitor in the CAM entry may be explained by reference to an example of reading data stored in storage capacitor SB0 in FIG. 2A. If the storage capacitor (e.g., SB0) is storing a logic ONE represented by a logic High voltage level stored in the capacitor, the transistor T2 of the
XNOR circuit 202 will be ON (because its gate is being held High by the capacitor SB0), and a current can flow from the pre-charged High bit-line (e.g., BL0) through T2 to ground, having the effect of pulling the voltage level of bit-line BL0 towards ground. This current and/or the attendant drop of voltage on bit-line BL0 may be sensed by any appropriate sensing circuit known to persons skilled in the art coupled to the bit-line (BL0), and may be registered as indicating that a logic ONE is stored in the data storage device (i.e., capacitor SB0). Conversely, the lack of such a current, or the lack of such a voltage drop on BL0, may be sensed and registered as indicating that a logic Zero is stored in the data storage device (i.e., capacitor SB0). - The DCAM's support circuitry (not shown) allows the system hardware to read the data stored in the DCAM's memory storage cells (210 a and 211 a), and write to the DCAM's memory storage cells. The DCAM's support circuitry also provides refresh timing circuitry to periodically refresh the DCAM entry's leaking data storage capacitors. A logical ONE stored as a charge in any of the DCAM entry's capacitors will eventually discharge to a logical Zero unless the Refresh circuitry recharges the capacitor periodically. The DCAM's support circuitry may include: Sense amplifiers to detect the state of (e.g., to amplify the signal or charge stored) on a data storage device (e.g. storage capacitor SB0) through a bit-line (e.g., BL0); Address logic to select rows and columns; Row Address Select (RAS) and Column Address Select (CAS) logic to latch and resolve the row and column addresses and to initiate and terminate random access read and write operations; Read and write circuitry to Write (i.e., store) information in the memory's storage cells (e.g., 210 a and 211 a) or to Read that which is stored there; Internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as needed; Output logic to assert the address of a MATCH-ing CAM entry (e.g, a HIT) when found by a CAM search.
- A voltage sense amplifier (SA) may be used to detect the logic state of the data storage device (e.g., capacitor SB0), even before the bit-line (BL0) is able to drop fully from rail to rail (i.e., from a pre-charged High voltage to ground). If a voltage-sensing circuit is used, a brief strobing signal (e.g. a pulse SETSA, See FIG. 3) may be used to enable the voltage-sensing circuit (e.g., SA) for a relatively brief time interval during which any sense-able drop of the voltage on Bit-line shall be expected to have occurred or not-occurred depending upon the contents of the storage capacitor (e.g., SB0). The sensing strobe signal (e.g., SETSA) may be pulsed at an optimal time by a circuit that includes a Dummy-Bit-Line as a timing model and implemented on the same integrated circuit chip, or by any other method known to persons skilled in the art. The sensing of the state of the data storage device (e.g., capacitor SB0) may be thereby performed in a brief time interval immediately before either one of the search lines of the DCAM entry (e.g., SLT and SLC) has been raised to the full High voltage level to effect a CAM search. Greater detail of exemplary timing and relationships of the inventive DCAM cell's circuits, signals and functions may be explained by reference to FIG. 3 in conjunction with the circuit diagram of DCAM cell 200 a of FIG. 2A.
- FIG. 3 is a timing diagram that depicts exemplary timing relationships of signals and functions on lines coupled to the inventive ternary DCAM cell200 a of FIG. 2A during a span of time including three consecutive CAM search cycles (310, 320, 330). Each CAM search cycle (e.g., 310, 320, 330) comprises a CAM-search period (i.e. a period during which the stored-data in every entry of the CAM array is compared to a comparand) (e.g., 313, 323, 333 respectively), and a Match Line Pre-Charge period (e.g., 318, 328, 338 respectively) to prepare the Match Line coupled to all the DCAM cells (e.g., 200 a) of the DCAM entry for the CAM search (e.g., 313, 323, 333 respectively).
- A CAM search is performed when one bit of the comparand and that comparand bit's logical complement are asserted respectively on the two search-lines (e.g., SLT and SLC) of each DCAM cell (e.g.,200 a) of the CAM entry. Thus, during each CAM search period (e.g., 313) one search line (e.g., SLC) of a given DCAM cell 200 a will be High, and the other search line (e.g., SLT) will be Low.
- The first
CAM search cycle 310 depicted in FIG. 3 illustrates an exemplary timing of signals in the inventive ternary DCAM CELL 200 a during a refresh-read (withinperiod 318 plus 312) and a subsequent refresh-write performed within the CAM search period (313). Although the first search cycle (313) happens to illustrate the case where the CAM cell 200 a is within a MISS-ing entry of a CAM array, the ability to perform a refresh-read and/or a refresh-write within a CAM search cycle (e.g. 310) is not dependent upon the data stored in the entry, and is not dependent upon whether the CAM entry happens to be MISS-ing entry or a MATCH-ing entry. - During each CAM search (e.g.,310, 320, 330), a given CAM entry will be either a MISS-ing entry, or a MATCH-ing entry based upon a comparison of the data word stored in the entry compared with the (unmasked) bits of the comparand being asserted during that particular CAM search. Because a different comparand and/or a different comparand-mask (e.g., a global bit mask) may be asserted to the CAM array during each CAM search cycle, a given CAM entry may be a MISS-ing entry during one CAM search cycle, and the same CAM entry may be a MATCH-ing entry during the very next or any subsequent CAM search cycle, or vice versa. A MISS-ing ternary CAM entry is a CAM entry that happens to be storing a ternary data word that is not logically the same as the unmasked bits of the comparand being asserted during a particular CAM search. Conversely, a MATCH-ing CAM entry is a CAM entry that happens to be storing a ternary data word that is logically the same as the unmasked bits of the comparand being asserted during a particular CAM search.
- The inventive DCAM cell's data-comparand comparison function is performed by four pass-switches (e.g., N-channel pass-transistors T2, T3, T4, T5) arranged in two parallel stacks (T2-T4 and T3-T5) forming the
XNOR Gate 202. Each of the lower pass-switches (i.e., each of transistors T2 and T3) perform the dual function of supporting the nondestructive-read of the data value stored in the associated data storage device (i.e., capacitor SB0 and SB1 respectively) plus that of enabling the XNOR comparison function within the inventive ternary DCAM cell (e.g. 200 a, 200 b, 200 c). - In the case of a MISS-ing CAM entry, the occurrence of which is indicated by a drop to Low of the Match Line voltage, a current-conducting connection between the MATCH LINE and ground will be established through one or more pass-transistor stacks (e.g., T2-T4, and/or T3-T5) of the
XNOR circuit 202. Accordingly, in embodiments of the invention the pre-charged-High MATCH LINE voltage of a MISS-ing entry will drop to a Low (e.g., nearly ground) voltage level, thus indicating the MISS. - In the case of a MATCH-ing entry, the occurrence of which is depicted in the third CAM search cycle (330) in FIG. 3, no current-conducting connection between the MATCH LINE and ground will be established through any of the transistor stacks (e.g., neither T2-T4 nor T3-T5) of the XNOR circuits (e.g., 202) in the DCAM cells (e.g. 200 a) of the CAM entry. Accordingly, in embodiments of the invention the MATCH LINE voltage of a MATCH-ing entry will remain at the pre-charged High voltage level, and this High HIT-event voltage can be detected and therefore a MATCH or HIT may be associated with the unique address of such a MATCH-ing CAM entry.
- The
second search cycle 320 depicted in FIG. 3 illustrates the timing of signals in the inventive ternary DCAM CELL 200 a during a non-destructive read (occurring withinperiods 328 and 322) and asubsequent CAM search 323 in the case where the DCAM cell 200 a happens to be within a MISS-ing entry of a CAM array. Thesecond search cycle 320 illustrates that a reliable CAM search (323) can be performed in the CAM array immediately after a nondestructive read has been performed in embodiments of an inventive CAM entry (e.g., comprising CAM cells 200 a, 200 b and/or 200 c) without having refresh-written the read-data back into the data storage devices (e.g., SB0 and SB1) in the CAM entry that was read-from. - The third search cycle330 depicted in FIG. 3 illustrates the timing of signals in the inventive ternary DCAM CELL 200 a during a refresh-write (occurring within the CAM search period 333) subsequent to a refresh-read (e.g., occurring in a prior CAM search cycle 320) in the case where the DCAM cell 200 a happens to be within a MATCH-ing entry of a CAM array. The third search cycle 330 illustrates that the refresh-write can be delayed following a refresh-read, allow processing time to perform error (e.g., soft-error) detection analysis on the refresh-read data prior to the refresh-write, without preventing or delaying regular periodic CAM search cycles and reliable CAM searches therein.
- In the exemplary embodiments of the inventive DCAM cell (e.g.,200 a, 200 b, 200 c), prior to each CAM search (e.g., 313, 323, 333) the Match Line is pre-charged (either High or Low in accordance with Match-Line Controller design, as previously described), through a pass-switch (e.g., pass-transistor TPCHG) connected to the Match Line that is controlled by a Match Line Pre-Charge control signal MLPCHG. During each Match Line Pre-Charge period (e.g., 318, 328, 338, 348). In an exemplary embodiment of the invention (e.g., 200 a) wherein the Match Line is pre-charged High, both search lines (i.e., SLT and SLC) of each DCAM cell (e.g., 200 a) will be held Low (e.g. during a regular Match
Line Precharge period XNOR function 202, so that no conducting path exists between the Match Line and ground, and so that the Match Line will hold the High charge until a CAM search on that DCAM entry is a “MISS” (i.e., the stored data does not match the comparand). - The detection of the state of the memory storage devices (i.e., a non-destructive read of the data stored in the capacitors) in any inventive DCAM entry may be performed within a period of time during which all search lines of the DCAM entry are held Low, (e.g. within the Match Line
pre-charge periods - A non-destructive read may be performed by the following sequence of steps: First, pre-charging High the Bit-Lines (e.g. BL0 and BL1) of all DCAM cells (e.g. 200 a) of the DCAM array within the Match Line Pre-Charge period (e.g. 318) or before the Match Line Pre-Charge period; Second, asserting (e.g. High) the Read-Word-Line RWL of the CAM entry-to-be-read in order to turn ON (i.e. conducting) the pass-transistors (e.g., T6 and T7) thereof (while the pass-transistors T0 and T1 coupled to the data storage devices SB0 and SB1 in DCAM 200 a are OFF) outside of (e.g. before) a CAM search period (e.g., 313); Third, detecting the state of the memory storage devices (e.g., SB0 and SB1) through the respective Bit-Lines (e.g. BL0 and BL1) while the pass-transistors (e.g., T6 and T7) are ON, as described above. The state of each of the memory storage devices (e.g. SB0 and SB1) as thus detected may be asserted and/or stored (e.g. stored on the Bit-Lines BL0 and BL1 before 312 or during 314 or after the
subsequent CAM search 314 and until the next Bit-Line Pre-Charge) and then (316) written-back into the same data storage devices (e.g. SB0 and SB1). - The Bit-Lines can be pre-charged High through a plurality of Bit-Line Pre-CHarGe pass-switches (e.g., p-channel pass-transistors P0 and p1 in FIG. 2A) coupled to a logic High voltage level (e.g. the power supply voltage) and controlled by a Bit-Line PreCHarGe control signal BLPCHG. The control signal BLPCHG will activate (i.e. turn ON=conducting) the pass-switches (e.g. P0 and P1) to pre-charge the Bit-Lines (e.g. BL0 and BL1 respectively) during or before the Match Line Pre-Charge period (e.g. 318). If a Bit-Line (e.g. BL0 or BL1) is designed to be used both for reading and for writing data (as in DCAM cell 200 a in FIG. 2A, but not in DCAM cell 200 b nor 200 c of FIGS. 2B and 2C) then the use of the Bit-Line (e.g. BL0 or BL1) must be time-multiplexed such that reading and writing operations do not occur at the same times and do not interfere with each other. Therefore, in the DCAM 200 a of FIG. 2A, the Bit-Lines can be pre-charged High for non-destructive reading during Match Line Precharging periods (e.g. 318 and 328, 338, and 348) outside of writing-periods (e.g. 316 and 336 during which writing is being performed. However, where separate lines are provided to each memory storage cell (e.g. 210 b and 210 c in DCAM cells 200 b and 200 c as shown in FIGS. 2B and 2C respectively) for writing and for reading, the Non-Destructive Read Bit-Line (e.g. RBL0 in FIGS. 2B and 2C) may be pre-charged High before or even while a write operation is being performed on the same or on another DCAM entry in the CAM array. Where separate lines (e.g. RBL0, WBL0) are provided to each memory storage cell (e.g. 210 c in DCAM cell 200 c as shown in FIG. 2C) for writing (e.g. WBL0) and for reading (RBL0), and where neither of such lines is also a Search-Line (e.g. SLC) coupled to the
XNOR Gate 202, a refresh-reading operation and a refresh-writing operation can be performed at the same time, or during overlapping time periods during a Match Line Pre-Charge period within a CAM search cycle. - Accordingly, a non-destructive read of an entire CAM entry can be “hidden” (i.e., performed without interrupting the periodic Search cycles of the CAM entry) if it is performed during a time interval within a CAM Search Cycle period (e.g.,316) during which all Search Lines coupled to the CAM cell are held Low, e.g., Match Line Pre-Charge period 318). In embodiments of the invention wherein the MATCH LINE is ordinarily Pre-charged High prior to each CAM search, all the search lines will ordinarily be held Low prior to each CAM search in order to Pre-Charge the Match-Line High. During that time interval (e.g. 318) before each next CAM search (e.g., 323), a “hidden” read may performed on the entire CAM entry. The sensing of the state of the data storage devices may be thereby performed in the brief time interval (e.g., 304 and/or 312) before either one of the search lines (SLT and SLC) shall have been raised to the High voltage level to perform a CAM search (323).
- Because the read thereby effected has been nondestructive of the data stored in the memory storage devices (e.g., capacitors SB0 and SB1) of the CAM cells (e.g., 200 a) of the CAM entry, a CAM search may be performed immediately (313) thereafter without first completing a refresh-write (e.g., 316). The non-destructively read data (acquired during period 318) may be refresh-written back before, while (316), or after (336) the post-read CAM search (313) is performed.
- The writing of data into the data storage devices (e.g., capacitors SB0 and SB1) of the DCAM cells 200 a, 200 b and 200 c of FIGS. 2A, 2B and 2C, is performed (e.g., while RWL in 200 a is Low) by asserting a High voltage on the Word-Line (WL) and asserting the logical voltage representing bits of the data word on the respective write-enabling lines (e.g., BL0, BL1 in DCAM 200 a; WSL0 and WSL1 in DCAM 200 b; WBL0 and WBL1 in DCAM 200 c). The data represented by voltages thus asserted on the data-bit lines then charges (or discharges according to the data) each data storage capacitors (e.g., SB0 and SB1) of the DCAM cell (e.g., 200 a, 200 b and 200 c). When the Word-Line WL are brought Low, the write-enabling lines may then be used for other purposes, (such as for asserting the bits of the comparand during a CAM search as in 200 b in FIG. 2B; or for performing nondestructive reads as described above in DCAM cell 200 a in FIG. 2A; or for performing destructive-reads as in the related art DCAM cells) The write-enabling lines (e.g., BL0, BL1 in DCAM 200 a; WSL0 and WSL1 in DCAM 200 b; WBL0 and WBL1 in DCAM 200 c) can be used alternatively for performing destructive-reads of the stored-memory in accordance with conventional methods of the related art, unless the array utilization of the particular DCAM array manufactured in accordance with embodiments of the present invention is too large to support such destructive charge-transfer type reads.
- A feature of the inventive DCAM cell is that the refresh-write may begin before, while (316) or after (336) the post-read CAM search (313) is performed, and therefore without delaying the post-read CAM search (313). Thus, embodiments of the invention provide a “hidden” refresh-write in addition to a “hidden” refresh-read. The inventive DCAM cell may therefore be said to provide a “hidden refresh.”
- The DCAM's memory refresh-cycle, which is ordinarily performed from time to time on each entire word (e.g., entry) of the inventive CAM array, includes a refresh-read operation (e.g. performed within a Match Line Pre-Charge period318) followed by a refresh-write operation (e.g. performed during a CAM search) both of which may be performed within the same CAM search cycle (e.g. 310). Because the read-operation performed through pass-transistors (e.g., T2-T7 or T3-T6) is non-destructive (i.e., does not alter the charge stored by the storage capacitors SB0 and SB1 respectively), the read-operation does not itself necessitate an immediate write-back of the data read-from the storage capacitor. Accordingly, a CAM search operation (e.g. 313), or even a plurality (i.e., N, wherein N is a positive integer) of CAM search operations, may be performed between the time that such a non-destructive read operation (e.g. 318 or 328) has been performed on a CAM entry and the later time that a refresh-write operation (e.g., 336) is performed on the same CAM entry. Stated another way, the inventive DCAM's refresh cycle does not need to be completed within one conventional DCAM's refresh cycle, and can instead be begun and completed during a period that spreads across the boundaries of a plurality N of CAM search cycles.
- This flexibility provides a variety of opportunities, including the opportunity to begin and complete the refresh cycle during periods that do not interfere with other activities of the DCAM cell. The flexibility of the inventive DCAM cell may support the ability to perform error (e.g., soft-error) detection analysis (e.g., using stored parity bits) and perhaps even error-correction algorithms before writing-back the data. The ability to perform error-detection during data refresh and without interfering (e.g., delaying) CAM searches may in turn enable the increase of CAM circuit density, such as by allowing for a reduction of hardware and/or device sizes (e.g. large trench capacitors) that may otherwise be provided to prevent such errors. If a stored data error (e.g., soft-error) is detected in an inventive DCAM entry, data may be corrected and immediately written back, or CAM searches can be suspended until the error can be corrected and correct data is written-back to the entry, or alternatively other measures can be taken to insure reliable CAM search results (such as writing to the entry such data or null-data that will not produce erroneous CAM search results). Because the risk of soft-error may be reduced by error-detection, the inventive DCAM cell may also utilize a parasitic capacitance (e.g. from the source-substrate) rather than an explicit (e.g., trench) capacitor to decrease the cost of the storage element. Use of the parasitic capacitance in transistors (e.g., T0-T2 and T1-T3) allows an overall simplification of the manufacturing process of the storage elements (e.g. SB0 and SB1), thus, facilitating the use of a relatively lower cost SCAM-like process. A lower storage capacitance may be utilized with a relatively higher refresh rate and/or a higer error-detection sampling rate. The optimal parasitic capacitance (or total effective capacitance) and the required refresh interval may depend on the particular fabrication process used to make the DCAM of the present invention. Optimization techniques that balance the interrelated factors of circuit density and refresh rate are well known in the art.
- The Writing of random data (i.e., data not read-from the same entry) into an entry may be performed whenever no CAM search is being performed and no read operation is being performed. The writing of random data into each storage capacitor (e.g., SB0), is performed in the manner described above by charge-transfer from a voltage asserted on the respective write-enabling lines (e.g., BL0 and BL1) through pass-switches (e.g., pass-transistors T0 and T1) which are operatively controlled by the Word Line (WL).
- The MATCH LINE coupled to a CAM entry including the inventive CAM cell (e.g.,200 a, 200 b, 200 c) may be pre-charged to a logic High voltage level by holding all search lines (e.g., SLC, SLT) of the entry Low, thereby turning OFF (i.e., non-conducting) all transistor stacks (e.g., T2-T4 and T3-T5) of all the XNOR circuits (e.g., 202) thereof and then asserting a logic High voltage on the pre-charge transistor TPCHG coupled to the MATCH LINE, thereby conductively connecting the MATCH LINE to the supply voltage (e.g., logic High voltage) level.
- FIG. 2C is a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading and writing, and separate search lines are provided.
- FIG. 2B depicts a circuit diagram of an alternative embodiment of the inventive DCAM cell of FIG. 2A wherein separate bit-lines are provided for reading (e.g., RBL0 and RBL1) and for writing (e.g. WSL0 and WSL1). The inventive ternary DCAM cell (200 b) enables a read (e.g., a nondestructive refresh-read) to be performed at each memory storage cell (e.g., 210 b, 211 b) thereof, by operation of pass-transistors (e.g., T2-T7, T3-T6) and through a Non-Destructive Read Bit-Lines (e.g., RBL0, RBL1). The refresh-read operation can be performed to read the contents of the entire entry (e.g., comprised of a plurality of DCAM cell 200 b) via the Read enabling Bit-Lines (e.g., RWBL0, RWBL1) whenever the Read-Word Line (RWL) coupled to the pass-transistors (e.g., T7 and T6 respectively) is asserted High, while all the Search Lines (e.g., WSL0 and WSL1 respectively) controlling the XNOR stack transistors coupled to the MATCH LINE (e.g., T4, and T5 respectively) are held Low. Alternatively, one of the two individual bits stored in each DCAM cell (e.g., a bit stored in CELLO of DCAM cell 200 b) in a DCAM cell 200 b can be reliably read during a CAM search, since during a CAM search operation one of the two complementary Search Lines (e.g., either WSL0 or WSL1) will be Low.
- A hidden-refresh-write may be performed through a pass-transistor (e.g., T0, T1; controlled by a Word Line, WL) and through the separate Write Bit-Lines (e.g., WSL0, WSL1) which also function as the DCAM's Search Lines. Because the Write Bit-Lines (e.g., WSL0, WSL1 which also function as the DCAM's Search Lines, it is impracticable in this alternative embodiment to perform refresh-writes while CAM searches are being performed.
- FIG. 2C depicts a circuit diagram of an alternative embodiment of the inventive DCAM cells of FIGS. 2A and 2B wherein separate bit-lines are provided for reading (e.g., RBL0 and RBL1) and for writing (e.g. WBL0 and WBL1) and the Search Lines (SLC and SLT) are separate from the bit lines. The inventive ternary DCAM cell 200 c of FIG. 2C enables nondestructive reads same manner as described for DCAM cell 200 b in FIG. 2B.
- A hidden-refresh-write may be performed in the DCAM cell200 c of FIG. 2C in the same manner as described for DCAM cell 200 b in FIG. 2B, however because the write bit lines (WBL0 and WBL1) are separate from the Search Lines (SLC and SLT) a refresh-write may be performed in the DCAM cell 200 c of FIG. 2C at the same time that a CAM search is proceeding (just as in the DCAM cell 200 a in FIG. 2A).
- The inventive DCAM cell (e.g,200 a, 200 b, and 200 c) may comprise solely NFETS (e.g., N-Channel MOSFETS) as disclosed and depicted in the embodiments shown in FIGS. 2A, 2B, and 2C. PFETs may be substituted for NFETs (e.g., T0, T1, T2, T3, T4, T5, T6, or T7) if control signals etc. are accordingly complemented. Alternately, All-P-Channel embodiments of the inventive DCAM cell are also within the scope of the present invention.
- FIG. 4 depicts a representative digital system including a CAM array comprising a DCAM cell depicted in FIGS. 2A, 2B, or2C. The digital system, may be for example, a computer, or a network router, comprising a digital processor operatively coupled to a CAM array; the CAM array comprising embodiments of the inventive DCAM cells disclosed herein above.
- While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention. Embodiments of the invention may be implemented as an integrated electronic circuit on a semiconductor substrate, or as an electronic circuit implemented with discrete devices such as switches (e.g., transistors, or electromechanical relays, or analogous optical components), or as a combination of these circuits. The following claims are therefore intended to include all such alternative embodiments of the invention. Accordingly, term “pass-switch” is used in the following claims to describe the structure and function provided by the pass-transistors depicted in the accompanying drawings that depict exemplary embodiments of the invention.
Claims (20)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/730,673 US6430073B1 (en) | 2000-12-06 | 2000-12-06 | Dram CAM cell with hidden refresh |
KR10-2001-0073680A KR100472113B1 (en) | 2000-12-06 | 2001-11-26 | Dram cam cell with hidden refresh |
SG200107479A SG96264A1 (en) | 2000-12-06 | 2001-11-30 | Dram cam cell with hidden refresh |
JP2001368965A JP3737745B2 (en) | 2000-12-06 | 2001-12-03 | DRAMCAM cell with hidden refresh |
TW090129804A TW571312B (en) | 2000-12-06 | 2001-12-03 | DRAM CAM cell with hidden refresh |
CNB011429828A CN1186782C (en) | 2000-12-06 | 2001-12-06 | Memory unit containing implicit updated DRAM and with addressable contents |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/730,673 US6430073B1 (en) | 2000-12-06 | 2000-12-06 | Dram CAM cell with hidden refresh |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020067632A1 true US20020067632A1 (en) | 2002-06-06 |
US6430073B1 US6430073B1 (en) | 2002-08-06 |
Family
ID=24936336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/730,673 Expired - Lifetime US6430073B1 (en) | 2000-12-06 | 2000-12-06 | Dram CAM cell with hidden refresh |
Country Status (6)
Country | Link |
---|---|
US (1) | US6430073B1 (en) |
JP (1) | JP3737745B2 (en) |
KR (1) | KR100472113B1 (en) |
CN (1) | CN1186782C (en) |
SG (1) | SG96264A1 (en) |
TW (1) | TW571312B (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030058673A1 (en) * | 2001-09-24 | 2003-03-27 | Alon Regev | Reducing signal swing in a match detection circuit |
US20030169612A1 (en) * | 2002-03-08 | 2003-09-11 | Hu Shane Ching-Feng | Static content addressable memory cell |
US20040228165A1 (en) * | 2003-05-16 | 2004-11-18 | Kim Gi Hong | SRAM-compatible memory device performing refresh operation having separate fetching and writing operation periods and method of driving the same |
US20040243758A1 (en) * | 2003-05-30 | 2004-12-02 | Renesas Technology Corp. | Data storage circuit |
US20050018463A1 (en) * | 2003-07-25 | 2005-01-27 | Vipul Patel | Noise reduction in a CAM memory cell |
US20050024976A1 (en) * | 2003-04-25 | 2005-02-03 | Samsung Electronics Co., Ltd. | Content addressable memory device |
US6870749B1 (en) | 2003-07-15 | 2005-03-22 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors |
US6879504B1 (en) | 2001-02-08 | 2005-04-12 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same |
US20050080988A1 (en) * | 2003-10-08 | 2005-04-14 | Tom Teng | Parity-scanning and refresh in dynamic memory devices |
US20050190201A1 (en) * | 2002-07-23 | 2005-09-01 | Baer David A. | System and method for providing graphics using graphical engine |
US6987684B1 (en) | 2003-07-15 | 2006-01-17 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein |
WO2006007250A2 (en) | 2004-06-29 | 2006-01-19 | Cisco Technology, Inc. | Error protection for lookup operations in content-addressable memory entries |
US7193876B1 (en) | 2003-07-15 | 2007-03-20 | Kee Park | Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors |
US20070115229A1 (en) * | 2005-11-21 | 2007-05-24 | Nec Corporation | Display device and apparatus using same |
US20070297210A1 (en) * | 2006-06-23 | 2007-12-27 | Yoshihiro Ueda | Semiconductor memory device and writing method thereof |
US20110001491A1 (en) * | 2009-07-02 | 2011-01-06 | Novatek Microelectronics Corp. | Capacitance measurement circuit and method |
WO2015149037A1 (en) * | 2014-03-28 | 2015-10-01 | Synopsys, Inc. | Most activated memory portion handling |
US20220351776A1 (en) * | 2021-04-30 | 2022-11-03 | Samsung Electronics Co., Ltd. | Non-volatile content addressable memory device having simple cell configuration and operating method of the same |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2307240C (en) * | 2000-05-01 | 2011-04-12 | Mosaid Technologies Incorporated | Matchline sense circuit and method |
US6262907B1 (en) * | 2000-05-18 | 2001-07-17 | Integrated Device Technology, Inc. | Ternary CAM array |
US6560156B2 (en) * | 2001-02-08 | 2003-05-06 | Integrated Device Technology, Inc. | CAM circuit with radiation resistance |
US6760249B2 (en) * | 2001-06-21 | 2004-07-06 | Pien Chien | Content addressable memory device capable of comparing data bit with storage data bit |
US7260673B1 (en) | 2001-07-20 | 2007-08-21 | Cisco Technology, Inc. | Method and apparatus for verifying the integrity of a content-addressable memory result |
US7257763B1 (en) * | 2001-08-03 | 2007-08-14 | Netlogic Microsystems, Inc. | Content addressable memory with error signaling |
US7283380B1 (en) | 2001-08-03 | 2007-10-16 | Netlogic Microsystems, Inc. | Content addressable memory with selective error logging |
US6671218B2 (en) * | 2001-12-11 | 2003-12-30 | International Business Machines Corporation | System and method for hiding refresh cycles in a dynamic type content addressable memory |
US7301961B1 (en) | 2001-12-27 | 2007-11-27 | Cypress Semiconductor Corportion | Method and apparatus for configuring signal lines according to idle codes |
US6618281B1 (en) * | 2002-05-15 | 2003-09-09 | International Business Machines Corporation | Content addressable memory (CAM) with error checking and correction (ECC) capability |
US20040015753A1 (en) * | 2002-07-16 | 2004-01-22 | Patella Benjamin J. | Detection of bit errors in content addressable memories |
US7100097B2 (en) * | 2002-07-16 | 2006-08-29 | Hewlett-Packard Development Company, L.P. | Detection of bit errors in maskable content addressable memories |
US6836419B2 (en) * | 2002-08-23 | 2004-12-28 | Micron Technology, Inc. | Split word line ternary CAM architecture |
US6760241B1 (en) | 2002-10-18 | 2004-07-06 | Netlogic Microsystems, Inc. | Dynamic random access memory (DRAM) based content addressable memory (CAM) cell |
US7237172B2 (en) | 2002-12-24 | 2007-06-26 | Micron Technology, Inc. | Error detection and correction in a CAM |
US7617356B2 (en) * | 2002-12-31 | 2009-11-10 | Intel Corporation | Refresh port for a dynamic memory |
US7054995B2 (en) * | 2003-04-23 | 2006-05-30 | Integrated Silicon Solution, Inc. | Dynamic linking of banks in configurable content addressable memory systems |
KR100525460B1 (en) * | 2003-05-23 | 2005-10-31 | (주)실리콘세븐 | SRAM compatable memory having three SAs between two memory blocks and performing REFRESH operation in which the inducing and the rewriting operation are performed seperately and Operating Method thereof |
JP2004355691A (en) | 2003-05-28 | 2004-12-16 | Hitachi Ltd | Semiconductor device |
US6900999B1 (en) | 2003-06-30 | 2005-05-31 | Integrated Device Technology, Inc. | Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio |
US6856528B1 (en) * | 2003-07-30 | 2005-02-15 | Micron Technology, Inc. | Match line sensing amplifier for content addressable memory |
US6906938B2 (en) * | 2003-08-15 | 2005-06-14 | Micron Technology, Inc. | CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture |
US7019999B1 (en) | 2003-10-08 | 2006-03-28 | Netlogic Microsystems, Inc | Content addressable memory with latching sense amplifier |
US7304875B1 (en) | 2003-12-17 | 2007-12-04 | Integrated Device Technology. Inc. | Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same |
KR100532508B1 (en) * | 2004-03-12 | 2005-11-30 | 삼성전자주식회사 | Content Addressable Memory having high speed operation |
US7187571B1 (en) * | 2004-04-09 | 2007-03-06 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
JP2006012357A (en) * | 2004-06-29 | 2006-01-12 | Fujitsu Ltd | Memory device |
JP4704078B2 (en) * | 2004-12-20 | 2011-06-15 | 富士通セミコンダクター株式会社 | Semiconductor memory |
US7145789B2 (en) * | 2005-01-05 | 2006-12-05 | Texas Instruments Incorporated | Low power low area precharge technique for a content addressable memory |
US7304873B1 (en) | 2005-01-25 | 2007-12-04 | Netlogic Microsystems, Inc. | Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor |
US7239559B2 (en) * | 2005-05-05 | 2007-07-03 | International Business Machines Corporation | Methods and apparatus for accessing memory |
US7471569B2 (en) * | 2005-06-15 | 2008-12-30 | Infineon Technologies Ag | Memory having parity error correction |
US7313047B2 (en) | 2006-02-23 | 2007-12-25 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
TW200832408A (en) * | 2007-01-19 | 2008-08-01 | Univ Nat Chiao Tung | Hierarchical search line with internal storage irrelevant entry control |
US8089793B1 (en) | 2007-12-05 | 2012-01-03 | Netlogic Microsystems, Inc. | Dynamic random access memory based content addressable storage element with concurrent read and compare |
US20090240875A1 (en) * | 2008-03-18 | 2009-09-24 | Chu Albert M | Content addressable memory with hidden table update, design structure and method |
KR101167272B1 (en) | 2009-11-04 | 2012-07-23 | 경희대학교 산학협력단 | Binary content addressable memory |
US8199547B2 (en) * | 2010-02-10 | 2012-06-12 | Freescale Semiconductor, Inc. | Error detection in a content addressable memory (CAM) |
US8553441B1 (en) | 2010-08-31 | 2013-10-08 | Netlogic Microsystems, Inc. | Ternary content addressable memory cell having two transistor pull-down stack |
US8462532B1 (en) | 2010-08-31 | 2013-06-11 | Netlogic Microsystems, Inc. | Fast quaternary content addressable memory cell |
US8625320B1 (en) | 2010-08-31 | 2014-01-07 | Netlogic Microsystems, Inc. | Quaternary content addressable memory cell having one transistor pull-down stack |
US8582338B1 (en) | 2010-08-31 | 2013-11-12 | Netlogic Microsystems, Inc. | Ternary content addressable memory cell having single transistor pull-down stack |
US8621324B2 (en) * | 2010-12-10 | 2013-12-31 | Qualcomm Incorporated | Embedded DRAM having low power self-correction capability |
US8990631B1 (en) | 2011-03-03 | 2015-03-24 | Netlogic Microsystems, Inc. | Packet format for error reporting in a content addressable memory |
US8897049B2 (en) * | 2011-05-13 | 2014-11-25 | Semiconductor Energy Laboratories Co., Ltd. | Semiconductor device and memory device including semiconductor device |
US8837188B1 (en) | 2011-06-23 | 2014-09-16 | Netlogic Microsystems, Inc. | Content addressable memory row having virtual ground and charge sharing |
US8773880B2 (en) | 2011-06-23 | 2014-07-08 | Netlogic Microsystems, Inc. | Content addressable memory array having virtual ground nodes |
US8659937B2 (en) * | 2012-02-08 | 2014-02-25 | International Business Machines Corporation | Implementing low power write disabled local evaluation for SRAM |
CN103226971B (en) * | 2013-03-21 | 2016-05-25 | 苏州宽温电子科技有限公司 | A kind of quick write-back circuit of CAM that prevents data corruption |
CN103714853B (en) * | 2013-12-24 | 2016-06-15 | 中国科学院上海高等研究院 | NAND content addressable memory |
US9583219B2 (en) | 2014-09-27 | 2017-02-28 | Qualcomm Incorporated | Method and apparatus for in-system repair of memory in burst refresh |
WO2016167821A1 (en) | 2015-04-14 | 2016-10-20 | Cambou Bertrand F | Memory circuits using a blocking state |
EP3295331A4 (en) | 2015-05-11 | 2019-04-17 | Cambou, Bertrand, F. | Memory circuit using dynamic random access memory arrays |
WO2016195736A1 (en) | 2015-06-02 | 2016-12-08 | Cambou Bertrand F | Memory circuit using resistive random access memory arrays in a secure element |
US20170110178A1 (en) * | 2015-09-17 | 2017-04-20 | Intel Corporation | Hybrid refresh with hidden refreshes and external refreshes |
CN111933198B (en) * | 2020-09-14 | 2021-02-05 | 新华三半导体技术有限公司 | Matchline detection circuit for Content Addressable Memory (CAM) |
CN113096710B (en) * | 2021-04-28 | 2023-03-31 | 清华大学 | Unit circuit and dynamic tri-state content addressing memory thereof |
TWI783767B (en) * | 2021-11-02 | 2022-11-11 | 瑞昱半導體股份有限公司 | Memory time-division control device |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4110841A (en) | 1977-12-06 | 1978-08-29 | Bell Telephone Laboratories, Incorporated | Level shifter and sense-refresh detector |
US4412314A (en) | 1980-06-02 | 1983-10-25 | Mostek Corporation | Semiconductor memory for use in conjunction with error detection and correction circuit |
JPS6055593A (en) | 1983-09-06 | 1985-03-30 | Nec Corp | Pseudo static memory |
US4653030B1 (en) | 1984-08-31 | 1997-08-26 | Texas Instruments Inc | Self refresh circuitry for dynamic memory |
JPS62165794A (en) * | 1986-01-17 | 1987-07-22 | Toshiba Corp | Memory cell for associative storage |
JPH01196792A (en) | 1988-01-29 | 1989-08-08 | Mitsubishi Electric Corp | Semiconductor memory device |
US4970689A (en) | 1988-03-07 | 1990-11-13 | International Business Machines Corporation | Charge amplifying trench memory cell |
JPH01307095A (en) * | 1988-06-01 | 1989-12-12 | Mitsubishi Electric Corp | Nonvolatile cam |
US5319590A (en) | 1992-12-04 | 1994-06-07 | Hal Computer Systems, Inc. | Apparatus for storing "Don't Care" in a content addressable memory cell |
US5446685A (en) | 1993-02-23 | 1995-08-29 | Intergraph Corporation | Pulsed ground circuit for CAM and PAL memories |
KR0135699B1 (en) * | 1994-07-11 | 1998-04-24 | 김주용 | Dual port dynamic cam cell and refresh circuit |
US5703803A (en) | 1996-04-29 | 1997-12-30 | Intel Corporation | Dynamically controlled, cross-stacked CAM cell |
US5757693A (en) | 1997-02-19 | 1998-05-26 | International Business Machines Corporation | Gain memory cell with diode |
US5761114A (en) | 1997-02-19 | 1998-06-02 | International Business Machines Corporation | Multi-level storage gain cell with stepline |
US5949696A (en) * | 1997-06-30 | 1999-09-07 | Cypress Semiconductor Corporation | Differential dynamic content addressable memory and high speed network address filtering |
US5909400A (en) | 1997-08-22 | 1999-06-01 | International Business Machines Corporation | Three device BICMOS gain cell |
US5999435A (en) | 1999-01-15 | 1999-12-07 | Fast-Chip, Inc. | Content addressable memory device |
CA2266062C (en) * | 1999-03-31 | 2004-03-30 | Peter Gillingham | Dynamic content addressable memory cell |
US6188594B1 (en) * | 1999-06-09 | 2001-02-13 | Neomagic Corp. | Reduced-pitch 6-transistor NMOS content-addressable-memory cell |
US6078513A (en) * | 1999-06-09 | 2000-06-20 | Neomagic Corp. | NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select |
-
2000
- 2000-12-06 US US09/730,673 patent/US6430073B1/en not_active Expired - Lifetime
-
2001
- 2001-11-26 KR KR10-2001-0073680A patent/KR100472113B1/en not_active IP Right Cessation
- 2001-11-30 SG SG200107479A patent/SG96264A1/en unknown
- 2001-12-03 TW TW090129804A patent/TW571312B/en not_active IP Right Cessation
- 2001-12-03 JP JP2001368965A patent/JP3737745B2/en not_active Expired - Fee Related
- 2001-12-06 CN CNB011429828A patent/CN1186782C/en not_active Expired - Fee Related
Cited By (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6879504B1 (en) | 2001-02-08 | 2005-04-12 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same |
US6822886B2 (en) * | 2001-09-24 | 2004-11-23 | Micron Technology, Inc. | Reducing signal swing in a match detection circuit |
US20030058673A1 (en) * | 2001-09-24 | 2003-03-27 | Alon Regev | Reducing signal swing in a match detection circuit |
US7269040B2 (en) | 2002-03-08 | 2007-09-11 | Micron Technology, Inc. | Static content addressable memory cell |
US6952359B2 (en) | 2002-03-08 | 2005-10-04 | Micron Technology, Inc. | Static content addressable memory cell |
US20060181911A1 (en) * | 2002-03-08 | 2006-08-17 | Hu Shane C | Static content addressable memory cell |
US20040095793A1 (en) * | 2002-03-08 | 2004-05-20 | Hu Shane Ching-Feng | Static content addressable memory cell |
US20060114705A1 (en) * | 2002-03-08 | 2006-06-01 | Hu Shane C | Static content addressable memory cell |
US20040095794A1 (en) * | 2002-03-08 | 2004-05-20 | Hu Shane Ching-Feng | Static content addressable memory cell |
US6751110B2 (en) * | 2002-03-08 | 2004-06-15 | Micron Technology, Inc. | Static content addressable memory cell |
US7099172B2 (en) | 2002-03-08 | 2006-08-29 | Micron Technology, Inc. | Static content addressable memory cell |
US20030169612A1 (en) * | 2002-03-08 | 2003-09-11 | Hu Shane Ching-Feng | Static content addressable memory cell |
US7307860B2 (en) | 2002-03-08 | 2007-12-11 | Micron Technology, Inc. | Static content addressable memory cell |
US6888732B2 (en) | 2002-03-08 | 2005-05-03 | Micron Technology, Inc. | Static content addressable memory cell |
US20050190639A1 (en) * | 2002-03-08 | 2005-09-01 | Hu Shane C. | Static content addressable memory cell |
US20050190201A1 (en) * | 2002-07-23 | 2005-09-01 | Baer David A. | System and method for providing graphics using graphical engine |
US20050024976A1 (en) * | 2003-04-25 | 2005-02-03 | Samsung Electronics Co., Ltd. | Content addressable memory device |
US7002822B2 (en) * | 2003-04-25 | 2006-02-21 | Samsung Electronics Co., Ltd. | Content addressable memory device |
US7035133B2 (en) * | 2003-05-16 | 2006-04-25 | Silicon7 Inc. | SRAM-compatible memory device performing refresh operation having separate fetching and writing operation periods and method of driving the same |
US20040228165A1 (en) * | 2003-05-16 | 2004-11-18 | Kim Gi Hong | SRAM-compatible memory device performing refresh operation having separate fetching and writing operation periods and method of driving the same |
US7345936B2 (en) * | 2003-05-30 | 2008-03-18 | Renesas Technology Corp. | Data storage circuit |
US20040243758A1 (en) * | 2003-05-30 | 2004-12-02 | Renesas Technology Corp. | Data storage circuit |
US6870749B1 (en) | 2003-07-15 | 2005-03-22 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors |
US6987684B1 (en) | 2003-07-15 | 2006-01-17 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein |
US7193876B1 (en) | 2003-07-15 | 2007-03-20 | Kee Park | Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors |
US7499302B2 (en) * | 2003-07-25 | 2009-03-03 | Micron Technology, Inc. | Noise reduction in a CAM memory cell |
US20050018463A1 (en) * | 2003-07-25 | 2005-01-27 | Vipul Patel | Noise reduction in a CAM memory cell |
US6954369B2 (en) * | 2003-07-25 | 2005-10-11 | Micron Technology, Inc. | Noise reduction in a CAM memory cell |
US20050254277A1 (en) * | 2003-07-25 | 2005-11-17 | Vipul Patel | Noise reduction in a cam memory cell |
US7240148B2 (en) | 2003-10-08 | 2007-07-03 | Micron Technology, Inc. | Parity-scanning and refresh in dynamic memory devices |
US20070229525A1 (en) * | 2003-10-08 | 2007-10-04 | Tom Teng | Parity-scanning and refresh in dynamic memory devices |
US20050080988A1 (en) * | 2003-10-08 | 2005-04-14 | Tom Teng | Parity-scanning and refresh in dynamic memory devices |
US7107390B2 (en) * | 2003-10-08 | 2006-09-12 | Micron Technology, Inc. | Parity-scanning and refresh in dynamic memory devices |
US7617355B2 (en) | 2003-10-08 | 2009-11-10 | Micron Technology, Inc. | Parity-scanning and refresh in dynamic memory devices |
EP1782206A2 (en) * | 2004-06-29 | 2007-05-09 | Cisco Technology, Inc. | Error protection for lookup operations in content-addressable memory entries |
WO2006007250A2 (en) | 2004-06-29 | 2006-01-19 | Cisco Technology, Inc. | Error protection for lookup operations in content-addressable memory entries |
EP1782206A4 (en) * | 2004-06-29 | 2009-10-28 | Cisco Tech Inc | Error protection for lookup operations in content-addressable memory entries |
US8217920B2 (en) * | 2005-11-21 | 2012-07-10 | Nec Corporation | Data-holding circuit and substrate for a display device |
US20070115229A1 (en) * | 2005-11-21 | 2007-05-24 | Nec Corporation | Display device and apparatus using same |
US9947279B2 (en) | 2005-11-21 | 2018-04-17 | Nlt Technologies, Ltd. | Data-holding circuit and substrate for a display device |
US9489903B2 (en) | 2005-11-21 | 2016-11-08 | Nlt Technologies, Ltd. | Data-holding circuit and substrate for a display device |
US20070297210A1 (en) * | 2006-06-23 | 2007-12-27 | Yoshihiro Ueda | Semiconductor memory device and writing method thereof |
US7577041B2 (en) * | 2006-06-23 | 2009-08-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device and writing method thereof |
US8415957B2 (en) * | 2009-07-02 | 2013-04-09 | Novatek Microelectronics Corp. | Capacitance measurement circuit and method |
US20110001491A1 (en) * | 2009-07-02 | 2011-01-06 | Novatek Microelectronics Corp. | Capacitance measurement circuit and method |
WO2015149037A1 (en) * | 2014-03-28 | 2015-10-01 | Synopsys, Inc. | Most activated memory portion handling |
US9431085B2 (en) | 2014-03-28 | 2016-08-30 | Synopsys, Inc. | Most activated memory portion handling |
US20220351776A1 (en) * | 2021-04-30 | 2022-11-03 | Samsung Electronics Co., Ltd. | Non-volatile content addressable memory device having simple cell configuration and operating method of the same |
US11996150B2 (en) * | 2021-04-30 | 2024-05-28 | Samsung Electronics Co., Ltd. | Non-volatile content addressable memory device having simple cell configuration and operating method of the same |
Also Published As
Publication number | Publication date |
---|---|
US6430073B1 (en) | 2002-08-06 |
TW571312B (en) | 2004-01-11 |
JP2002197872A (en) | 2002-07-12 |
SG96264A1 (en) | 2003-05-23 |
CN1357892A (en) | 2002-07-10 |
JP3737745B2 (en) | 2006-01-25 |
KR100472113B1 (en) | 2005-03-08 |
KR20020071702A (en) | 2002-09-13 |
CN1186782C (en) | 2005-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6430073B1 (en) | Dram CAM cell with hidden refresh | |
US6563754B1 (en) | DRAM circuit with separate refresh memory | |
US6560156B2 (en) | CAM circuit with radiation resistance | |
US7821858B2 (en) | eDRAM hierarchical differential sense AMP | |
US7561454B2 (en) | Compare circuit for a content addressable memory cell | |
US7724559B2 (en) | Self-referenced match-line sense amplifier for content addressable memories | |
US6256216B1 (en) | Cam array with minimum cell size | |
US6310880B1 (en) | Content addressable memory cells and systems and devices using the same | |
US6744688B2 (en) | Searchline control circuit and power reduction method | |
KR100718902B1 (en) | Matchline sense circuit and method | |
US6678198B2 (en) | Pseudo differential sensing method and apparatus for DRAM cell | |
US6400593B1 (en) | Ternary CAM cell with DRAM mask circuit | |
US20080016277A1 (en) | Dram hierarchical data path | |
JPH1050076A (en) | Associated memory | |
KR20040018109A (en) | Semiconductor memory device storing ternary data signal | |
US6188594B1 (en) | Reduced-pitch 6-transistor NMOS content-addressable-memory cell | |
US7342839B2 (en) | Memory cell access circuit | |
US20050152166A1 (en) | Folded DRAM CAM cell | |
US6339550B1 (en) | Soft error immune dynamic random access memory | |
US7709299B2 (en) | Hierarchical 2T-DRAM with self-timed sensing | |
US20040109338A1 (en) | Ternary content addressable memory cell | |
JP2004355691A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BATSON, KEVIN A.;BUSCH, ROBERT E.;KOCH, GARRETT S.;REEL/FRAME:011374/0051 Effective date: 20001204 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 12 |
|
SULP | Surcharge for late payment |
Year of fee payment: 11 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |