US20020067625A1 - High voltage circuit - Google Patents
High voltage circuit Download PDFInfo
- Publication number
- US20020067625A1 US20020067625A1 US09/933,239 US93323901A US2002067625A1 US 20020067625 A1 US20020067625 A1 US 20020067625A1 US 93323901 A US93323901 A US 93323901A US 2002067625 A1 US2002067625 A1 US 2002067625A1
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- US
- United States
- Prior art keywords
- transformer
- primary winding
- switching element
- circuit
- inductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/18—Generation of supply voltages, in combination with electron beam deflecting
- H04N3/185—Maintaining dc voltage constant
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Dc-Dc Converters (AREA)
- Details Of Television Scanning (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a high voltage generation circuit and, more particularly, to a high voltage generation circuit for generating a high voltage to be supplied to a CRT (cathode ray tube) or the like.
- 2. Description of the Related Art
- FIG. 1 is a circuit diagram showing an example of a high voltage generation circuit as the background of the present invention. The high
voltage generation circuit 10 includes atransformer 12. The primary winding of thetransformer 12 is connected to the anode of adiode 14. The cathode of thediode 14 is connected to the drain ofFET 16 as a switching element. The source of the FET 16 is connected to aresistor 18. The other side of theresistor 18 is grounded. Adiode 20 is connected in parallel to the series circuit comprising thediode 14, theFET 16, and theresistor 18. The cathode of thediode 20 is connected to the anode side of thediode 14. The anode of thediode 20 is grounded. - A series circuit comprising a
resonance capacitor 22 and adiode 24 is connected in parallel to thediode 20. One end of theresonance capacitor 22 is connected to the anode side of thediode 14, and the other end of theresonance capacitor 22 is connected to the cathode of thediode 24. The anode of thediode 24 is grounded. Moreover, the node between theresonance capacitor 22 and thediode 24 is connected to the anode of anotherdiode 26. The cathode of thediode 26 is connected to the primary winding of thetransformer 12 via aringing suppression circuit 28. Theringing suppression circuit 28 comprises acapacitor 30, aresistor 32, and aninductor 34. A power supply +B is connected between thediode 26 and theringing suppression circuit 28. The node between thediode 26 and theringing suppression circuit 28 is grounded via acapacitor 36 and anelectrolytic capacitor 38. - To the gate of the
FET 16, a signal for on and off control thereof is provided from a PWM (Pulse Width Modulation)control circuit 40. Voltage produced by dividing a secondary output voltage of thetransformer 12 is input to thePWM control circuit 40. This voltage and a horizontal driving signal are input to thePWM control circuit 40. ThePWM control circuit 40 generates a control signal for controlling theFET 16. A node between theFET 16 and theresistor 18 is connected to a protection circuit provided in thePWM control circuit 40, so that an over-current flowing in the circuit is detected. - FIG. 2 shows waveforms at the respective portions of the high
voltage generation circuit 10. FIGS. 2(a), (b), and (c), respectively represent the waveform chart of a signal for controlling theFET 16, the voltage at point A shown in FIG. 1, and the current flowing through the primary winding of thetransformer 12. First, when the FET 16 is turned on at t0, current flows from the power supply +B through thediode 14, theFET 16, and theresistor 18. Electromagnetic energy is stored in the primary winding of thetransformer 12, due to the current. - The FET16 is turned off at t1. At this time, current flows from the primary winding of the
transformer 12 through theresonance capacitor 22 and thediode 26, and the primary winding of thetransformer 12 and theresonance capacitor 22 start to resonate. As shown in the waveform chart of FIG. 2(b), a flyback pulse is generated. The flyback pulse becomes maximum when all of the electromagnetic energy stored in thetransformer 12 is converted to electrostatic energy of theresonance capacitor 22. - After all of the electromagnetic energy stored in the primary winding of the
transformer 12 is transferred to thecapacitor 22, reverse current flows through thediode 24, theresonance capacitor 22, and the primary winding of thetransformer 12. Thus, the electrostatic energy in theresonance capacitor 22 is reversely converted to the electromagnetic energy in the primary winding of thetransformer 12. At this time, thediode 14 prevents electric charge stored in the parasitic capacitance of theFET 16 from flowing out toward the primary winding side. - At t2 when the flyback pulse is completed, the potential at the point A becomes zero. Then, the
diode 20 is turned on, so that current flows from the ground side of thediode 20 into the primary winding of thetransformer 12. The current increases the voltage at the point A. The voltage at the point A has the same potential as that of the power supply+B at t3. At this time, thediode 20 is turned off, and the current becomes zero. Then, as regards the flow of current from the power supply+B into theresonance capacitor 22, the potential at both ends of theresonance capacitor 22 is clamped to the voltage of the power supply +B by a current-blocking clamp circuit comprising thediodes transformer 12 into theresonance capacitor 22. Then, the FET 16 is turned on at t4, so that current flows from the power supply +B toward the primary winding, and the circuit returns to the initial state at to. This operation is repeated. Thus, the circuit operation is continued. Accordingly, the voltage of the flyback pulse is increased by thetransformer 12, so that high voltage is output from the secondary winding. - Capacitances included in the circuit, such as the parasitic capacitance in the
FET 16, exist at t3 when the current becomes zero. Accordingly, resonance with the primary winding of thetransformer 12 occurs, and a quiescent ringing pulse is generated during the time from t3 to t4. Theringing suppression circuit 28 is used to suppress the ringing vibration pulse. - In the high
voltage generation circuit 10, the primary inductance Lp of thetransformer 12 is designed so as to satisfy the condition of Lp≦Eb·Ts/Ipp in which Eb is a source voltage, Ts is the time from the completion of a flyback pulse to the start of the next flyback pulse, and Ipp is the allowed current of theFET 16. Conventionally, such a high voltage generation circuit is designed such that the above-mentioned condition is satisfied, and a required output voltage can be obtained from the secondary winding of thetransformer 12. - However, if the FET is turned on nearly at the peak of the quiescent ringing pulse as shown in FIG. 3, the high voltage of the quiescent ringing pulse is instantaneously terminated. Thus, the ringing which is determined by the distributed capacitance of the
transformer 12 and so forth is generated, so that overshoot and undershoot occur in current flowing through the primary winding of thetransformer 12. The generation of such overshoot and undershoot causes a problem in that losses in thetransformer 12 and a resistance loss in the ringing suppression circuit are increased. - Accordingly, it is a principal object of the present invention to provide a high voltage generation circuit in which the loss caused by overshoot and undershoot when the switching element is turned on can be reduced.
- According to the present invention, there is provided a high voltage generation circuit which comprises a transformer, a power supply for supplying power to the primary winding of the transformer, a switching element for controlling current flowing through the primary winding of the transformer from the power supply, and a resonance capacitor which resonates with the primary winding of the transformer when the switching element is off, so that a flyback pulse is generated, the switching element being controlled so as to be switched on nearly at the bottom of a quiescent ringing pulse which is produced by the resonance of the inductance of the primary winding of the transformer with the capacitance included in a circuit connected to the primary winding of the transformer, after the flyback pulse is generated.
- In the high voltage generation circuit, preferably, the control of the switching element is carried out by adjusting at least one of the primary inductance of the transformer, the distributed inductance, the voltage of the power supply, and resonance capacitance.
- Since the timing at which the switching element is turned on in the high voltage generation circuit is controlled so as to occur nearly at the bottom of the quiescent ringing pulse, the quiescent ringing pulse is terminated in the low voltage portion thereof. Accordingly, overshoot and undershoot is suppressed from generating in the current flowing through the primary winding of the transformer, and losses in the transformer and the ringing suppression circuit can be reduced.
- As seen in the above description, controlling the timing at which the switching element is turned on so as to coincide with the bottom of the quiescent ringing pulse or its neighborhood can be made by adjusting the primary inductance of the transformer, the distributed inductance, the voltage of the power supply, the resonance capacitance, and the like.
- The above-described and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings.
- FIG. 1 is a circuit diagram of an example of a high voltage generation circuit as the background of the present invention;
- FIG. 2(a) shows a signal for controlling FET of FIG. 1, FIG. 2(b) shows voltage at point A of FIG. 1, and FIG. 2(c) shows current flowing through the primary winding of the transformer of FIG. 1;
- FIG. 3 is a waveform chart of current flowing through the primary winding when the FET is turned on nearly at the top of a quiescent ringing pulse;
- FIG. 4 illustrates a relation between the quiescent ringing pulse and the current flowing through the primary winding when the primary inductance of the transformer is changed; and
- FIG. 5 is a waveform of current flowing through the primary winding when the FET is turned on nearly at the bottom of the quiescent ringing pulse.
- In the high
voltage generation circuit 10 shown in FIG. 1, the primary inductance Lp of thetransformer 12 has a maximum control limit in the PWM control system, expressed by the condition of Ipp=Eb·Ts/Lp in which Eb is the power supply voltage, Ts is the time from the completion of a flyback pulse to the start of the next flyback pulse, and Ipp is the allowed current of theFET 16. Therefore, the highvoltage generation circuit 10 to be operated in the PWM control system is designed so as to satisfy the condition of Lp≦Eb·Ts/Ipp. Moreover, the time at which theFET 16 starts to switch on can be set to coincide substantially with the bottom of the quiescent ringing pulse by controlling the primary inductance of thetransformer 12, the distributed inductance, the voltage of the power supply +B, the resonance capacitance, and so forth. - For example, the primary inductance of the
transformer 12 can be controlled by adjustment of the number of turns of thetransformer 12. The current flowing through the primary winding when the primary inductance Lp of thetransformer 12 is changed will be discussed. The slope of the current waveform caused when theFET 16 is on is defined by ΔIpp/Δt. Here, the allowed current Ipp is Ipp=Eb·t/Lp. Thus, the slope of the current flowing through the primary winding of thetransformer 12 can be expressed as Eb/Lp. Accordingly, when the primary inductance Lp of thetransformer 12 is adjusted from Lp1 to Lp2 (Lp2>Lp1), the slope of the current waveform is reduced. Thus, the timing at which theFET 16 is turned on can be made earlier. By adjusting the primary inductance Lp of thetransformer 12 as described above, the time at which theFET 16 starts to be turned on can be controlled. Thus, the time at which theFET 16 starts to be turned on can be made to coincide substantially with the bottom of the quiescent ringing pulse. - Moreover, the on-start time of the
FET 16 may be controlled so as to coincide substantially with the bottom of the quiescent ringing pulse by adjusting the resonance capacitance of the circuit connected to the primary winding of thetransformer 12. Thus, the on-start time of theFET 16 may be controlled, or the time when the quiescent ringing pulse is generated may be controlled. Any manner may be employed, provided that the on-start time of theFET 16 can be made to coincide substantially with the bottom of the quiescent ringing pulse. - As shown in the above description, by turning on the
FET 16 nearly at the bottom of the quiescent ringing pulse, the quiescent ringing pulse can be terminated when the voltage is in the low state. Therefore, substantially no overshoot or undershoot in the waveform of current flowing through the primary winding of thetransformer 12 is generated when theFET 16 is turned on as shown in FIG. 5. Accordingly, losses in thetransformer 12 and in the ringingsuppression circuit 28, which may be caused by the overshoot or undershoot, can be suppressed. Moreover, the whole power consumption of the highvoltage generation circuit 10 can be reduced. These effects can be also obtained for a high voltage generation circuit excluding the clamping circuit comprising thediodes - In the high voltage generation circuit according to the present invention, the overshoot or undershoot of current flowing through the primary winding of the transformer can be suppressed, and thereby, losses in the transformer and in the ringing suppression circuit can be reduced. Accordingly, the power consumption of the high voltage generation circuit can be decreased.
- Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention should be limited not by the specific disclosure herein, but only by the appended claims.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-262840 | 2000-08-31 | ||
JP2000262840A JP3475923B2 (en) | 2000-08-31 | 2000-08-31 | High voltage generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020067625A1 true US20020067625A1 (en) | 2002-06-06 |
US6434022B1 US6434022B1 (en) | 2002-08-13 |
Family
ID=18750460
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/933,239 Expired - Lifetime US6434022B1 (en) | 2000-08-31 | 2001-08-20 | High voltage circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US6434022B1 (en) |
JP (1) | JP3475923B2 (en) |
KR (1) | KR100380108B1 (en) |
CN (1) | CN1178370C (en) |
TW (1) | TW533666B (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4563731A (en) * | 1982-01-07 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Resonant type constant voltage supply apparatus |
DE3751770T2 (en) * | 1986-09-20 | 1996-11-14 | Canon Kk | Power source apparatus |
JP3647166B2 (en) * | 1996-09-11 | 2005-05-11 | キヤノン株式会社 | Power circuit |
-
2000
- 2000-08-31 JP JP2000262840A patent/JP3475923B2/en not_active Expired - Lifetime
-
2001
- 2001-08-08 TW TW090119310A patent/TW533666B/en not_active IP Right Cessation
- 2001-08-20 US US09/933,239 patent/US6434022B1/en not_active Expired - Lifetime
- 2001-08-24 CN CNB011209836A patent/CN1178370C/en not_active Expired - Lifetime
- 2001-08-31 KR KR10-2001-0053356A patent/KR100380108B1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP3475923B2 (en) | 2003-12-10 |
JP2002078337A (en) | 2002-03-15 |
KR100380108B1 (en) | 2003-04-11 |
CN1178370C (en) | 2004-12-01 |
CN1340905A (en) | 2002-03-20 |
TW533666B (en) | 2003-05-21 |
KR20020018616A (en) | 2002-03-08 |
US6434022B1 (en) | 2002-08-13 |
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