US20020056924A1 - Semiconductor package having an insulating region on an edge of a chip to prevent shorts - Google Patents
Semiconductor package having an insulating region on an edge of a chip to prevent shorts Download PDFInfo
- Publication number
- US20020056924A1 US20020056924A1 US10/035,634 US3563401A US2002056924A1 US 20020056924 A1 US20020056924 A1 US 20020056924A1 US 3563401 A US3563401 A US 3563401A US 2002056924 A1 US2002056924 A1 US 2002056924A1
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- Prior art keywords
- semiconductor chip
- wafer
- edge
- substrate
- semiconductor
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Definitions
- a semiconductor package in another embodiment, includes a semiconductor chip, a substrate, bond wires, and a resin encapsulation portion.
- the semiconductor chip includes a silicon substrate having an active area containing integrated circuits, a plurality of pads electrically connected to the integrated circuits, a non-active layer on the active area except for the pads, a polyimide layer formed on the non-active layer, and an insulation layer along the edge of the silicon substrate.
- the pads are along a center portion of the active area.
- the surface of the semiconductor chip that is opposite the active area attaches to the upper surface of the substrate.
- the bonding wires electrically connect the pads of the semiconductor chip to the substrate.
- the manufacturing method includes removing the polyimide layer from the pads; cutting the wafer along the scribe area to separate the individual semiconductor chips; attaching one or more of the semiconductor chips to a substrate; attaching bonding wires that electrically connect the pads of the semiconductor chip to the substrate; and encapsulating the semiconductor chip and the bonding wires.
- the bonding wire contacts the polyimide layer at the edge of the semiconductor chip, thereby preventing electrical shorts between the bonding wire and the silicon substrate.
- FIG. 2 is a cross-sectional view illustrating separation of the semiconductor chips form in a wafer.
- FIG. 4 b is a cross-sectional view along the line 4 b - 4 b of FIG. 4 a before separation of individual semiconductor chips.
- FIG. 5 is a cross-sectional view showing a ball grid array package according to another embodiment of the present invention.
- FIG. 7 d is a cross-sectional view of the wafer of FIG. 7 c after backside grinding.
- FIG. 9 c is cross-sectional view of the wafer of FIG. 9 b after cutting the wafer along scribe lines.
- FIG. 4 a is a plan view of a silicon wafer 180 that includes a plurality of semiconductor chips 110 .
- Conventional wafer manufacturing processes which are well-known in the art, can form integrated circuits on the semiconductor chips 110 .
- the wafer includes scribe lines in a scribe area 182 that lacks circuitry and is between neighboring semiconductor chips 110 . Since the manufacturing method of the circuit devices in the semiconductor chips 110 is not critical to this invention, a detailed description of the integrated circuit manufacturing process is omitted.
- FIG. 5 shows the complete BGA package 300 using the semiconductor chip 210 having the insulation layer 215 formed by the potting method.
- FIG. 8 is a cross-sectional view showing a BGA package 400 according to yet another embodiment of the invention.
- the BGA package 400 includes a semiconductor chip 310 having an insulation layer 315 on the edge of its active area.
- the remaining structure of the BGA package 400 is the same as described above.
- a potting or printing method forms the insulation layer 315 .
- a bonding wire 350 which connects a pad 312 of the semiconductor chip 310 to a top wiring pattern 323 of a substrate 320 , contacts the insulation layer 315 formed on the edge 318 of the semiconductor chip 310 .
- the insulating layer 315 thereby prevents electrical shorts between the bonding wire 350 and the silicon substrate 390 .
- a wafer before or after the backside grinding process may be used for fabrication of the semiconductor chip 410 .
- a wafer cutting process is soon after forming the insulating material in the groove.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip. A groove can be formed in the scribe area and then filled with insulating material before cutting along the groove. As a result, the insulating material from inside the groove extends onto the sides of the separated semiconductor chips. If the groove is formed before backside grinding of the wafer, the insulating region can cover the side of a chip. The insulating material is typically an epoxy type resin that can be cut without chipping.
Description
- This application is a divisional of and claims priority from U.S. patent application Ser. No. 09/483,252 entitled “Semiconductor Package Having An Insulating Region On An Edge Of A Chip To Prevent Shorts And A Manufacturing Method Thereof”, filed Jan. 14, 2000.
- 1. Field of the invention
- The present invention relates to integrated circuit packages and manufacture of integrated circuit packages and more particularly to preventing electrical shorts that result from bonding wires contacting the edge of a semiconductor chip.
- 2. Description of the Related Art
- A typical goal in manufacture of electronic appliances is to make the electronic appliances small and thin. To meet this goal, the integrated circuits in the electronic appliances also need to be small and thin. Accordingly, high-density integration, which provides smaller semiconductor chips, and efficient packaging, which provides smaller IC packages, have become very important for the devices in electronic appliances. In the computer field, semiconductor chips need to be relatively large to accommodate the required capabilities and the large numbers of circuit elements in devices, such as RAMs (Random Access Memories) and Flash memories. Accordingly, smaller packages for the chips have been studied.
- One way to reduce chip size is to form a center pad type semiconductor chip. Generally, a center pad type semiconductor chip is smaller than an edge pad type semiconductor chip that contains the same circuitry. Accordingly, many integrated circuit manufacturers make semiconductor chips of the center pad type to obtain more chips per wafer.
- One of the packages recently developed is the ball grid array (BGA) package. The BGA package has advantages of requiring a small mounting area on a motherboard and providing superior electrical characteristics when compared to a plastic package. In a BGA package, a printed circuit board is used instead of the lead frame common to plastic packages. A semiconductor chip attaches to one surface of the circuit board. On the opposite surface of the circuit board are solder balls that act as external terminals for direct attachment to a motherboard. The BGA package has the advantage of a high mounting density on the motherboard. However, bonding wires in a package containing a center pad type semiconductor chip extend across part of the semiconductor chip and then down to a lead frame or printed circuit board on which the semiconductor chip is mounted. These bonding wires can sag or otherwise contact the edge of an active surface of the semiconductor chip and create electrical shorts.
- FIG. 1 shows a cross-sectional view of a known
BGA package 100. FIG. 2 shows a cross-sectional view of a wafer being separated intosemiconductor chips 10, one of which is in the BGA package of FIG. 1. As shown in FIGS. 1 and 2, the BGApackage 100 includes thesemiconductor chip 10 that is mounted on an upper surface of asubstrate 20.Bonding wires 50 electrically connect apad 12 on thesemiconductor chip 10 to thesubstrate 20. A molding resin encapsulates an upper surface of thesubstrate 20 including thesemiconductor chip 10 and thebonding wire 50, thereby forming aresin encapsulation portion 30.Solder balls 40 on a lower surface of thesubstrate 20 connect to thesemiconductor chip 10 viaconductive patterns 24 andconductive vias 26. - The
substrate 20 is a printed circuit board including asubstrate body 22. Theconductive patterns 24 include atop wiring pattern 23 on the upper surface of thesubstrate body 22 and and abottom wiring pattern 25 formed on the lower surface of thesubstrate body 22. Thebonding wires 50 electrically connect thebonding pads 12 to thetop wiring pattern 23.Conductive vias 26 electrically connect to thetop wiring pattern 23 to thebottom wiring pattern 25 on which thesolder balls 40 reside. - The
semiconductor chip 10 is of the center pad type and has thebonding pads 12 in a central portion of an active area. Thesemiconductor chip 10 also includes asilicon substrate 90, anitride layer 14, and apolyimide layer 16. Integrated circuit elements reside in and onsilicon substrate 90, andnitride layer 14 as a non-active passivation layer protects the integrated circuits andpads 12.Polyimide layer 16 helps resist collection of an electrostatic charge on thenitride layer 14 and damage from alpha rays. - As shown in FIG. 2, scribe
areas 82 separate the semiconductor chips formed in awafer 80. Adiamond cutter 60 cuts wafer 80 along thescribe area 82 and separatesindividual semiconductor chips 10. To facilitate cutting of thewafer 80, polyimide layers are absent from thescribe areas 82. Otherwise, the polyimide can stick to cutter 60 and cause chipping of thewafer 80. - Returning to FIG. 1, the length of a
bonding wire 50 that connects apad 12 and thetop wiring pattern 23 of thesubstrate 20 is longer than that of a bonding wire in packaging for a semiconductor chip of the edge pad type. Further, thebonding wire 50 is typically at a low height above thechip 10 to reduce the thickness of thesemiconductor package 100. Accordingly, thebonding wire 50 may contact theedge 18 of the active area of thesemiconductor chip 10. - As noted above, the
polyimide layer 16 is missing from the edge of the active area of thesemiconductor chip 10, and anitride layer 14 is exposed. When the bonding wire sags or otherwise contacts theedge 18 ofsemiconductor chip 10, thenitride layer 14 may insulate thebonding wire 50 from underlying integrated circuits, but electrical shorts can result because the nitride layer is thin and may be chipped. The electrical shorts are often a consequence of the mechanical cutting of a wafer. A cutting process preferably cuts thenitride layer 14 to form a very smooth surface, and chipping during the cutting process can expose the edge of an active surface in thesilicon substrate 90 below thenitride layer 14 and allow shorts with thebonding wire 50. - Increasing the height of the bonding wire to avoid contact with the edge of the semiconductor chip avoids electrical shorts, but increasing the height of the bonding wire also increases the thickness of the semiconductor package. Additionally, larger semiconductor chips have longer distance from the pads to the edge in the semiconductor chip, and the thickness of the packages must increase in proportion to the size of the chip. Otherwise the probability of the bonding wire contacting the edge of the semiconductor chip increases, and the problem of electrical shorts arises.
- In accordance with an aspect of the present invention, a semiconductor package has an insulating region at the edge of the active area of the semiconductor chip to avoid electrical shorts when bonding wires contact the edge of the active area of the semiconductor chip.
- In one embodiment of the invention, a semiconductor package includes a semiconductor chip, a substrate, and a resin encapsulation portion. The semiconductor chip includes a silicon substrate having an active area containing integrated circuits and a plurality of pads. The pads electrically connect to the integrated circuits and are along a center portion of the active area. A non-active layer overlies the active area except for the pads, and a polyimide layer is on the non-active layer. The polyimide layer helps prevent damage resulting from electrical shorts or alpha rays. A surface of the semiconductor chip, which is the opposite the active area of the semiconductor chip, attaches to an upper surface of the substrate. One or more bonding wires electrically connect the pads of the semiconductor chip to the substrate. The resin encapsulation portion encapsulates the semiconductor chip and bonding wires on the upper surface of the substrate. External terminals are on the lower surface of the substrate and electrically connected to the semiconductor chip. At the edge of the substrate, the boding wire contacts with the polyimide layer, thereby preventing electrical shorts between the bonding wire and the silicon substrate.
- In another embodiment of the present invention, a semiconductor package includes a semiconductor chip, a substrate, bond wires, and a resin encapsulation portion. The semiconductor chip includes a silicon substrate having an active area containing integrated circuits, a plurality of pads electrically connected to the integrated circuits, a non-active layer on the active area except for the pads, a polyimide layer formed on the non-active layer, and an insulation layer along the edge of the silicon substrate. The pads are along a center portion of the active area. The surface of the semiconductor chip that is opposite the active area attaches to the upper surface of the substrate. The bonding wires electrically connect the pads of the semiconductor chip to the substrate. The resin encapsulation portion encapsulates the semiconductor chip and bonding wires at the upper surface of the substrate. External terminals are on the lower surface of the substrate and electrically connected to the semiconductor chip. At the edge of the silicon substrate, a bonding wire contacts the insulation layer, thereby preventing electrical shorts between the bonding wire and the silicon substrate. Preferably, the insulation layer is on the edge of the active surface of the semiconductor chip and may extend over a neighboring portion of the side surface of the semiconductor chip. A plastic resin of an epoxy type can be used in the insulation layer.
- Another embodiment of the present invention is a method for manufacturing a semiconductor package. The manufacturing method uses a semiconductor wafer having a plurality of semiconductor chips and a scribe area between the semiconductor chips. Each semiconductor chip includes integrated circuits on an active area of the semiconductor wafer, a plurality of pads electrically connected to the integrated circuits, a non-active layer on the active area except for the pads, and a polyimide layer formed on the non-active layer to prevent damage from electrical shorts or alpha rays. The manufacturing method includes removing the polyimide layer from the pads; cutting the wafer along the scribe area to separate the individual semiconductor chips; attaching one or more of the semiconductor chips to a substrate; attaching bonding wires that electrically connect the pads of the semiconductor chip to the substrate; and encapsulating the semiconductor chip and the bonding wires. The bonding wire contacts the polyimide layer at the edge of the semiconductor chip, thereby preventing electrical shorts between the bonding wire and the silicon substrate.
- In the above method, the wafer cutting uses a diamond cutter with a grit size of 2 through 4 μm or 0.3 through 3 μm, and the wafer is cut along the scribe area at a cutting rate of 20 mm of depth per second and a rotational speed between 35,000 and 40,000 rpm.
- In an another embodiment of the present invention, a method for manufacturing a semiconductor package again starts with a semiconductor wafer including a plurality of semiconductor chips and a scribe area between the semiconductor chips. Each semiconductor chip includes integrated circuits on an active area of the wafer, a plurality of pads electrically connected to the integrated circuits, a non-active layer formed on the active area except for the pads, and a polyimide layer formed on the non-active layer. The method includes removing the polyimide layer from the pad and the scribe area; forming an insulation layer on the scribe area; cutting the wafer along the scribe area to separate individual semiconductor chips; attaching a semiconductor chip on an upper surface of a substrate; attaching bonding wires that electrically connect the pads of the semiconductor chip to the substrate; and encapsulating the semiconductor chip and the bonding wire. At the edge of the substrate, the bonding wire contacts the insulation layer, thereby preventing electrical shorts between the bonding wire and the silicon substrate. In this embodiment, after removing portions of the polyimide layer, the method may further include forming a groove in the scribe area. The groove is wider than the width of lines cut in the wafer to separate the wafer into individual semiconductor chips. Cutting the wafer and forming the insulation groove can be accomplished using a diamond cutter with a grit size of 4 through 6 μm while cutting along the scribe area at a rate of 80 mm of depth per second and a speed of rotation between 35,000 and 40,000 rpm. Formation of the groove is before backside grinding of the wafer. After forming the insulation layer in the groove, the backside grinding of the wafer exposes the insulation material filled into the groove. The insulation layer is typically a plastic resin of an epoxy type and can be formed by potting or printing methods.
- Other advantages and features of the present invention will become more apparent and the invention itself will best be better understood by referring to the following description taken in conjunction with the accompanying drawings.
- FIG. 1 is a cross-sectional view of a conventional ball grid array package.
- FIG. 2 is a cross-sectional view illustrating separation of the semiconductor chips form in a wafer.
- FIG. 3 is a cross-sectional view of a ball grid array package according to an embodiment of the present invention.
- FIG. 4a is a plan view of a wafer.
- FIG. 4b is a cross-sectional view along the
line 4 b-4 b of FIG. 4a before separation of individual semiconductor chips. - FIG. 4c is a cross-sectional view along the
line 4 b-4 b after cutting a wafer along scribe area of the wafer. - FIG. 5 is a cross-sectional view showing a ball grid array package according to another embodiment of the present invention.
- FIG. 6a is a plan view illustrating the formation of insulation along the edge of a semiconductor chip attached to a substrate.
- FIG. 6b is a cross-sectional view along the line of 6 b-6 b of FIG. 6a.
- FIG. 7a is a cross-sectional view of a wafer having a polyimide layer exposing scribe lines and pads.
- FIG. 7b is a cross-sectional view of a wafer that is cut to form a groove in the scribe area.
- FIG. 7c is a cross-sectional view of the wafer of FIG. 7b after filling the groove with an insulating material.
- FIG. 7d is a cross-sectional view of the wafer of FIG. 7c after backside grinding.
- FIG. 7e is a cross-sectional view of the wafer of FIG. 7d after cutting the wafer along scribe lines.
- FIG. 8 is a cross-sectional view of a ball grid array package according to yet another embodiment of the present invention.
- FIG. 9a is a cross-sectional view of a wafer having a polyimide layer that exposes scribe lines and pads.
- FIG. 9b is a cross-sectional view of the wafer of FIG. 9a after formation of a thick insulating region on the scribe area of the wafer.
- FIG. 9c is cross-sectional view of the wafer of FIG. 9b after cutting the wafer along scribe lines.
- FIG. 10 is a cross-sectional view of a ball grid array package according to yet another embodiment of the present invention.
- FIG. 3 is a cross-sectional view showing a
BGA package 200 according to an embodiment of the present invention.BGA package 200 includes asemiconductor chip 110 mounted by anon-conductive adhesive 170 at the center of the upper surface of asubstrate 122. Thesubstrate 122 is an insulating board havingcircuit wiring 124 in and on thesubstrate 122.Circuit wiring 124 includes atop wiring pattern 123 on the upper surface of thesubstrate 122 and abottom wiring pattern 125 on the lower surface of thesubstrate 122. Viaholes 126 penetrate from the upper surface to the lower surface, and conductors (not shown) in the via holes 126 connect the top andbottom wiring patterns semiconductor chip 110 includes a plurality ofbonding pads 112 on an active area of the upper surface thereof. Anitride layer 114, as a non-active layer, is also on the upper surface except for thepads 112. Thenitride layer 114 is a passivation layer that protects the integrated circuits formed in thesemiconductor chip 110 from the external environment. Apolyimide layer 116 on thenitride layer 114 helps prevent electrical shorts and damage ofsemiconductor chip 110 by alpha rays.Bonding wires 150 electrically connect thebonding pads 112 and thetop wiring pattern 123. Inpackage 200, although thebonding wires 150 may contact the upper edge of thesemiconductor chip 110, electrical shorts do not occur because thepolyimide layer 116 covers theupper edge 118 of thesemiconductor chip 110. - FIGS. 4a, 4 b, and 4 c illustrate a method for manufacturing the
semiconductor chip 110, which is inBGA package 200. FIG. 4a is a plan view of asilicon wafer 180 that includes a plurality ofsemiconductor chips 110. Conventional wafer manufacturing processes, which are well-known in the art, can form integrated circuits on the semiconductor chips 110. The wafer includes scribe lines in ascribe area 182 that lacks circuitry and is between neighboring semiconductor chips 110. Since the manufacturing method of the circuit devices in the semiconductor chips 110 is not critical to this invention, a detailed description of the integrated circuit manufacturing process is omitted. - As shown in FIG. 4b, a
bonding pad 112, which electrically connects to the integrated circuits in asilicon substrate 190, is on an active area of thesilicon substrate 190. Anitride layer 114, as a non-active passivation layer, covers the active surface of thesilicon substrate 190 and the edges of thebonding pad 112 to protect the integrated circuits. Apolyimide layer 116 is on thenitride layer 114 and thebonding pad 112 and protects the integrated circuits from damage that electric shorts or alpha rays might otherwise cause. In an exemplary embodiment, thebonding pad 112 is aluminum and resides in the central portion of the active surface of asemiconductor chip 110. - As shown in FIG. 4c, a process for removing the
polyimide layer 116 from thepad 112, i.e., a photolithography process leaves the polyimide in thescribe areas 182. Thewafer 180 is cut along the scribe lines in thescribe area 182, thereby separating thewafer 180 intoindividual semiconductor chips 110. That is, in this embodiment, the cutting process cuts thewafer 180 while thepolyimide layer 116 remains on thescribe area 182. Previous manufacturing processes removed the polyimide to avoid the chipping that the polyimide layer causes during the cutting process. The cutting process in accordance with this embodiment of the invention reduces or avoids the chipping through use of a diamond cutter with a smaller grit size and a slower forwarding speed than those conventionally used. In particular, a diamond cutter with grit size of 2 through 4 μm or 0.3 through 3 μm and a rotational speed between 35,000 and 40,000 rpm cuts thewafer 180 at the rate of 20 mm of depth per second. - The above embodiment of the invention uses the
polyimide layer 116 to prevent electrical shorts between thesubstrate 190 and thebonding wire 150. Other embodiments of the invention, described below, use a plastic resin of an epoxy type at the edge of the active area of the semiconductor chip to prevent shorting. - FIG. 5 is a cross-sectional view showing a
BGA package 300 according to another embodiment of the present invention.BGA package 300 includes asemiconductor chip 210 attached to an upper surface of asubstrate 220 by anon-conductive adhesive 270.Bonding wires 250 electrically connectbonding pads 212 of thesemiconductor chip 210 to atop wiring pattern 223 of thesubstrate 220. A mold resin encapsulates an upper surface of thesubstrate 220 including thesemiconductor chip 210 and thebonding wires 250. A plurality ofsolder balls 240 is on abottom wiring pattern 225 of the lower surface of thesubstrate 220 and electrically connects with thesemiconductor chip 210. - In the
BGA package 300, aninsulation layer 215 resides on theedge 218 of thesemiconductor chip 210. That is, the insulation layer resides at the edge of the active area of thesemiconductor chip 210 and on the remaining scribe area of thesemiconductor chip 210, where the polyimide layer is absent. Further, theinsulation layer 215 is not only on the top surface of thesemiconductor chip 210 but also on the side surface of thesemiconductor chip 210. Accordingly,bonding wires 250 contact theinsulation layer 215 at theedge 218 of thesemiconductor chip 210, and theinsulation layer 215 prevents electrical shorts betweensubstrate 290 and thebonding wire 250. Here, a potting or print method can form theinsulation layer 215. - A potting method for forming an insulation layer on the edge of the active surface of the semiconductor chip is explained with reference to FIGS. 6a and 6 b. After attaching the
semiconductor chip 210 to the top surface of thesubstrate 220 with anon-conductive adhesive 270, asyringe 260 applies an insulatingmaterial 215 a to cover theedge 218 of the active area of thesemiconductor chip 210. Curing of the insulatingmaterial 215 a then forms the insulation layer 215 (FIG. 5). A plastic resin of an epoxy type is preferable as the insulatingmaterial 215 a. A conventional wafer fabrication process fabricates thesemiconductor chip 210. In particular, the fabrication process removes the polyimide layer from the edge of the active area, thereby exposing a nitride layer. The insulatingmaterial 215 a covers on the exposed portion of the nitride layer and extends onto the side of thesemiconductor chip 210. - After the potting method forms the
insulation layer 215 as described above, conventional package manufacturing processes complete theBGA package 300. In particular, wire bonding attachesbonding wires 250, molding encapsulates thesemiconductor chip 210 and thebonding wires 250, and a solder ball forming processes forms the external terminals ofBGA package 300. FIG. 5 shows thecomplete BGA package 300 using thesemiconductor chip 210 having theinsulation layer 215 formed by the potting method. - FIGS. 7a through 7 e illustrate a printing method for forming an insulation layer on the edge of the active area of the semiconductor chip. As shown in FIG. 7a, a
wafer 280 has part of apolyimide layer 216 removed to expose a portion of anitride layer 214 and thebonding pad 212. Thewafer 280 is in a state before backside grinding and has a thickness of about 640 μm for an 8-inch wafer and about 825 μm for a 12-inch wafer. - FIG. 7b shows the wafer after the formation of a
groove 284 inscribe area 282. Cutting the wafer along its scribe lines to a predetermined depth forms thegroove 284. Thegroove 284 is wider than the width that is required for cutting the wafer when separating the wafer into theindividual semiconductor chips 210. - Since the
semiconductor chip 210 typically has a thickness between about 280 μm and about 450 μm, thegroove 284 preferably has a depth between about 320 μm and about 500 μm. Generally, the depth of thegroove 284 depends on the desired thickness of thesemiconductor chip 210. The width of theinsulation groove 284 typically depends on the width of thescribe area 282 and the width required for separating the chips. When the width of thescribe area 282 is about 120 μm and the width of the cut separating the chips is between 45 μm and 50 μm, the width of thegroove 284 is about 60 μm. - Next, as shown in FIG. 7c, printing deposits an insulating
material 215 b on thepolyimide layer 216, thenitride layer 214, and in thegroove 284. A mask (not shown) having an opening that exposes theinsulation groove 284 can define the boundaries of the insulatingmaterial 215 b. The mask is removed, and theinsulation material 215 b is cured. Alternatively, instead of the printing method, potting can fill theinsulation groove 284 with or without a mask to control the boundaries of the insulatingmaterial 215 b. - FIG. 7d shows the wafer after grinding of a backside of the wafer to expose the
insulation material 215 b at the bottom of thegroove 284. In FIG. 7c, a plane ‘A’ denotes a destination of the backside grinding of thewafer 280. As mentioned above, after grinding the wafer, the thickness of the semiconductor wafer is between about 280 μm and about 450 μm. - FIG. 7e shows the
wafer 280 after cutting inscribe area 282 separates thewafer 280 intoindividual semiconductor chips 210. Since the width required for cutting the wafer is less than the width of the groove, a part of theinsulation material 215 b from the groove remains after cutting the wafer. Accordingly, theinsulation layer 215 remains on the top and side surfaces of the semiconductor chip. The conditions or parameters for cutting thewafer 280 in FIG. 7b and FIG. 7e are the same as those used in conventional wafer cutting processes. For example, a diamond cutter can have a grit size of 4 μm through 6 μm, and the cutting rate is about 80 mm of depth per second at the speed of rotation between 35,000 and 40,000 rpm. - After obtaining the
individual semiconductor chips 210 having theinsulation layer 215, conventional processes such as semiconductor chip attaching, wire bonding, molding, and solder ball forming complete the semiconductor package. - FIG. 8 is a cross-sectional view showing a
BGA package 400 according to yet another embodiment of the invention. TheBGA package 400 includes asemiconductor chip 310 having aninsulation layer 315 on the edge of its active area. The remaining structure of theBGA package 400 is the same as described above. Here, a potting or printing method forms theinsulation layer 315. Abonding wire 350, which connects apad 312 of thesemiconductor chip 310 to atop wiring pattern 323 of asubstrate 320, contacts theinsulation layer 315 formed on theedge 318 of thesemiconductor chip 310. The insulatinglayer 315 thereby prevents electrical shorts between thebonding wire 350 and thesilicon substrate 390. - The
semiconductor chip 310 in theBGA package 400 will be explained with reference to FIGS. 9a through 9 c. FIG. 9a shows awafer 380 having a polyimide layer removed from above thepad 312 and ascribe area 382. FIG. 9a shows thewafer 380 after completion of backside grinding, and the thickness of thewafer 380 is between about 280 μm and about 450 μm depending on the desired thickness of thesemiconductor chip 310. Alternatively, a wafer in which the backside grinding process is not completed may be used. - FIG. 9b shows the
wafer 280 after formation an insulatingmaterial 315 a on thescribe area 382. A printing method can deposit the insulatingmaterial 315 a, and theinsulation material 315 a is subsequently cured. Alternatively, a potting method can place the insulatingmaterial 315 a on thescribe area 282 of thewafer 280. - FIG. 9c shows the
wafer 380 after cutting along the scribe lines in thescribe area 382 separates theindividual semiconductor chips 310. Since the width required for cutting the wafer is smaller than that of thescribe area 382, a part of theinsulation material 315 a remains, thereby forming theinsulation layer 315 on the edge of thesemiconductor chip 310. Conventional wafer cutting techniques as described above can cut the insulatingmaterial 315 a and thewafer 380 to separate the semiconductor chips 310. After obtaining asemiconductor chip 310, the conventional manufacturing processes described above can complete the package. - FIG. 10 is a cross-sectional view of a
BGA package 500 according to still another embodiment of the present invention. TheBGA package 500 includes aninsulation layer 415 on theedge 418 of thesemiconductor chip 410. The manufacturing method of thesemiconductor chip 410 forBGA 500 is the same as that of the semiconductor chip illustrated in FIGS. 7a and 7 e, except that a groove in the scribe area for thesemiconductor chip 410 is shallower than that of thegroove 284 in FIG. 7b. For example, the groove cut in the scribe area for thesemiconductor chip 410 is preferably about 60 μm wide and between about 70 μm and about 150 μm deep. - Although, in FIG. 7a, a wafer before a backside grinding process is used, a wafer before or after the backside grinding process may be used for fabrication of the
semiconductor chip 410. When using the wafer after the backside grinding process, a wafer cutting process is soon after forming the insulating material in the groove. - Although, in preferred embodiments of the present invention, a semiconductor chip is applied to a BGA package using a semiconductor chip of a center pad type, the semiconductor chip according to the present invention may also be applied to a lead frame having a die pad.
- When stacking semiconductor chips and using bonding wire between the semiconductor chip and external terminals, a semiconductor chip of the edge-pad type is mainly used as the lower portion, whereas a semiconductor of an edge pad type or a center pad type is used for an upper portion. In accordance with the principals of the invention, processes for forming an insulation material or a polyimide layer on the edge of a semiconductor chip are also suitable for an edge pad type semiconductor chip. In particular, an insulating region on the lower semiconductor chip in a stack prevents the bonding wire of the upper semiconductor chip from contacting the edge of the lower semiconductor chip, and thereby the insulating material prevents electrical shorts.
- Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.
Claims (8)
1. A semiconductor package comprising:
a semiconductor chip including a silicon substrate having an active area, a plurality of pads in a center portion of the active area, and a polyimide layer overlying the active area and extending to an edge of the semiconductor chip;
a substrate on which the semiconductor chip is attached; and
a bonding wire electrically connecting one of the pads of the semiconductor chip to the substrate, wherein the bonding wire contacts the polyimide layer at the edge of the semiconductor chip, whereby the polyimide layer prevents an electrical short between the bonding wire and the silicon substrate.
2. The semiconductor package of claim 1 , further comprising:
a resin encapsulation portion for encapsulating the semiconductor chip and the bonding wire at an upper surface of the substrate; and
a plurality of external terminals formed on a lower surface of the substrate and electrically connected with the semiconductor chip.
3. A semiconductor package comprising:
a semiconductor chip including a silicon substrate having an active area, a plurality of pads in a center portion of the active area, and an insulation layer formed along an edge of the silicon substrate;
a substrate on which the semiconductor chip is attached; and
a bonding wire electrically connecting one of the pads of the semiconductor chip to the substrate, wherein the bonding wire contacts the insulation layer at the edge of the semiconductor chip, whereby the insulation layer prevents an electrical short between the bonding wire and the silicon substrate.
4. The semiconductor package according to claim 3 , wherein the semiconductor chip further comprises:
a non-active layer formed on the active area except for the pads; and
a polyimide layer formed on the non-active except for the pads and the edge of semiconductor chip.
5. The semiconductor package according to claim 4 , wherein the insulation layer is formed on the edge of the active surface of the semiconductor chip, where the polyimide layer is absent.
6. The semiconductor package according to claim 5 , wherein the insulation layer extends past the edge of the semiconductor chip and onto a portion of a side surface of the semiconductor chip.
7. The semiconductor package according to claim 3 , wherein the insulation layer is a plastic resin of an epoxy type.
8. The semiconductor package of claim 3 , further comprising:
a resin encapsulation portion for encapsulating the semiconductor chip and the bonding wire at an upper surface of the substrate; and
a plurality of external terminals formed on a lower surface of the substrate and electrically connected with the semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/035,634 US20020056924A1 (en) | 1999-07-06 | 2001-10-26 | Semiconductor package having an insulating region on an edge of a chip to prevent shorts |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990027041A KR100297451B1 (en) | 1999-07-06 | 1999-07-06 | Semiconductor package and method for manufacturing thereof |
KR99-27041 | 1999-07-06 | ||
US09/483,252 US6348363B1 (en) | 1999-07-06 | 2000-01-14 | Method for manufacturing a semiconductor package |
US10/035,634 US20020056924A1 (en) | 1999-07-06 | 2001-10-26 | Semiconductor package having an insulating region on an edge of a chip to prevent shorts |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/483,252 Division US6348363B1 (en) | 1999-07-06 | 2000-01-14 | Method for manufacturing a semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020056924A1 true US20020056924A1 (en) | 2002-05-16 |
Family
ID=19599614
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/483,252 Expired - Lifetime US6348363B1 (en) | 1999-07-06 | 2000-01-14 | Method for manufacturing a semiconductor package |
US10/035,634 Abandoned US20020056924A1 (en) | 1999-07-06 | 2001-10-26 | Semiconductor package having an insulating region on an edge of a chip to prevent shorts |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/483,252 Expired - Lifetime US6348363B1 (en) | 1999-07-06 | 2000-01-14 | Method for manufacturing a semiconductor package |
Country Status (3)
Country | Link |
---|---|
US (2) | US6348363B1 (en) |
JP (1) | JP3676646B2 (en) |
KR (1) | KR100297451B1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
KR20010008946A (en) | 2001-02-05 |
US6348363B1 (en) | 2002-02-19 |
JP3676646B2 (en) | 2005-07-27 |
JP2001024024A (en) | 2001-01-26 |
KR100297451B1 (en) | 2001-11-01 |
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