US20020048866A1 - Thin film transistor display and method of fabrication - Google Patents
Thin film transistor display and method of fabrication Download PDFInfo
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- US20020048866A1 US20020048866A1 US09/828,857 US82885701A US2002048866A1 US 20020048866 A1 US20020048866 A1 US 20020048866A1 US 82885701 A US82885701 A US 82885701A US 2002048866 A1 US2002048866 A1 US 2002048866A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Definitions
- the present invention relates to a thin film transistor display and a method of fabricating the same.
- a thin film transistor display such as a thin film transistor liquid crystal display (TFT-LCD)
- TFT-LCD thin film transistor liquid crystal display
- the advantages of the TFT-LCD include the portability, low power consumption, and low radiation. Therefore, the TFT-LCD is widely used in various portable products, such as notebooks, personal data assistants (PDA), etc.
- PDA personal data assistants
- the TFT-LCD replaces the CRT monitor in desktop computers gradually.
- FIG. 1A to FIG. 1H of schematic diagrams of a prior art method for fabricating a transistor of a TFT-LCD 10 .
- the transistor of the TFT-LCD 10 is formed on the surface of a glass substrate 12 .
- an aluminum (Al) layer 14 and a cap layer 16 are first deposited on the substrate 12 , respectively.
- the Al layer 14 and the cap layer 16 are patterned by a first photo-etching process (PEP) to form a gate electrode.
- PEP photo-etching process
- an insulating layer 18 , an amorphous silicon layer 20 , and a doped amorphous silicon layer 22 are deposited on the glass substrate 12 .
- a second photo-etching process is used to remove the portion of the doped amorphous silicon layer 22 and the amorphous silicon layer 20 outside the transistor area 24 .
- the insulating layer 18 is then exposed outside the transistor area 24 .
- a metal layer 26 is deposited on the glass substrate 12 .
- a third PEP is performed to pattern the metal layer 26 .
- the doped amorphous silicon layer 22 is etched by using the metal layer 26 as a hard mask, the remaining doped amorphous silicon layer 22 and the metal layer 26 are used to form a source metal layer 28 and a drain metal layer 30 , respectively.
- a passivation layer 32 is deposited on the glass substrate 12 .
- a fourth PEP process is performed to define the pattern of the passivation layer 32 and form a drain opening 34 above the drain metal layer 30 .
- an indium tin oxide (ITO) layer 36 is deposited on the glass substrate 12 and fills in the drain opening 34 .
- a fifth PEP is performed to form the pattern of the ITO layer 36 so that the drain metal layer 30 is electrically connected to a display region (not shown). The transistors are used to control the brightness of the TFT-LCD 10 .
- the prior art method of fabricating the TFT-LCD 10 requires at least five photo-etching processes to form a transistor.
- the method is complicated, expensive, and time-consuming, resulting in a low yield of the TFT-LCD.
- each TFT-LCD includes many other electronic components, and these components will be affected when the yield of the TFT-LCD is low.
- the fabrication of the related electronic components must be integrated into a single process for cost-saving and make the TFT-LCD can compete with the low-cost CRT monitors.
- the present invention provides a method for fabricating a thin film transistor display.
- the thin film transistor display is fabricated on a substrate having a first region and a second region.
- the first region comprises a transistor area for the formation of a transistor
- the second region comprises a pad area for the formation of a pad.
- a first metal layer is deposited on the substrate and then patterned to form a gate electrode in the transistor area and a pad electrode in the pad area.
- a first insulating layer is formed and patterned.
- the first insulating layer includes a pad opening formed in the pad area to expose the pad electrode.
- a second insulating layer, a semiconductor layer, a doped silicon conductive layer, and a second metal layer are deposited on the first insulating layer.
- a channel area is defined in the transistor area, and then, removing portions of the second metal layer and the doped silicon layer positioned (1) outside the transistor area and (2) within the channel area.
- the remaining second metal layer forms a source metal layer and a drain metal layer at the transistor area.
- the source and drain metal layers are separated by the channel area, and the semiconductor layer is exposed outside the transistor area.
- a passivation layer is deposited and patterned on the substrate. The portion of the passivation layer outside the first region is removed to expose the semiconductor layer outside the first region.
- the passivation layer as an etching mask, the semiconductor layer and the second insulating layer unprotected by the passivation layer is removed.
- the first insulating layer is therefore exposed outside the first region, and the pad electrode is exposed in the pad opening.
- FIG. 1A to FIG. 1H are schematic diagrams of a prior art method for fabricating transistors of a TFT-LCD.
- FIG. 2A to FIG. 2G are schematic diagrams of a first embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 3A to FIG. 3B are schematic diagrams of a second embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 4A to FIG. 4I are schematic diagrams of a third embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 5 is a schematic diagram of a fourth embodiment of the present invention method for fabricating a TFT-LCD.
- the present invention is a thin film transistor liquid crystal display (TFT-LCD) 50 .
- the TFT-LCD 50 is formed on the surface of the substrate 52 .
- the substrate 52 comprises at least a first region 51 , a second region 53 , and a third region 55 .
- the first region 51 comprises a transistor area 54 for the formation of a transistor 60
- the third region 55 comprises a capacitor area 56 for the formation of a capacitor 62
- the second region 53 comprises a pad area 58 for the formation of a pad 64 .
- a metal layer 66 is first deposited on the surface of the substrate 52 . As shown in FIG. 2A, the pattern of the metal layer 66 is then defined to form a gate electrode 66 a in the transistor area 54 , a capacitor bottom electrode 66 b in the capacitor area 56 , and a pad electrode 66 c in the pad area 58 .
- an insulating layer 68 As shown in FIG. 2B, an insulating layer 68 , a semiconductor layer 70 , a doped silicon layer 72 , and a metal layer 74 are deposited, respectively, on the substrate 52 .
- the semiconductor layer 70 can be made of a polysilicon layer or an amorphous silicon layer, depending on the process condition or the size of the display area.
- the insulating layer 68 , the semiconductor layer 70 , the doped silicon conductive layer 72 , and the metal layer 74 are then patterned.
- a channel area 75 is first defined in the transistor area 54 , then removing portions of both the doped silicon layer 72 and the metal layer 74 positioned (1) outside the transistor area 54 and inside the channel area 75 of the first region 51 , (2) inside the second region 53 , and (3) in the third region 55 which is not covered by the capacitor bottom electrode 66 b. Therefore, the remaining metal layer 74 forms a source metal layer 74 a and a drain metal layer 74 b in the transistor area 54 , and forms a capacitor top electrode 74 c in the capacitor area 56 .
- the source metal layer 74 a and the drain metal layer 74 b are separated by the channel area 75 , and the semiconductor layer 70 is exposed in the regions outside the transistor area 54 and outside the capacitor area 56 .
- a passivation layer 76 is deposited on the semiconductor layer 70 and the metal layer 74 .
- the passivation layer 76 covers the transistor layer 54 , the capacitor layer 56 , the pad area 58 , and also fills in the channel area 75 .
- the passivation layer 76 is then patterned. As shown in FIG. 2E, a source opening 78 a is defined above the source metal layer 74 a , a drain opening 78 b is defined above the drain metal layer 74 b , a capacitor opening 78 c is defined in the capacitor area 56 , and a pad opening 80 is defined in the pad area 58 . Further, the following portions of the passivation layer 76 are removed: (1) outside the first region 51 , the second region 53 , and the third region 55 , and (2) within the source opening 78 a , the drain opening 78 b , the capacitor opening 78 c , and the pad opening 80 .
- the semiconductor layer 70 is therefore exposed outside the first region layer 51 , the second region layer 53 , and the third region layer 55 and inside the pad opening 80 . Also, the source metal layer 74 a , the drain metal layer 74 b , and the capacitor top electrode 74 c are also exposed in the source opening 78 a , the drain opening 78 b , and the capacitor opening 78 c , respectively
- the passivation layer 76 then functions as an etching mask to remove the portions of the semiconductor layer 70 and the insulating layer 68 unprotected by the passivation layer 76 . Therefore, the following portions of the semiconductor layer 70 and the insulating layer 68 will be removed: (1) outside the first region 51 , the second region 53 , and the third region 55 , and (2) within the pad opening 80 . Thus, (1) the glass substrate 52 is exposed outside the first region 51 , the second region 53 , and the third region 55 , and (2) the pad electrode 66 c is exposed within the pad opening 80 . Then, a transistor 60 and a capacitor 62 are manufactured completely.
- a transparent conductive layer 82 is deposited on the substrate 52 .
- the transparent conductive layer 82 usually made of indium tin oxide (ITO), fills into the source opening 78 a , the drain opening 78 b , the capacitor opening 78 c , and the pad opening 80 for electrically connecting to the source metal layer 74 a , the drain metal layer 74 b , the capacitor top electrode 74 c , and the pad electrode 66 c , respectively.
- ITO indium tin oxide
- the transparent conductive layer 82 is patterned and divided into three electrically isolated parts including: a source block 82 a , a drain block 82 b , and a pad block 82 c.
- the source block 82 a is electrically connected to the source metal layer 74 a via the source opening 78 a .
- the drain block 82 b is electrically connected to the drain metal layer 74 b via the drain opening 78 b and to the capacitor top electrode 74 c via the capacitor opening 78 c .
- the pad block 82 c is electrically connected to the pad electrode 66 c via the pad opening 80 .
- the transparent conductive layer 82 is electrically connected to the transistor 60 and capacitor 62 .
- the fabrication of the TFT-LCD 50 therefore requires only four photo-etching processes.
- the structure of the TFT-LCD 50 includes the substrate 52 , the thin film transistor 60 , the capacitor 62 , and the pad 64 used as a gate bonding pad.
- the thin film transistor 60 includes a gate electrode 66 a formed on the substrate 52 , a transistor insulating layer 68 a and a transistor semiconductor layer 70 a formed on the gate electrode 66 a .
- a first doped silicon layer 72 a and a second doped silicon layer 72 b are further formed on the transistor semiconductor layer 70 a , and separated by a channel area 75 .
- a source conductive layer 74 a is formed on the first doped silicon layer 72 a while a drain conductive layer 74 b is formed on the second doped silicon layer 72 b .
- a transistor passivation layer 76 a covers the channel area 75 , the source metal layer 74 a , and the drain metal layer 74 b.
- the sidewall of the transistor insulating layer 68 a is aligned with the sidewall of the transistor semiconductor layer 70 a .
- the sidewall of the source metal layer 74 a is aligned with the sidewall of the first doped silicon layer 72 a while the sidewall of the drain metal layer 74 b is aligned with the sidewalls of the second doped silicon layer 72 b .
- the sidewall of the source metal layer 74 a and the drain metal layer 74 b are spaced apart from the sidewall of the insulating layer 70 a.
- the capacitor 62 comprises a capacitor bottom electrode 66 b in common with the gate electrode 66 a and covered by a capacitor insulating layer 68 b .
- a capacitor semiconductor layer 70 b , a capacitor doped silicon layer 72 c , a capacitor top electrode 74 c , and a capacitor passivation layer 76 b are formed on the capacitor insulating layer 68 b .
- a transparent conductive layer 82 b further covers the capacitor passivation layer 76 b .
- the capacitor passivation layer 76 b has a capacitor opening 78 c , and the capacitor top electrode 74 c is exposed in the capacitor opening 78 c .
- the transparent conductive layer 82 b can then fill in the capacitor opening 78 c and is electrically connected to the capacitor top electrode 74 c.
- the gate pad includes a pad electrode 66 c formed on the substrate 52 and electrically connected to the gate electrode 66 a .
- a pad insulating layer 68 c , a pad semiconductor layer 70 c , and a pad passivation layer 76 c surround the boundary of the pad electrode 66 c to form a pad opening 80 .
- the pad opening 80 penetrates the pad passivation layer 76 c , the pad semiconductor layer 70 c , and the pad insulating layer 68 c , so that the pad electrode 66 c is exposed in the pad opening 80 .
- a transparent conductive layer 82 c fills in the pad opening 80 to electrically connect with the pad electrode 66 c.
- the transistor passivation layer 76 a has a source opening 78 a above the source metal layer 74 a , and a drain opening 78 b above the drain metal layer 78 b .
- the TFT-LCD 50 further comprises a transparent source conductive layer block 82 a , a transparent drain conductive layer block 82 b , and a transparent pad conductive layer block 82 c .
- the transparent source conductive layer block 82 a connects to the source conductive layer 74 a via the source opening 78 a
- the transparent drain conductive layer block 82 b connects to the drain conductive layer 74 b via the drain opening 78 b
- the transparent pad conductive layer block 82 c connects to the pad electrode 66 c via the pad opening 80 .
- FIG. 3A and FIG. 3B are the schematic diagrams of the second embodiment in the present invention.
- the second embodiment can be applied to an in-plain-switch (IPS) type TFT-LCD.
- IPS in-plain-switch
- the second embodiment requires only three photo-etching processes (PEPs), and the first two steps are the same as these in the first embodiment.
- PEPs photo-etching processes
- the steps shown in FIG. 2A to FIG. 2D will be performed before the process shown in FIG. 3A.
- the final step of the second embodiment is to remove portions of the passivation layer 76 , the semiconductor layer 70 , and the insulating layer 68 positioned (1) outside the first region 51 , the second region 53 , and the third region 55 , and (2) within the pad area 58 to form a pad opening 80 .
- the above-mentioned liquid crystal display also includes a gate line and a signal line intercrossed with the gate line (both are not shown).
- the gate line is connected to the gate electrode 66 a and the pad electrode 66 c .
- a signal bonding pad is position at the end of the signal line, which cross-sectional figure is shown as FIG. 3B.
- an insulating layer 68 d , a semiconductor layer 70 d , and a doped silicon layer 72 d are formed, respectively, on the substrate 52 .
- a second metal layer 74 d is formed in a predetermined area of the doped silicon layer 72 d , and a passivation layer 76 d covers both the second metal layer 74 d and the doped silicon layer 72 d . Further, an opening 82 is formed above the second metal layer 74 d , and the second metal layer 74 d is exposed and can be electrical connected with the outer circuit (not shown).
- the structure of the second embodiment is similar to the first embodiment in the present invention.
- the major difference between the two embodiments includes: (1) there is no transparent conductive layer in the second embodiment, and (2) the passivation layer 76 does not have openings at the position above the source metal layer 74 a , drain metal layer 74 b , or the capacitor top electrode 74 c.
- FIG. 4A to FIG. 4I are the schematic diagrams of the third embodiment according to the present invention.
- three different kinds of capacitors can be fabricated in three regions 55 a , 55 b , and 55 c .
- a metal layer 66 is first deposited on the substrate 52 , and patterned by a first photo-etching process (PEP-III-1) to form a gate electrode 66 a , a capacitor bottom electrode 66 b , and a pad electrode 66 c.
- PEP-III-1 first photo-etching process
- an first insulating layer 681 is deposited on the substrate 52 .
- the insulating layer 681 is then patterned by a second photo-etching process (PEP-III-2) .
- PEP-III-2 a second photo-etching process
- FIG. 4C a capacitor insulating layer opening 84 a is formed in capacitor area 56 c to expose the capacitor bottom electrode 66 b
- a pad opening 84 b is formed in pad area 58 to expose the pad electrode 66 c.
- an second insulating layer 682 , a semiconductor layer 70 , a doped silicon layer 72 , and a second metal layer 74 are sequentially formed on the substrate 52 .
- the second insulating layer 682 fills both the capacitor insulating layer opening 84 a and the pad opening 84 b .
- the total thickness of the first insulating layer 681 and the second insulating layer 682 of this embodiment is equal to the thickness of the insulating layer 68 of the first embodiment so that the structure of the transistor 60 remains unchanged.
- the pattern of the insulating layer 682 , the semiconductor layer 70 , the doped silicon layer 72 , and the metal layer 74 are then defined by a third photo-etching process (PEP-III-3).
- PEP-III-3 a third photo-etching process
- a channel area 75 is defined in the transistor area 54 , and then removing both the second metal layer 74 and the doped silicon layer 72 positioned (a) within the channel area 75 , and (b) outside the transistor area 54 , and capacitor areas 56 b and 56 c .
- the remaining metal layer 74 therefore forms a source metal layer 74 a and a drain metal layer 74 b in the transistor area 54 , and also forms capacitor top electrodes 74 c in the capacitor areas 56 b and 56 c .
- the source metal and the drain metal layer is separated by the channel area 75 .
- the semiconductor layer 70 is exposed outside the transistor area 54 , the capacitor area 56 b , and the capacitor area 56 c.
- a passivation layer 76 is deposited to cover the first region 51 , the second region 53 , the third regions 55 b , 55 c , the transistor area 54 , the capacitor areas 56 a , 56 b and 56 c , and the pad area 58 , as well as filled into the channel area 75 .
- the passivation layer 76 is then patterned by a fourth photo-etching process(PEP-III-4). Portions of the passivation layer 76 outside the first region 51 and the third regions 55 b and 55 c are removed to expose the semiconductor layer 70 in the second region 53 and the third region 55 a .
- a source opening 78 a is defined above the source metal layer 74 a
- a drain opening 78 b is defined above the drain metal layer 74 b
- capacitor openings 78 c are defined in the capacitor areas 56 b and 56 c .
- portions of the passivation layer 76 are then removed within the source opening 78 a , the drain opening 78 b , and the capacitor opening 78 c . Therefore, the source metal layer 74 a is exposed in the source opening 78 a of the transistor area 54 , the drain metal layer 74 b is exposed in the drain opening 78 b , the insulating layer is exposed in the capacitor area 66 b , and the capacitor top electrodes 74 c are exposed in the capacitor openings 78 c.
- the passivation layer 76 is then used as an etching mask to remove the unprotected portions of the semiconductor layer 70 and the insulating layer 682 . Therefore, the insulating layer 681 is exposed outside the first region 51 , and the third regions 55 b and 55 c . In other words, the insulating layer 681 is exposed in the second region 53 and the third region 55 a . Further, the pad electrode 66 c is exposed in the pad opening 84 b , and the fabrication of the transistor 60 and the capacitor 62 b is thus completed.
- the pad opening 84 b shown in FIG. 4C can be formed by the second PEP (PEP-III-2) or after the fourth PEP(PEP-III-4), in other words, the second PEP(PEP-III-2) can be performed after the fourth PEP(PEP-III-4).
- a transparent conductive layer 82 is formed on the substrate 52 to cover the capacitor areas 56 a , 56 b and 56 c , as well as fill in the source opening 78 a , the drain opening 78 b , the capacitor opening 78 c , and the pad opening 84 b.
- the transparent conductive layer 82 is patterned by a fifth photo-etching process (PEP-III-5). Therefore, the transparent conductive layer 82 is separated into at least three electrical-isolated parts including the source block 82 a , the drain block 82 b , and the pad block 82 c .
- the source block 82 a is electrically connected to the source metal layer 74 a via the source opening 78 a
- the drain block 82 b is electrically connected to the drain metal layer 74 b via the drain opening 78 b
- the pad block 82 c is electrically connected to the pad electrode 66 c via the pad opening 84 b
- the transparent conductive layer 82 is electrically connected to the capacitor top electrode 74 c .
- the transparent conductive layer 82 is electrically connected to the transistor 60 and each capacitor after the fabrication of the capacitor 62 a and the pad 64 is completed.
- the gate pad of the third embodiment includes a pad electrode 66 c , a pad insulating layer 681 , and a pad block 82 c of the transparent conductive layer.
- the pad electrode 66 c is formed on the substrate 52 and electrically connected to the gate electrode 66 a
- the pad insulating layer 681 surrounds the boundary of the pad electrode 66 c to form a pad opening 84 b
- the pad opening 84 b is penetrated through the pad insulating layer 681 to expose the pad electrode 66 c .
- the pad block 82 c is electrically connected to the pad electrode 66 c via the pad opening 84 b.
- the capacitor 62 a includes a capacitor bottom electrode 66 b common with the gate electrode 66 a , a insulating layer 681 covering the capacitor bottom electrode 66 b , and the transparent conductive layer 82 b covering the insulating layer 681 and functions as a capacitor top electrode.
- the capacitor 62 b includes the capacitor bottom electrode 66 b common with the gate electrode 66 a , the insulating layer 681 covering the capacitor bottom electrode 66 b , and the insulating layer 682 as well as the semiconductor layer 70 covering the insulating layer 681 . Further, the doped silicon layer 72 , the capacitor top electrode 74 c , and the capacitor passivation layer 76 c are formed on the semiconductor layer 70 . The capacitor passivation layer 76 c is covered by a transparent conductive layer 82 d . In addition, the capacitor passivation layer 76 c includes a capacitor opening 78 c to expose the capacitor top electrode 74 c . The transparent conductive layer 82 d fills in the capacitor opening 78 c and electrically connects to the capacitor top electrode 74 c.
- the capacitor 62 c is also similar to the capacitor 62 b .
- the major difference between these capacitors 62 c and 62 b is that the capacitor 62 c has the insulating opening 84 a in the insulating layer 681 to expose the capacitor bottom electrode 66 b , and the insulating layer 682 will fill into the insulating opening 84 a . Therefore, the distance between the capacitor top electrode 74 c and the capacitor bottom electrode 66 b is smaller for resulting an increased capacitor value in the capacitor 62 c.
- FIG. 5 is the schematic diagram according to the fourth embodiment.
- This embodiment can be applied to an in-plain-switch (IPS) type TFT-LCD.
- the fourth embodiment of the present invention combines features of the second and third embodiments to form various different kinds of capacitors without using the transparent conductive layer because the IPS type TFT-LCD doesn't require the transparent conductive layer.
- the first three steps of the fourth embodiment are the same as those of the third embodiment, a half-finished product as shown in FIG. 4F is manufactured.
- portions of the passivation layer 76 , the semiconductor layer 70 , and the insulating layer 682 positioned (1) outside the first region 51 , and (2) outside the third regions 55 b and 55 c are removed in the fourth photo-etching process of the fourth embodiment.
- the fabrication of the transistor 60 , the capacitors 62 b , 62 c , and the pad 64 are then completed. There is no transparent conductive layer, therefore, the above method can be used in the fabrication of the IPS type TFT-LCD.
- a metal wire 62 a is formed in the third region 55 a.
- the major difference between the fourth embodiment and the third embodiment includes (1) the passivation layer 76 of the fourth embodiment lacks the openings above the source conductive layer 74 a , the drain conductive layer 74 b , and the capacitor top electrode 74 c , and (2) no transparent conductive layer is formed in the fourth embodiment.
- the feature of the present invention is to deposit the metal layer 74 above the doped silicon layer 72 for reducing the resistance of the transistor 60 and the capacitor 62 , and increasing the operation rate.
- the metal layer 74 above the doped silicon layer 72 for reducing the resistance of the transistor 60 and the capacitor 62 , and increasing the operation rate.
- no transparent conductive layer 82 is needed, resulting in a reduction in both the resistance and the cost of the display.
- Another advantage of the present invention is the increased flexibility in circuit design since the same process can be used to manufacture different kinds of capacitors without affecting the structure of the transistor 60 and the pad 64 or changing the area of the capacitor area 66 .
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a thin film transistor display and a method of fabricating the same.
- 2. Description of the Prior Art
- A thin film transistor display, such as a thin film transistor liquid crystal display (TFT-LCD), utilizes a lot of thin film transistors are arranged in a matrix as switches for driving liquid crystal molecules to produce brilliant images after co-operating with other elements such as capacitors and bonding pads. The advantages of the TFT-LCD include the portability, low power consumption, and low radiation. Therefore, the TFT-LCD is widely used in various portable products, such as notebooks, personal data assistants (PDA), etc. Moreover, the TFT-LCD replaces the CRT monitor in desktop computers gradually.
- Please refer to FIG. 1A to FIG. 1H of schematic diagrams of a prior art method for fabricating a transistor of a TFT-
LCD 10. In the prior art, the transistor of the TFT-LCD 10 is formed on the surface of aglass substrate 12. As shown in FIG. 1A, an aluminum (Al)layer 14 and acap layer 16 are first deposited on thesubstrate 12, respectively. Next, theAl layer 14 and thecap layer 16 are patterned by a first photo-etching process (PEP) to form a gate electrode. - Then, as shown in FIG. 1B, an
insulating layer 18, anamorphous silicon layer 20, and a dopedamorphous silicon layer 22 are deposited on theglass substrate 12. As shown in FIG. 1C, a second photo-etching process is used to remove the portion of the dopedamorphous silicon layer 22 and theamorphous silicon layer 20 outside thetransistor area 24. Theinsulating layer 18 is then exposed outside thetransistor area 24. As shown in FIG. 1D, ametal layer 26 is deposited on theglass substrate 12. As shown in FIG. 1E, a third PEP is performed to pattern themetal layer 26. Further, the dopedamorphous silicon layer 22 is etched by using themetal layer 26 as a hard mask, the remaining dopedamorphous silicon layer 22 and themetal layer 26 are used to form asource metal layer 28 and adrain metal layer 30, respectively. - As shown in FIG. 1F, after the third PEP, a
passivation layer 32 is deposited on theglass substrate 12. Then, as shown in FIG. 1G, a fourth PEP process is performed to define the pattern of thepassivation layer 32 and form a drain opening 34 above thedrain metal layer 30. Next, an indium tin oxide (ITO)layer 36 is deposited on theglass substrate 12 and fills in the drain opening 34. Finally, as shown in FIG. 1H, a fifth PEP is performed to form the pattern of theITO layer 36 so that thedrain metal layer 30 is electrically connected to a display region (not shown). The transistors are used to control the brightness of the TFT-LCD 10. - The prior art method of fabricating the TFT-
LCD 10 requires at least five photo-etching processes to form a transistor. The method is complicated, expensive, and time-consuming, resulting in a low yield of the TFT-LCD. Besides, each TFT-LCD includes many other electronic components, and these components will be affected when the yield of the TFT-LCD is low. Thus, the fabrication of the related electronic components must be integrated into a single process for cost-saving and make the TFT-LCD can compete with the low-cost CRT monitors. - It is therefore a primary objective of the present invention to provide a new method of fabricating a thin film transistor display to solve the above-mentioned problem.
- In a preferred embodiment, the present invention provides a method for fabricating a thin film transistor display. The thin film transistor display is fabricated on a substrate having a first region and a second region. The first region comprises a transistor area for the formation of a transistor, and the second region comprises a pad area for the formation of a pad. A first metal layer is deposited on the substrate and then patterned to form a gate electrode in the transistor area and a pad electrode in the pad area. Then, a first insulating layer is formed and patterned. The first insulating layer includes a pad opening formed in the pad area to expose the pad electrode. Further, a second insulating layer, a semiconductor layer, a doped silicon conductive layer, and a second metal layer are deposited on the first insulating layer. A channel area is defined in the transistor area, and then, removing portions of the second metal layer and the doped silicon layer positioned (1) outside the transistor area and (2) within the channel area. The remaining second metal layer forms a source metal layer and a drain metal layer at the transistor area. The source and drain metal layers are separated by the channel area, and the semiconductor layer is exposed outside the transistor area. Further, a passivation layer is deposited and patterned on the substrate. The portion of the passivation layer outside the first region is removed to expose the semiconductor layer outside the first region. Finally, by using the passivation layer as an etching mask, the semiconductor layer and the second insulating layer unprotected by the passivation layer is removed. The first insulating layer is therefore exposed outside the first region, and the pad electrode is exposed in the pad opening.
- It is an advantage of the present invention that a method of fabricating a thin film transistor display can produce different kinds of capacitors as well as reduce the resistance of both transistors and capacitors under the same process condition.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
- FIG. 1A to FIG. 1H are schematic diagrams of a prior art method for fabricating transistors of a TFT-LCD.
- FIG. 2A to FIG. 2G are schematic diagrams of a first embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 3A to FIG. 3B are schematic diagrams of a second embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 4A to FIG. 4I are schematic diagrams of a third embodiment of the present invention method for fabricating a TFT-LCD.
- FIG. 5 is a schematic diagram of a fourth embodiment of the present invention method for fabricating a TFT-LCD.
- Please refer to FIG. 2A to FIG. 2G which are the schematic diagrams of the method for fabricating the thin-film transistor display according to the present invention. In this preferred embodiment, the present invention is a thin film transistor liquid crystal display (TFT-LCD)50. The TFT-
LCD 50 is formed on the surface of thesubstrate 52. Thesubstrate 52 comprises at least afirst region 51, asecond region 53, and athird region 55. Thefirst region 51 comprises atransistor area 54 for the formation of atransistor 60, thethird region 55 comprises acapacitor area 56 for the formation of acapacitor 62, and thesecond region 53 comprises apad area 58 for the formation of apad 64. - According to the present invention, a
metal layer 66 is first deposited on the surface of thesubstrate 52. As shown in FIG. 2A, the pattern of themetal layer 66 is then defined to form agate electrode 66a in thetransistor area 54, acapacitor bottom electrode 66b in thecapacitor area 56, and apad electrode 66c in thepad area 58. - As shown in FIG. 2B, an insulating
layer 68, asemiconductor layer 70, a dopedsilicon layer 72, and ametal layer 74 are deposited, respectively, on thesubstrate 52. Thesemiconductor layer 70 can be made of a polysilicon layer or an amorphous silicon layer, depending on the process condition or the size of the display area. - As shown in FIG. 2C, the insulating
layer 68, thesemiconductor layer 70, the doped siliconconductive layer 72, and themetal layer 74 are then patterned. Achannel area 75 is first defined in thetransistor area 54, then removing portions of both the dopedsilicon layer 72 and themetal layer 74 positioned (1) outside thetransistor area 54 and inside thechannel area 75 of thefirst region 51, (2) inside thesecond region 53, and (3) in thethird region 55 which is not covered by thecapacitor bottom electrode 66 b. Therefore, the remainingmetal layer 74 forms asource metal layer 74 a and adrain metal layer 74 b in thetransistor area 54, and forms acapacitor top electrode 74 c in thecapacitor area 56. Thesource metal layer 74 a and thedrain metal layer 74 b are separated by thechannel area 75, and thesemiconductor layer 70 is exposed in the regions outside thetransistor area 54 and outside thecapacitor area 56. - Secondly, as shown in FIG. 2D, a
passivation layer 76 is deposited on thesemiconductor layer 70 and themetal layer 74. Thepassivation layer 76 covers thetransistor layer 54, thecapacitor layer 56, thepad area 58, and also fills in thechannel area 75. - The
passivation layer 76 is then patterned. As shown in FIG. 2E, a source opening 78 a is defined above thesource metal layer 74 a, adrain opening 78 b is defined above thedrain metal layer 74 b, acapacitor opening 78 c is defined in thecapacitor area 56, and apad opening 80 is defined in thepad area 58. Further, the following portions of thepassivation layer 76 are removed: (1) outside thefirst region 51, thesecond region 53, and thethird region 55, and (2) within the source opening 78 a, thedrain opening 78 b, thecapacitor opening 78 c, and thepad opening 80. Thesemiconductor layer 70 is therefore exposed outside thefirst region layer 51, thesecond region layer 53, and thethird region layer 55 and inside thepad opening 80. Also, thesource metal layer 74 a, thedrain metal layer 74 b, and thecapacitor top electrode 74 c are also exposed in the source opening 78 a, thedrain opening 78 b, and thecapacitor opening 78 c, respectively - The
passivation layer 76 then functions as an etching mask to remove the portions of thesemiconductor layer 70 and the insulatinglayer 68 unprotected by thepassivation layer 76. Therefore, the following portions of thesemiconductor layer 70 and the insulatinglayer 68 will be removed: (1) outside thefirst region 51, thesecond region 53, and thethird region 55, and (2) within thepad opening 80. Thus, (1) theglass substrate 52 is exposed outside thefirst region 51, thesecond region 53, and thethird region 55, and (2) thepad electrode 66 c is exposed within thepad opening 80. Then, atransistor 60 and acapacitor 62 are manufactured completely. - Then, as shown in FIG. 2F, a transparent
conductive layer 82 is deposited on thesubstrate 52. The transparentconductive layer 82, usually made of indium tin oxide (ITO), fills into the source opening 78 a, thedrain opening 78 b, thecapacitor opening 78 c, and thepad opening 80 for electrically connecting to thesource metal layer 74 a, thedrain metal layer 74 b, thecapacitor top electrode 74 c, and thepad electrode 66 c, respectively. - Finally, as shown in FIG. 2G, the transparent
conductive layer 82 is patterned and divided into three electrically isolated parts including: asource block 82 a, a drain block 82 b, and apad block 82 c. Thesource block 82 a is electrically connected to thesource metal layer 74 a via the source opening 78 a. The drain block 82 b is electrically connected to thedrain metal layer 74 b via thedrain opening 78 b and to thecapacitor top electrode 74 c via thecapacitor opening 78 c. Thepad block 82c is electrically connected to thepad electrode 66 c via thepad opening 80. Thereafter, the transparentconductive layer 82 is electrically connected to thetransistor 60 andcapacitor 62. - The fabrication of the TFT-
LCD 50 therefore requires only four photo-etching processes. The structure of the TFT-LCD 50 includes thesubstrate 52, thethin film transistor 60, thecapacitor 62, and thepad 64 used as a gate bonding pad. As shown in FIG. 2G, thethin film transistor 60 includes agate electrode 66 a formed on thesubstrate 52, a transistor insulating layer 68 a and atransistor semiconductor layer 70 a formed on thegate electrode 66 a. A first dopedsilicon layer 72 a and a seconddoped silicon layer 72 b are further formed on thetransistor semiconductor layer 70 a, and separated by achannel area 75. Then, a sourceconductive layer 74 a is formed on the firstdoped silicon layer 72 a while a drainconductive layer 74 b is formed on the seconddoped silicon layer 72 b. Finally, a transistor passivation layer 76 a covers thechannel area 75, thesource metal layer 74 a, and thedrain metal layer 74 b. - In the
transistor 60, the sidewall of the transistor insulating layer 68 a is aligned with the sidewall of thetransistor semiconductor layer 70 a. The sidewall of thesource metal layer 74 a is aligned with the sidewall of the firstdoped silicon layer 72 a while the sidewall of thedrain metal layer 74 b is aligned with the sidewalls of the seconddoped silicon layer 72 b. In addition, the sidewall of thesource metal layer 74 a and thedrain metal layer 74 b are spaced apart from the sidewall of the insulatinglayer 70 a. - The
capacitor 62 comprises acapacitor bottom electrode 66 b in common with thegate electrode 66 a and covered by acapacitor insulating layer 68 b. Acapacitor semiconductor layer 70 b, a capacitor doped silicon layer 72 c, acapacitor top electrode 74 c, and acapacitor passivation layer 76 b are formed on thecapacitor insulating layer 68 b. A transparent conductive layer 82 b further covers thecapacitor passivation layer 76 b. Thecapacitor passivation layer 76 b has acapacitor opening 78 c, and thecapacitor top electrode 74 c is exposed in thecapacitor opening 78 c. The transparent conductive layer 82 b can then fill in thecapacitor opening 78 c and is electrically connected to thecapacitor top electrode 74 c. - The gate pad includes a
pad electrode 66 c formed on thesubstrate 52 and electrically connected to thegate electrode 66 a. Apad insulating layer 68 c, apad semiconductor layer 70 c, and apad passivation layer 76 c surround the boundary of thepad electrode 66 c to form apad opening 80. Thepad opening 80 penetrates thepad passivation layer 76 c, thepad semiconductor layer 70 c, and thepad insulating layer 68 c, so that thepad electrode 66 c is exposed in thepad opening 80. Besides, a transparentconductive layer 82 c fills in thepad opening 80 to electrically connect with thepad electrode 66 c. - The transistor passivation layer76 a has a source opening 78 a above the
source metal layer 74 a, and adrain opening 78 b above thedrain metal layer 78 b. The TFT-LCD 50 further comprises a transparent sourceconductive layer block 82 a, a transparent drain conductive layer block 82 b, and a transparent padconductive layer block 82 c. The transparent sourceconductive layer block 82 a connects to the sourceconductive layer 74 a via the source opening 78 a, the transparent drain conductive layer block 82 b connects to the drainconductive layer 74 b via thedrain opening 78 b, and the transparent padconductive layer block 82 c connects to thepad electrode 66 c via thepad opening 80. - Please refer to FIG. 3A and FIG. 3B. which are the schematic diagrams of the second embodiment in the present invention. The second embodiment can be applied to an in-plain-switch (IPS) type TFT-LCD. The second embodiment requires only three photo-etching processes (PEPs), and the first two steps are the same as these in the first embodiment. In the other word, the steps shown in FIG. 2A to FIG. 2D will be performed before the process shown in FIG. 3A.
- There is no transparent conductive layer for light transmission in the IPS type TFT-LCD. The IPS type TFT-LCD directly utilizes a metal layer as the driving electrode. Thus, as shown in FIG. 3A, the final step of the second embodiment is to remove portions of the
passivation layer 76, thesemiconductor layer 70, and the insulatinglayer 68 positioned (1) outside thefirst region 51, thesecond region 53, and thethird region 55, and (2) within thepad area 58 to form apad opening 80. - The above-mentioned liquid crystal display also includes a gate line and a signal line intercrossed with the gate line (both are not shown). The gate line is connected to the
gate electrode 66 a and thepad electrode 66 c. A signal bonding pad is position at the end of the signal line, which cross-sectional figure is shown as FIG. 3B. In FIG. 3B, an insulatinglayer 68 d, asemiconductor layer 70 d, and a dopedsilicon layer 72 d are formed, respectively, on thesubstrate 52. Asecond metal layer 74 d is formed in a predetermined area of the dopedsilicon layer 72 d, and apassivation layer 76 d covers both thesecond metal layer 74 d and the dopedsilicon layer 72 d. Further, anopening 82 is formed above thesecond metal layer 74 d, and thesecond metal layer 74 d is exposed and can be electrical connected with the outer circuit (not shown). - The structure of the second embodiment is similar to the first embodiment in the present invention. The major difference between the two embodiments includes: (1) there is no transparent conductive layer in the second embodiment, and (2) the
passivation layer 76 does not have openings at the position above thesource metal layer 74 a,drain metal layer 74 b, or thecapacitor top electrode 74 c. - Please refer to FIG. 4A to FIG. 4I which are the schematic diagrams of the third embodiment according to the present invention. In the third embodiment, three different kinds of capacitors can be fabricated in three
regions metal layer 66 is first deposited on thesubstrate 52, and patterned by a first photo-etching process (PEP-III-1) to form agate electrode 66 a, acapacitor bottom electrode 66 b, and apad electrode 66 c. - As shown in FIG. 4B, an first insulating
layer 681 is deposited on thesubstrate 52. The insulatinglayer 681 is then patterned by a second photo-etching process (PEP-III-2) . As shown in FIG. 4C, a capacitor insulating layer opening 84 a is formed incapacitor area 56 c to expose thecapacitor bottom electrode 66 b, and apad opening 84 b is formed inpad area 58 to expose thepad electrode 66 c. - As shown in FIG. 4D, an second
insulating layer 682, asemiconductor layer 70, a dopedsilicon layer 72, and asecond metal layer 74 are sequentially formed on thesubstrate 52. The secondinsulating layer 682 fills both the capacitor insulating layer opening 84 a and thepad opening 84 b. The total thickness of the first insulatinglayer 681 and the second insulatinglayer 682 of this embodiment is equal to the thickness of the insulatinglayer 68 of the first embodiment so that the structure of thetransistor 60 remains unchanged. - As shown in FIG. 4E, the pattern of the insulating
layer 682, thesemiconductor layer 70, the dopedsilicon layer 72, and themetal layer 74 are then defined by a third photo-etching process (PEP-III-3). First, achannel area 75 is defined in thetransistor area 54, and then removing both thesecond metal layer 74 and the dopedsilicon layer 72 positioned (a) within thechannel area 75, and (b) outside thetransistor area 54, andcapacitor areas metal layer 74 therefore forms asource metal layer 74 a and adrain metal layer 74 b in thetransistor area 54, and also formscapacitor top electrodes 74 c in thecapacitor areas channel area 75. Thus, thesemiconductor layer 70 is exposed outside thetransistor area 54, thecapacitor area 56 b, and thecapacitor area 56 c. - Moreover, as shown in FIG. 4F, a
passivation layer 76 is deposited to cover thefirst region 51, thesecond region 53, thethird regions transistor area 54, thecapacitor areas pad area 58, as well as filled into thechannel area 75. - As shown in FIG. 4G, the
passivation layer 76 is then patterned by a fourth photo-etching process(PEP-III-4). Portions of thepassivation layer 76 outside thefirst region 51 and thethird regions semiconductor layer 70 in thesecond region 53 and thethird region 55 a. Concurrently, a source opening 78 a is defined above thesource metal layer 74 a, adrain opening 78 b is defined above thedrain metal layer 74 b, andcapacitor openings 78 c are defined in thecapacitor areas passivation layer 76 are then removed within the source opening 78 a, thedrain opening 78 b, and thecapacitor opening 78 c. Therefore, thesource metal layer 74 a is exposed in the source opening 78 a of thetransistor area 54, thedrain metal layer 74 b is exposed in thedrain opening 78 b, the insulating layer is exposed in thecapacitor area 66 b, and the capacitortop electrodes 74 c are exposed in thecapacitor openings 78 c. - The
passivation layer 76 is then used as an etching mask to remove the unprotected portions of thesemiconductor layer 70 and the insulatinglayer 682. Therefore, the insulatinglayer 681 is exposed outside thefirst region 51, and thethird regions layer 681 is exposed in thesecond region 53 and thethird region 55 a. Further, thepad electrode 66 c is exposed in thepad opening 84 b, and the fabrication of thetransistor 60 and thecapacitor 62 b is thus completed. - The
pad opening 84 b shown in FIG. 4C can be formed by the second PEP (PEP-III-2) or after the fourth PEP(PEP-III-4), in other words, the second PEP(PEP-III-2) can be performed after the fourth PEP(PEP-III-4). - As shown in FIG. 4H, a transparent
conductive layer 82 is formed on thesubstrate 52 to cover thecapacitor areas drain opening 78 b, thecapacitor opening 78 c, and thepad opening 84 b. - Finally, as shown in FIG. 4I, the transparent
conductive layer 82 is patterned by a fifth photo-etching process (PEP-III-5). Therefore, the transparentconductive layer 82 is separated into at least three electrical-isolated parts including the source block 82 a, the drain block 82 b, and thepad block 82 c. Thesource block 82 a is electrically connected to thesource metal layer 74 a via the source opening 78 a, the drain block 82 b is electrically connected to thedrain metal layer 74 b via thedrain opening 78 b, thepad block 82 c is electrically connected to thepad electrode 66 c via thepad opening 84 b, and the transparentconductive layer 82 is electrically connected to thecapacitor top electrode 74 c. Besides, the transparentconductive layer 82 is electrically connected to thetransistor 60 and each capacitor after the fabrication of thecapacitor 62 a and thepad 64 is completed. - The transistor of the third embodiment is similar to that of the first embodiment, but the structures of the gate pad and the capacitor are different. As shown in FIG. 4I, the gate pad of the third embodiment includes a
pad electrode 66 c, apad insulating layer 681, and apad block 82 c of the transparent conductive layer. Thepad electrode 66 c is formed on thesubstrate 52 and electrically connected to thegate electrode 66 a, thepad insulating layer 681 surrounds the boundary of thepad electrode 66 c to form apad opening 84 b, and thepad opening 84 b is penetrated through thepad insulating layer 681 to expose thepad electrode 66 c. Thepad block 82 c is electrically connected to thepad electrode 66 c via thepad opening 84 b. - Three different kinds of capacitor structures are formed in the third embodiment. The
capacitor 62 a includes acapacitor bottom electrode 66 b common with thegate electrode 66 a, a insulatinglayer 681 covering thecapacitor bottom electrode 66 b, and the transparent conductive layer 82 b covering the insulatinglayer 681 and functions as a capacitor top electrode. - The
capacitor 62 b includes thecapacitor bottom electrode 66 b common with thegate electrode 66 a, the insulatinglayer 681 covering thecapacitor bottom electrode 66 b, and the insulatinglayer 682 as well as thesemiconductor layer 70 covering the insulatinglayer 681. Further, the dopedsilicon layer 72, thecapacitor top electrode 74 c, and thecapacitor passivation layer 76 c are formed on thesemiconductor layer 70. Thecapacitor passivation layer 76 c is covered by a transparentconductive layer 82 d. In addition, thecapacitor passivation layer 76 c includes acapacitor opening 78 c to expose thecapacitor top electrode 74 c. The transparentconductive layer 82 d fills in thecapacitor opening 78 c and electrically connects to thecapacitor top electrode 74 c. - The
capacitor 62 c is also similar to thecapacitor 62 b. The major difference between thesecapacitors capacitor 62 c has the insulatingopening 84 a in the insulatinglayer 681 to expose thecapacitor bottom electrode 66 b, and the insulatinglayer 682 will fill into the insulatingopening 84 a. Therefore, the distance between the capacitortop electrode 74 c and thecapacitor bottom electrode 66 b is smaller for resulting an increased capacitor value in thecapacitor 62 c. - Please refer to FIG. 5 which is the schematic diagram according to the fourth embodiment. This embodiment can be applied to an in-plain-switch (IPS) type TFT-LCD. The fourth embodiment of the present invention combines features of the second and third embodiments to form various different kinds of capacitors without using the transparent conductive layer because the IPS type TFT-LCD doesn't require the transparent conductive layer. Similarly, the first three steps of the fourth embodiment are the same as those of the third embodiment, a half-finished product as shown in FIG. 4F is manufactured.
- As shown in FIG. 5, portions of the
passivation layer 76, thesemiconductor layer 70, and the insulatinglayer 682 positioned (1) outside thefirst region 51, and (2) outside thethird regions transistor 60, thecapacitors pad 64 are then completed. There is no transparent conductive layer, therefore, the above method can be used in the fabrication of the IPS type TFT-LCD. In addition, ametal wire 62 a, rather than a capacitor, is formed in thethird region 55 a. - The major difference between the fourth embodiment and the third embodiment includes (1) the
passivation layer 76 of the fourth embodiment lacks the openings above the sourceconductive layer 74 a, the drainconductive layer 74 b, and thecapacitor top electrode 74 c, and (2) no transparent conductive layer is formed in the fourth embodiment. - The feature of the present invention is to deposit the
metal layer 74 above the dopedsilicon layer 72 for reducing the resistance of thetransistor 60 and thecapacitor 62, and increasing the operation rate. In the IPS type TFT-LCD, no transparentconductive layer 82 is needed, resulting in a reduction in both the resistance and the cost of the display. Another advantage of the present invention is the increased flexibility in circuit design since the same process can be used to manufacture different kinds of capacitors without affecting the structure of thetransistor 60 and thepad 64 or changing the area of thecapacitor area 66. - Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (25)
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TW089120205A TWI236557B (en) | 2000-09-29 | 2000-09-29 | TFT LCD and method of making the same |
TW089120205 | 2000-09-29 |
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US6440783B2 (en) * | 2000-08-04 | 2002-08-27 | Au Optronics Corp. | Method for fabricating a thin film transistor display |
US6545293B2 (en) * | 2000-09-30 | 2003-04-08 | Au Optronics Corp. | Thin film transistor flat display |
CN100386674C (en) * | 2006-03-02 | 2008-05-07 | 友达光电股份有限公司 | Method for manufacturing down base plate for liquid crystal display device |
US20080237596A1 (en) * | 2006-12-19 | 2008-10-02 | L.G.Philips Lcd Co., Ltd. | Liquid crystal display device and fabrication method thereof |
US20090032892A1 (en) * | 2005-11-21 | 2009-02-05 | Chian-Chih Hsiao | Image TFT array of a direct X-ray image sensor and method of fabricating the same |
TWI472039B (en) * | 2010-06-01 | 2015-02-01 | Chunghwa Picture Tubes Ltd | Thin film transistor and manufacturing method thereof |
US9184187B2 (en) * | 2012-10-19 | 2015-11-10 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Thin film transistor array manufacturing method |
JP2022088460A (en) * | 2010-08-27 | 2022-06-14 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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US20070254399A1 (en) * | 2006-04-27 | 2007-11-01 | Industrial Technology Research Institute | Low temperature direct deposited polycrystalline silicon thin film transistor structure and method for manufacturing the same |
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US6440783B2 (en) * | 2000-08-04 | 2002-08-27 | Au Optronics Corp. | Method for fabricating a thin film transistor display |
US6545293B2 (en) * | 2000-09-30 | 2003-04-08 | Au Optronics Corp. | Thin film transistor flat display |
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