US20020028635A1 - Utility wafer for chemical mechanical polishing - Google Patents
Utility wafer for chemical mechanical polishing Download PDFInfo
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- US20020028635A1 US20020028635A1 US09/544,734 US54473400A US2002028635A1 US 20020028635 A1 US20020028635 A1 US 20020028635A1 US 54473400 A US54473400 A US 54473400A US 2002028635 A1 US2002028635 A1 US 2002028635A1
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- peripheral edge
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- 238000005498 polishing Methods 0.000 title claims description 54
- 239000000126 substance Substances 0.000 title abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000005336 cracking Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 128
- 238000007517 polishing process Methods 0.000 description 8
- 238000004088 simulation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010017076 Fracture Diseases 0.000 description 1
- 208000013201 Stress fracture Diseases 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007524 flame polishing Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
- B23K26/3568—Modifying rugosity
- B23K26/3576—Diminishing rugosity, e.g. grinding; Polishing; Smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
Definitions
- the present invention relates generally to chemical mechanical polishing, and more specifically, to the use of utility wafers for simulating chemical mechanical polishing processes.
- CMP chemical mechanical planarization
- Perlov et al. and Tolles et al. disclose a CMP system having a planarization apparatus that is supplied wafers from cassettes located in an adjacent liquid filled bath.
- a transfer mechanism, or robot facilitates the transfer of the wafers from the bath to a transfer station.
- the transfer station generally contains a load cup that positions the wafer into one of four processing heads mounted to a carousel.
- the carousel moves each processing head sequentially over the load cup to receive a wafer. As the processing heads fill, the carousel moves the processing head and wafer through the planarization stations for polishing.
- the wafers are planarized by moving the wafer relative to a polishing pad in the presence of a slurry or other polishing fluid medium.
- the polishing pad may include an abrasive surface. Additionally, the slurry may contain both chemicals and abrasives that aid in the removal of material from the wafer. After completion of the planarization process, the wafer is returned back through the transfer station to the proper cassette located in the bath.
- R is the removal rate
- K p is the Preston coefficient
- P is the applied pressure between the workpiece and the abrasive pad
- ⁇ s/ ⁇ t is the linear velocity of the abrasive pad relative the workpiece.
- Preston's equation has shown to be a reasonably accurate model for the planarization of silicon dioxide, copper and tungsten, although the dependence of K p on process variables, such as slurry composition and pad properties, is not well understood.
- the polishing rate has been known to vary as much as 20 percent between pads having different hardness.
- most chemical mechanical polishing process modeling is performed using empirical data.
- a simulation of the processes is performed using utility wafers in the place of production wafers.
- the simulation comprises running a number of utility wafers through the chemical mechanical polishing system, while periodically inserting and polishing a test wafer from which the polishing attributes can be obtained to construct a model of the polishing process. For example, in an exemplary CMP simulation, approximately 2000 polishing cycles are run. After every 100 utility wafers that are polished, a test wafer is polished, removed and measured to obtain data indicative the process. Once approximately 2,000 polishing cycles are completed, a data base representative of the process can be constructed. Other simulations may be configured to run more or less polishing cycles, and may polish test wafers at different frequencies.
- the utility wafers typically used to simulate the polishing of the production wafers generally are silicon wafers covered with a thin layer of oxide.
- the oxide layer can only withstand one to two polishing cycles through the chemical mechanical polishing system.
- the utility wafer, once the oxide has been substantially removed by polishing, can be reused after being stripped of the remaining oxide coating and a new layer of oxide is redeposited thereon. As the cost of depositing an oxide layer is not nominal, simulation tests that use between 1,500-2,000 utility wafers can become quite costly.
- the thickness of the Cuong van Vu utility wafer provides some resistance to breaking when the wafer is exposed to the forces applied in a chemical mechanical planarization process.
- Cuong van Vu teaches a quartz wafer thickness of 50 mils, and a silicon/quartz composite wafer that can withstand the surface tension forces experienced during the removal of the polished wafer from the polishing pad (dechucking) without breaking or cracking the wafer.
- a utility wafer which generally includes a first side and a second side opposing the first side and defining a thickness therebetween.
- a peripheral edge couples the first side and the second side.
- An edge defined at the interface of the peripheral edge and the first side is relieved, i.e., the edge has a chamfer, radius or other relief.
- a second edge at the interface of the peripheral edge and the second side is also relieved.
- the peripheral edge is polished.
- a method for fabricating a utility wafer generally comprises providing a wafer having a thickness of at least about 45 mils relieving at least one edge of the wafer and polishing the wafer.
- the wafer is laser polished and annealed.
- FIG. 1 is a schematic plan view of a chemical mechanical planarization system
- FIG. 2 is an elevation of a utility wafer.
- FIG. 1 depicts a schematic plan view of an exemplary chemical mechanical polisher 100 .
- the polisher 100 has a plurality of polishing stations 106 (e.g., three), a carousel 102 that supports four polishing heads 110 , a wafer load/unload assembly 104 , and a transfer station 108 .
- An input/output robot 116 loads and unloads wafers 114 to/from the transfer station 108 .
- Four polishing heads 110 are mounted in the carousel 102 .
- the carousel 102 is partially cut-away to provide a view of the components of the transfer station 108 . As such, one of the four polishing heads 110 is not shown.
- the carousel 102 rotates about a central axis such that any one of the polishing heads 110 may be positioned at any one of the polishing stations 106 or the transfer station 108 . Consequently, the wafer 114 can be loaded into a particular polishing head 110 , and the carousel 102 can move the head 110 to a particular polishing station 106 .
- the wafer 114 may be a production wafer, a test wafer or a utility wafer. Generally, the wafer 114 is transferred between the polisher 100 and other systems (e.g., wafer cleaners) or at least one wafer cassette 128 via the wafer input/output robot 116 .
- the input/output robot 116 has a gripper 118 (e.g., a vacuum gripper) that retains the wafer 114 during transfer between the transfer station 108 and the wafer cassette 128 .
- the wafer cassette 128 holds production wafers.
- the wafer cassette typically holds a plurality of utility wafers 130 , and one or more test wafers 132 .
- the transfer station 108 comprises at least one buffer station 120 (preferably, two buffer stations 120 A and 120 B) and a transfer robot 122 .
- the input/output robot 116 places the wafer 114 that is entering the polisher 100 into the input buffer station 120 B.
- the transfer station robot 122 retrieves the wafer 114 from the input buffer station 120 B and moves the wafer 114 to the wafer load/unload assembly 104 .
- the wafer load/unload assembly 104 positions the wafer 114 into a polishing head 110 .
- the transfer station 108 may be of any type known in the art for transferring a wafer between input/output robot and a polishing head.
- the transfer station 108 is a transfer station that is described in commonly assigned U.S. patent application Ser. No. 09/414,771, filed Oct. 6, 1999, to Tobin, and is incorporated herein by reference.
- the carousel 102 retrieves the wafer 114 from the wafer load/unload assembly 104 and proceeds to polish the wafer 114 . While the transfer robot 122 is busy moving a wafer 114 from the buffer station 120 to the wafer load/unload assembly 104 , the input/output robot 116 may position another wafer 114 into the empty input buffer station 120 B.
- the carousel 102 moves the wafer 114 to the wafer load/unload assembly 104 and releases the wafer 114 .
- the transfer robot 122 then retrieves the wafer 114 from the wafer load/unload assembly 104 and places the wafer 114 into the output buffer station 120 A.
- the polished wafer 114 is then retrieved from the output buffer station 120 B by the input/output robot 116 .
- FIG. 2 depicts embodiment of a utility wafer 130 according to the invention.
- the utility wafer 130 is typically fabricated out of a ceramic material.
- the utility wafer 130 substantially comprises quartz.
- the utility wafer 130 has a first side 202 , a second side 204 side and a peripheral edge 208 .
- one of the first or second sides 202 , 204 may comprise a reflective coating.
- the first side 202 is substantially parallel to the second side 204 and defines a thickness 216 of at least 1.5 mm.
- thinner wafers will provide some utility, thicker wafers will allow for a greater number of passes through the polisher 100 . Tests have shown that a thickness of 1.5 mm will exhibit a life in excess of 100 polishing cycles.
- the first side 202 and the peripheral edge 208 come together to form a first edge 206 .
- the second side 204 and the peripheral edge 208 come together to form a second edge 210 .
- At least one of the edges 206 , 210 is relieved to remove the otherwise sharp edge by chamfering, providing a radius, tapering, undercutting or other relief for removing the sharp edge.
- the first edge 206 comprises a first chamfer 218 .
- the first chamfer 218 generally has an angle 212 that ranges between about 30 to about 60 degrees relative the first side 202 .
- angle 212 may be utilized.
- the first chamfer 218 extends a distance 214 along the peripheral edge 208 . As the utility wafer 130 is polished and material is removed from the face 202 , the distance 214 will diminish. In one embodiment, the distance 214 is at least about 0.5 mm before initial polishing. The first chamfer 218 removes the sharp corner that would otherwise be present at the interface of the first side 202 and peripheral edge 208 .
- the first chamfer 206 thus minimizes the probability of chipping and the propagation of stress fractures through the utility wafer 130 when the peripheral edge 208 comes into contact with other objects such as, for example, a retaining ring of the polishing head 110 .
- the first edge 206 may alternatively comprise a radius of at least 5 mils.
- the second edge 210 may comprise a second chamfer 220 opposite the first chamfer 206 .
- the second chamfer 220 is fabricated identically to the first chamfer 218 , although the relative geometry of the chamfers 218 , 220 will vary as the utility wafer 130 is polished.
- the relief at the first edge 206 may be different than the relief at the second edge 210 , i.e., the first edge 206 may be chamfered while the second edge 210 has a radius
- the peripheral edge 208 of the utility wafer 130 is optionally polished after relieving one or both of the edges 206 , 210 .
- Polishing generally fuses the peripheral edge 208 of the utility wafer 130 such that any cracks or chips that may be present at the peripheral edge 208 and particularly the edges 206 and 210 , do not propagate into fractures or allow chips to be generated. Moreover, the fused peripheral edge 208 typically has more impact resistance, and is less prone to chipping than a non-fused surface. Polishing is generally in the form of heat polishing such as laser polishing or flame polishing. Optionally, polishing may be followed by annealing at an elevated temperature of, for example, about 1165° C. Prior to annealing, the utility wafer 130 should be cleaned to remove surface contamination.
- a simulation of a chemical mechanical planarization process can be performed by processing a plurality of utility wafers 130 through the polisher 100 , while periodically processing the test wafer 132 at predetermined intervals during the simulation.
- approximately twenty-five utility wafers 130 and at least one test wafer 132 are loaded into the wafer cassette 128 .
- the input/output robot 116 retrieves one of the utility wafers 130 from the cassette 128 and places the utility wafer 130 (shown as wafer 114 retained by robot 116 ) on the transfer station 108 .
- the transfer station 108 transfers the utility wafer 130 to the load/unload assembly 104 where the utility wafer is loaded one of the four polishing heads 110 mounted to the carousel 102 .
- the utility wafer 130 is then moved to a polishing station 106 and polished. Once polishing is complete, the utility wafer 130 is returned to the cassette 128 and another utility wafer is retrieved and polished. This sequence repeats until a predetermined quantity of utility wafers 130 are polished. If the required number of passes through the polisher 100 are greater than the number of utility wafers 130 in the cassette 128 , then the utility wafers 130 passed through the polisher more than once as required.
- the test wafer 132 is retrieved from the cassette 128 and processed in the polisher 100 . Once processed, the test wafer 132 is returned to the cassette 128 and another sequence of polishing the utility wafers 130 are preformed.
- the test wafer 132 is measured (typically remotely or in the polisher 100 before transfer to the cassette 128 ) to acquire data indicative of the polishing process.
- thickness of an oxide layer may be measured to indicate polishing rate and uniformity of the polishing process.
Abstract
A utility wafer, more specifically, an utility wafer for simulating a workpiece in a semiconductor processing system. The utility wafer includes a first side, a second side and a peripheral edge wherein one or both edges of the peripheral edge are relieved to remove the otherwise sharp edge. In one embodiment, the peripheral edge is polished. The utility wafer is resistant to chipping, stress cracking and breakage when undergoing chemical mechanical planarization.
Description
- 1. Field of Invention
- The present invention relates generally to chemical mechanical polishing, and more specifically, to the use of utility wafers for simulating chemical mechanical polishing processes.
- 2. Background of Invention
- In semiconductor wafer processing, the use of chemical mechanical planarization, or CMP, has gained favor due to the enhanced ability to stack multiple devices on a semiconductor workpiece, or substrate, such as a wafer. As the demand for planarization of layers formed on wafers in semiconductor fabrication increases, the requirement for greater system (i.e., process tool) throughput with less wafer damage and enhanced wafer planarization has also increased.
- Two exemplary CMP systems that address these issues are described in U.S. Pat. No. 5,804,507, issued Sep. 8, 1998, to Perlov et al., and in U.S. Pat. No. 5,738,574, issued Apr. 15, 1998, to Tolles et al., both of which are hereby incorporated by reference. Perlov et al. and Tolles et al. disclose a CMP system having a planarization apparatus that is supplied wafers from cassettes located in an adjacent liquid filled bath. A transfer mechanism, or robot, facilitates the transfer of the wafers from the bath to a transfer station. The transfer station generally contains a load cup that positions the wafer into one of four processing heads mounted to a carousel. The carousel moves each processing head sequentially over the load cup to receive a wafer. As the processing heads fill, the carousel moves the processing head and wafer through the planarization stations for polishing. The wafers are planarized by moving the wafer relative to a polishing pad in the presence of a slurry or other polishing fluid medium.
- The polishing pad may include an abrasive surface. Additionally, the slurry may contain both chemicals and abrasives that aid in the removal of material from the wafer. After completion of the planarization process, the wafer is returned back through the transfer station to the proper cassette located in the bath.
-
- where:
- R is the removal rate;
- Kp is the Preston coefficient;
- P is the applied pressure between the workpiece and the abrasive pad; and
- Δs/Δt is the linear velocity of the abrasive pad relative the workpiece.
- Preston's equation has shown to be a reasonably accurate model for the planarization of silicon dioxide, copper and tungsten, although the dependence of Kp on process variables, such as slurry composition and pad properties, is not well understood. For example, the theoretical value of the Preston coefficient Kp=½E (where E is Young's modulus of the surface being polished) does not explain the polishing rate variation with other important process variables such as pad type, pad condition, slurry abrasive and slurry chemicals Illustrative of this is that the polishing rate has been known to vary as much as 20 percent between pads having different hardness. As a result, most chemical mechanical polishing process modeling is performed using empirical data.
- To better predict the results of an actual chemical mechanical polishing process, typically a simulation of the processes is performed using utility wafers in the place of production wafers. Generally, the simulation comprises running a number of utility wafers through the chemical mechanical polishing system, while periodically inserting and polishing a test wafer from which the polishing attributes can be obtained to construct a model of the polishing process. For example, in an exemplary CMP simulation, approximately 2000 polishing cycles are run. After every 100 utility wafers that are polished, a test wafer is polished, removed and measured to obtain data indicative the process. Once approximately 2,000 polishing cycles are completed, a data base representative of the process can be constructed. Other simulations may be configured to run more or less polishing cycles, and may polish test wafers at different frequencies.
- The utility wafers typically used to simulate the polishing of the production wafers generally are silicon wafers covered with a thin layer of oxide. Generally, the oxide layer can only withstand one to two polishing cycles through the chemical mechanical polishing system. The utility wafer, once the oxide has been substantially removed by polishing, can be reused after being stripped of the remaining oxide coating and a new layer of oxide is redeposited thereon. As the cost of depositing an oxide layer is not nominal, simulation tests that use between 1,500-2,000 utility wafers can become quite costly.
- One solution to the high cost of the oxide coated silicon wafers is described in U.S. Pat. No. 5,890,951, issued Apr. 6, 1999, to Cuong van Vu. Cuong van 25 Vu teaches a utility wafer used for mechanically conditioning and stabilizing a polishing pad. This utility wafer is comprised of a high purity solid ceramic or metal member that has a thickness of between about 3-150 mils.
- The thickness of the Cuong van Vu utility wafer provides some resistance to breaking when the wafer is exposed to the forces applied in a chemical mechanical planarization process. For example, Cuong van Vu teaches a quartz wafer thickness of 50 mils, and a silicon/quartz composite wafer that can withstand the surface tension forces experienced during the removal of the polished wafer from the polishing pad (dechucking) without breaking or cracking the wafer.
- However, ceramic wafers of this type are prone to chipping as the edge of the wafer contacts the retaining ring of the polishing head during the planarization process, during dechucking from the polishing pad, or during handling in general. As the wafer contacts the retaining ring, pieces of material break off from the corners and stress cracks tend to propagate from the chipped edges as the wafer contacts against the retaining ring. These chips and cracks generally lead to premature failure of the utility wafer.
- Therefore, there is a need in the art for a utility wafer that provides a durable, low cost means for simulating a wafer in a chemical mechanical polishing system.
- In one aspect, a utility wafer is provided which generally includes a first side and a second side opposing the first side and defining a thickness therebetween. A peripheral edge couples the first side and the second side. An edge defined at the interface of the peripheral edge and the first side is relieved, i.e., the edge has a chamfer, radius or other relief. Optionally, a second edge at the interface of the peripheral edge and the second side is also relieved. In another embodiment, the peripheral edge is polished.
- In another aspect, a method for fabricating a utility wafer is provided. The method generally comprises providing a wafer having a thickness of at least about 45 mils relieving at least one edge of the wafer and polishing the wafer. In one embodiment the wafer is laser polished and annealed.
- The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
- FIG. 1 is a schematic plan view of a chemical mechanical planarization system; and
- FIG. 2 is an elevation of a utility wafer.
- To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
- FIG. 1 depicts a schematic plan view of an exemplary chemical
mechanical polisher 100. Thepolisher 100 has a plurality of polishing stations 106 (e.g., three), acarousel 102 that supports four polishingheads 110, a wafer load/unloadassembly 104, and atransfer station 108. An input/output robot 116 loads and unloadswafers 114 to/from thetransfer station 108. Four polishingheads 110 are mounted in thecarousel 102. Thecarousel 102 is partially cut-away to provide a view of the components of thetransfer station 108. As such, one of the four polishingheads 110 is not shown. Thecarousel 102 rotates about a central axis such that any one of the polishing heads 110 may be positioned at any one of the polishingstations 106 or thetransfer station 108. Consequently, thewafer 114 can be loaded into aparticular polishing head 110, and thecarousel 102 can move thehead 110 to aparticular polishing station 106. - The
wafer 114 may be a production wafer, a test wafer or a utility wafer. Generally, thewafer 114 is transferred between thepolisher 100 and other systems (e.g., wafer cleaners) or at least onewafer cassette 128 via the wafer input/output robot 116. The input/output robot 116 has a gripper 118 (e.g., a vacuum gripper) that retains thewafer 114 during transfer between thetransfer station 108 and thewafer cassette 128. In normal wafer processing, thewafer cassette 128 holds production wafers. During simulations of wafer processing, the wafer cassette typically holds a plurality ofutility wafers 130, and one ormore test wafers 132. - The
transfer station 108 comprises at least one buffer station 120 (preferably, twobuffer stations transfer robot 122. The input/output robot 116 places thewafer 114 that is entering thepolisher 100 into theinput buffer station 120B. After thetransfer station 108 receives thewafer 114 from therobot 116 and therobot 116 has cleared thetransfer station 108, thetransfer station robot 122 retrieves thewafer 114 from theinput buffer station 120B and moves thewafer 114 to the wafer load/unloadassembly 104. The wafer load/unloadassembly 104 positions thewafer 114 into a polishinghead 110. Thetransfer station 108 may be of any type known in the art for transferring a wafer between input/output robot and a polishing head. Preferably, thetransfer station 108 is a transfer station that is described in commonly assigned U.S. patent application Ser. No. 09/414,771, filed Oct. 6, 1999, to Tobin, and is incorporated herein by reference. - The
carousel 102 retrieves thewafer 114 from the wafer load/unloadassembly 104 and proceeds to polish thewafer 114. While thetransfer robot 122 is busy moving awafer 114 from the buffer station 120 to the wafer load/unloadassembly 104, the input/output robot 116 may position anotherwafer 114 into the emptyinput buffer station 120B. - When the
wafer 114 has completed a polishing procedure, thecarousel 102 moves thewafer 114 to the wafer load/unloadassembly 104 and releases thewafer 114. Thetransfer robot 122 then retrieves thewafer 114 from the wafer load/unloadassembly 104 and places thewafer 114 into theoutput buffer station 120A. Thepolished wafer 114 is then retrieved from theoutput buffer station 120B by the input/output robot 116. - FIG. 2 depicts embodiment of a
utility wafer 130 according to the invention. Theutility wafer 130 is typically fabricated out of a ceramic material. In one embodiment, theutility wafer 130 substantially comprises quartz. Theutility wafer 130 has afirst side 202, asecond side 204 side and aperipheral edge 208. Optionally, one of the first orsecond sides first side 202 is substantially parallel to thesecond side 204 and defines athickness 216 of at least 1.5 mm. One skilled in the art will appreciate that although thinner wafers will provide some utility, thicker wafers will allow for a greater number of passes through thepolisher 100. Tests have shown that a thickness of 1.5 mm will exhibit a life in excess of 100 polishing cycles. - The
first side 202 and theperipheral edge 208 come together to form afirst edge 206. Thesecond side 204 and theperipheral edge 208 come together to form asecond edge 210. At least one of theedges - In one embodiment the
first edge 206 comprises afirst chamfer 218. Thefirst chamfer 218 generally has anangle 212 that ranges between about 30 to about 60 degrees relative thefirst side 202. One skilled in the art will appreciate thatother angles 212 may be utilized. Thefirst chamfer 218 extends adistance 214 along theperipheral edge 208. As theutility wafer 130 is polished and material is removed from theface 202, thedistance 214 will diminish. In one embodiment, thedistance 214 is at least about 0.5 mm before initial polishing. Thefirst chamfer 218 removes the sharp corner that would otherwise be present at the interface of thefirst side 202 andperipheral edge 208. Thefirst chamfer 206 thus minimizes the probability of chipping and the propagation of stress fractures through theutility wafer 130 when theperipheral edge 208 comes into contact with other objects such as, for example, a retaining ring of the polishinghead 110. One skilled in the art will appreciate that other relief geometries, chamfer angles and distances may be readily substituted without departing from the teachings herein. For example, thefirst edge 206 may alternatively comprise a radius of at least 5 mils. - Optionally, the
second edge 210 may comprise asecond chamfer 220 opposite thefirst chamfer 206. Typically, thesecond chamfer 220 is fabricated identically to thefirst chamfer 218, although the relative geometry of thechamfers utility wafer 130 is polished. One skilled in the art will appreciate that the relief at thefirst edge 206 may be different than the relief at thesecond edge 210, i.e., thefirst edge 206 may be chamfered while thesecond edge 210 has a radius - In another embodiment, the
peripheral edge 208 of theutility wafer 130 is optionally polished after relieving one or both of theedges peripheral edge 208 of theutility wafer 130 such that any cracks or chips that may be present at theperipheral edge 208 and particularly theedges peripheral edge 208 typically has more impact resistance, and is less prone to chipping than a non-fused surface. Polishing is generally in the form of heat polishing such as laser polishing or flame polishing. Optionally, polishing may be followed by annealing at an elevated temperature of, for example, about 1165° C. Prior to annealing, theutility wafer 130 should be cleaned to remove surface contamination. - Referring to FIGS. 1 and 2, in operation, a simulation of a chemical mechanical planarization process can be performed by processing a plurality of
utility wafers 130 through thepolisher 100, while periodically processing thetest wafer 132 at predetermined intervals during the simulation. In an exemplary test sequence, approximately twenty-fiveutility wafers 130 and at least onetest wafer 132 are loaded into thewafer cassette 128. The input/output robot 116 retrieves one of theutility wafers 130 from thecassette 128 and places the utility wafer 130 (shown aswafer 114 retained by robot 116) on thetransfer station 108. Thetransfer station 108 transfers theutility wafer 130 to the load/unloadassembly 104 where the utility wafer is loaded one of the four polishingheads 110 mounted to thecarousel 102. - The
utility wafer 130 is then moved to a polishingstation 106 and polished. Once polishing is complete, theutility wafer 130 is returned to thecassette 128 and another utility wafer is retrieved and polished. This sequence repeats until a predetermined quantity ofutility wafers 130 are polished. If the required number of passes through thepolisher 100 are greater than the number ofutility wafers 130 in thecassette 128, then theutility wafers 130 passed through the polisher more than once as required. - Once the predetermined number of
utility wafers 130 have been polished, thetest wafer 132 is retrieved from thecassette 128 and processed in thepolisher 100. Once processed, thetest wafer 132 is returned to thecassette 128 and another sequence of polishing theutility wafers 130 are preformed. Thetest wafer 132 is measured (typically remotely or in thepolisher 100 before transfer to the cassette 128) to acquire data indicative of the polishing process. An example, thickness of an oxide layer may be measured to indicate polishing rate and uniformity of the polishing process. - The cycle of polishing a number of
utility wafers 130 followed by atest wafer 132 is repeated until the predetermined number of cycles through thepolisher 100 have completed. Data fromtest wafer 132 is compiled to create a data base from which a model of the polishing process just simulated can be constructed. - Although the teachings of the present invention that have been shown and described in detail herein, those skilled in the art can readily devise other varied embodiments that still incorporate the teachings and do not depart from the spirit of the invention.
Claims (23)
1. A utility wafer for use in a semiconductor wafer planarization system comprising:
a first side;
a second side opposing the first side and defining a thickness therebetween;
a peripheral edge coupled to the first side at an edge, the edge being relieved.
2. The utility wafer of claim 1 , wherein the edge is chamfered.
3. The utility wafer of claim 2 , wherein the chamfer is between about 30 to about 60 degrees relative the first side.
4. The utility wafer of claim 2 , wherein the chamfer is at least 0.5 mm along the peripheral edge.
5. The utility wafer of claim 1 further comprising a second edge at the interface of the second side and the peripheral edge, the second edge being relieved.
6. The utility wafer of claim 1 , wherein the edge has a radius.
7. The utility wafer of claim 6 , wherein the radius is 5 mils.
8. The utility wafer of claim 1 , wherein the peripheral edge is polished.
9. The utility wafer of claim 1 , wherein the peripheral edge is flame polished.
10. The utility wafer of claim 1 , wherein the peripheral edge is laser polished.
11. The utility wafer of claim 10 , wherein the laser polished peripheral edge is annealed.
12. The utility wafer of claim 1 , wherein the thickness is of at least 1.5 mm.
13. The utility wafer of claim 1 , wherein the thickness substantially comprises ceramic.
14. The utility wafer of claim 1 , wherein the thickness substantially comprises quartz.
15. A utility wafer for using in a semiconductor wafer planarization system comprising:
a first side;
an opposing second side; and
a peripheral edge coupled to the first side at a first edge and couple to the second side at a second edge, the first edge and the edge being relieved.
16. The utility wafer of claim 15 , wherein the first edge and the second edge are each chamfered at least 0.5 mm along the peripheral edge, and wherein the peripheral edge is laser polished and annealed.
17. A method for fabricating a utility wafer comprising the steps of:
providing a ceramic disk having a thickness of at least 1.5 mm; and
relieving at least one edge of the disk.
18. The method of claim 17 further comprising:
relieving a second edge of the disk.
19. The method of claim 17 further comprising the step of:
polishing a perimeter of the disk.
20. The method of claim 17 , wherein the polishing step comprises:
laser polishing.
21. The method of claim 17 , wherein the polishing step further comprises:
coating one side of the disk with a reflective material.
22. The method of claim 17 , wherein the polishing step further comprises:
annealing the disk.
23. The method of claim 17 , wherein the annealing step further comprises:
heating the disk to about 1165 degrees Celsius for about 35 minutes.
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Cited By (1)
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US20070196699A1 (en) * | 2004-08-11 | 2007-08-23 | Showa Denko K.K. | Silicon substrate for magnetic recording medium, manufacturing method thereof, and magnetic recording medium |
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US6962521B2 (en) * | 2000-07-10 | 2005-11-08 | Shin-Etsu Handotai Co., Ltd. | Edge polished wafer, polishing cloth for edge polishing, and apparatus and method for edge polishing |
US7980000B2 (en) | 2006-12-29 | 2011-07-19 | Applied Materials, Inc. | Vapor dryer having hydrophilic end effector |
KR101992778B1 (en) * | 2017-11-01 | 2019-06-25 | 에스케이실트론 주식회사 | Wafer and method for analyzing shape of the same |
EP3567138B1 (en) * | 2018-05-11 | 2020-03-25 | SiCrystal GmbH | Chamfered silicon carbide substrate and method of chamfering |
EP3567139B1 (en) | 2018-05-11 | 2021-04-07 | SiCrystal GmbH | Chamfered silicon carbide substrate and method of chamfering |
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JPH0624199B2 (en) * | 1982-07-30 | 1994-03-30 | 株式会社日立製作所 | Wafer processing method |
JPH0637025B2 (en) * | 1987-09-14 | 1994-05-18 | スピードファム株式会社 | Wafer mirror surface processing equipment |
US5117590A (en) * | 1988-08-12 | 1992-06-02 | Shin-Etsu Handotai Co., Ltd. | Method of automatically chamfering a wafer and apparatus therefor |
JP2571477B2 (en) * | 1991-06-12 | 1997-01-16 | 信越半導体株式会社 | Wafer notch chamfering device |
JP2559650B2 (en) * | 1991-11-27 | 1996-12-04 | 信越半導体株式会社 | Wafer chamfer polishing device |
KR0185234B1 (en) * | 1991-11-28 | 1999-04-15 | 가부시키 가이샤 토쿄 세이미쯔 | Method of chamfering semiconductor wafer |
US5226101A (en) * | 1992-06-15 | 1993-07-06 | Siecor Corporation | Method of laser polishing fiber optic connectors |
JPH07323420A (en) * | 1994-06-02 | 1995-12-12 | Tokyo Seimitsu Co Ltd | Manufacture of wafers and device thereof |
JPH081493A (en) * | 1994-06-17 | 1996-01-09 | Shin Etsu Handotai Co Ltd | Mirror finished surface polishing method for wafer chamfering part and mirror finished surface polishing device |
JP3580600B2 (en) * | 1995-06-09 | 2004-10-27 | 株式会社ルネサステクノロジ | Method for manufacturing semiconductor device, semiconductor wafer used for the same, and method for manufacturing the same |
JP3129172B2 (en) * | 1995-11-14 | 2001-01-29 | 日本電気株式会社 | Polishing apparatus and polishing method |
US5890951A (en) | 1996-04-15 | 1999-04-06 | Lsi Logic Corporation | Utility wafer for chemical-mechanical planarization |
JP3620679B2 (en) * | 1996-08-27 | 2005-02-16 | 信越半導体株式会社 | Chamfering device and chamfering method for wafer with loose abrasive grains |
US6159081A (en) * | 1997-09-09 | 2000-12-12 | Hakomori; Shunji | Method and apparatus for mirror-polishing of workpiece edges |
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US20070196699A1 (en) * | 2004-08-11 | 2007-08-23 | Showa Denko K.K. | Silicon substrate for magnetic recording medium, manufacturing method thereof, and magnetic recording medium |
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