US20020022376A1 - Method for fabricating gate oxide film of semiconductor device - Google Patents

Method for fabricating gate oxide film of semiconductor device Download PDF

Info

Publication number
US20020022376A1
US20020022376A1 US09/770,672 US77067201A US2002022376A1 US 20020022376 A1 US20020022376 A1 US 20020022376A1 US 77067201 A US77067201 A US 77067201A US 2002022376 A1 US2002022376 A1 US 2002022376A1
Authority
US
United States
Prior art keywords
oxide film
annealing
gate oxide
semiconductor substrate
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/770,672
Other versions
US6380102B1 (en
Inventor
Jong-Hyuk Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Assigned to HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. reassignment HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OH, JONG-HYUK
Publication of US20020022376A1 publication Critical patent/US20020022376A1/en
Application granted granted Critical
Publication of US6380102B1 publication Critical patent/US6380102B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • the present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a gate oxide film of a semiconductor device by which semiconductor devices having different electrical characteristics can be implemented in the same chip.
  • a transistor of a memory cell unit and a transistor of a peripheral circuit have a different operating voltage with each other.
  • the transistor of the memory cell unit fabricated with a fine line width operates at a voltage less than 1.8V
  • the transistor of the peripheral circuit operates at a voltage of 3.3V or 5V for matching with exterior system equipment.
  • FIGS. 1A through 1D illustrate a method for fabricating a gate oxide film by a dual step oxidation process.
  • a semiconductor substrate 10 is prepared.
  • a first gate oxide film 11 is formed on the top surface of the semiconductor substrate 10 .
  • a second gate oxide film 12 is formed on the top surface of the first gate oxide film 11 and the top surface of the semiconductor device 10 .
  • FIGS. 2A through 2D illustrates a method for fabricating a gate oxide film using a nitrogen ion implantation process.
  • a semiconductor substrate 20 is prepared.
  • a screen oxide film 21 is formed on the top surface of the semiconductor substrate 20 .
  • an ion implantation mask 22 is formed on the screen oxide film 21 of a portion on which a relatively thick oxide film is to be formed.
  • nitrogen (N 2 ) ions are implanted into the semiconductor substrate 20 of a portion being not covered with the ion implantation mask 22 .
  • a gate oxide film 23 is formed on the top surface of the semiconductor substrate 20 , as illustrated in FIG. 2D, a thin oxide film 23 a is formed on a portion into which nitrogen ions are implanted, because oxidation is restrained, and a relatively thick oxide film 23 b is formed on a portion into which nitrogen ions are not implanted.
  • a semiconductor substrate 30 is prepared.
  • a screen oxide film 31 is formed on the top surface of the semiconductor substrate 30 .
  • an ion implantation mask 32 is formed on the top surface of the screen oxide film 31 of a portion on which a relatively thin gate oxide film is to be formed.
  • fluoride ions are implanted into the semiconductor substrate 30 using the ion implantation mask 32 .
  • a gate oxide film 33 having different thicknesses is formed on the top surface of the semiconductor substrate 30 by oxidation of the semiconductor substrate 30 . That is, a thick gate oxide film is formed on the top surface of the semiconductor of a portion into which fluoride ions are implanted, and a thin gate oxide film is formed on a portion into which fluoride ions are not implanted.
  • the above-described conventional methods for fabricating a gate oxide film has the following problems.
  • the method for fabricating a gate oxide film by the dual step oxidation process has a complicated procedure, and a peripheral portion of a fabricated, thick gate oxide film becomes thinner and a breakdown is easily occurred on a thinned portion.
  • the nitrogen implantation process is disadvantageous in that, in case of forming a gate oxide film on the top surface of the semiconductor substrate into which nitrogen ions are implanted, the gate oxide film is degraded, although it is advantageous in that a smaller amount of ions can be implanted as to compared to the fluoride ion implantation process, which rather decreases the amount of leakage current.
  • the present invention provides a method for fabricating a gate oxide film of a semiconductor device having a small leakage current amount and a high reliability by reducing the concentration of nitrogen in the gate oxide film when a gate oxide film having different thicknesses according to its portion is fabricated on the top surface of a semiconductor substrate using a nitrogen ion implantation process.
  • a method for fabricating a gate oxide film of a semiconductor device includes the steps of: forming a screen oxide film on the top surface of a semiconductor substrate; forming an ion implantation mask on parts of the top surface of the screen oxide film; implanting nitrogen ions into the semiconductor substrate using the ion implantation mask; removing the ion implantation mask and the screen oxide film; forming an oxide film on the top surface of the semiconductor substrate; and annealing the semiconductor substrate.
  • a method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the pre-annealing step by a process of annealing at 500-900° C. by a furnace annealing method.
  • a method for fabricating a gate oxide film of a semiconductor device wherein the pre-annealing step is a process of annealing at 850-1200° C. by a rapid thermal annealing method.
  • a method for fabricating a gate oxide film of a semiconductor device wherein the oxide film formation step being a method for thermal oxidation at a furnace of 700-950° C.
  • a method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the oxide film formation step being a method for thermal oxidation at 850-1200° C. at the rapid thermal annealing method.
  • a method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the annealing step being performed by means of the rapid thermal annealing method in a N 2 O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
  • the annealing step can also be performed by means of the thermal annealing method in an O 3 atmosphere at a temperature of 400-1200° C. for about five minutes.
  • the annealing step can also be performed by means of the furnace annealing method in a N 2 O atmosphere at a temperature of 850-1200° C. for about one hour.
  • a method for fabricating a gate oxide film of a semiconductor device according to the present invention wherein the annealing step is performed by means of the rapid thermal annealing method in a N 2 O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
  • FIGS. 1A through 1D are a process chart illustrating one example of a method for fabricating a gate oxide film according to the conventional art
  • FIGS. 2A through 2D are a process chart illustrating another example of a method for fabricating a gate oxide film according to the conventional art
  • FIGS. 3A through 3D are a process chart illustrating still another example of a method for fabricating a gate oxide film according to the conventional art
  • FIGS. 4A through 4D are a process chart illustrating a method for fabricating a gate oxide film according to the present invention.
  • FIG. 5 is a graph illustrating the results of the SIMS analysis after annealing
  • FIG. 6 is a graph illustrating the changes in leakage current after annealing of a gate oxide film.
  • FIG. 7 is a graph illustrating the characteristics of an oxide film, e.g., a graph illustrating the amount of electric charge accumulated in the oxide film to the breakdown of the oxide film.
  • a screen oxide film 41 is formed on the top surface of a semiconductor device at a thickness of less than 200 ⁇ .
  • an ion implantation mask 42 is formed on the top surface of the screen oxide film 41 .
  • the ion implantation mask 42 is formed only on the top surface of a portion on which a relatively thick gate oxide film is to be formed.
  • nitrogen ions are implanted into the semiconductor substrate 40 .
  • the ion implantation process is performed with the implantation amount of nitrogen ions ranging from 5 ⁇ 10 13 cm 2 to 5 ⁇ 10 11 cm 2 and the ion implantation energy of 5-50 KeV.
  • a pre-annealing process is performed.
  • the pre-annealing process is performed at a furnace temperature of 500-900° C. for less than six hours.
  • RTA rapid thermal annealing
  • the pre-annealing process is performed at 850-1200° C. for less than five minutes.
  • a gate oxide film 43 is formed on the top surface of the semiconductor substrate 40 .
  • a relatively thin gate oxide film 43 a is formed on the top surface of the semiconductor substrate of a portion into which nitrogen ions are implanted
  • a relatively thick gate oxide film 43 b is formed on the top surface of the semiconductor substrate of a portion into which nitrogen ions are not implanted.
  • the oxide film formation process is a process of wet oxidation at a furnace temperature of 700-950° C. by the rapid thermal annealing method, or a process of dry oxidation at a furnace temperature of 850-1200° C. by the same method.
  • the semiconductor substrate 40 on which the gate oxide film 43 is fabricated is annealed.
  • the conditions of the annealing process are as follows. In case of the rapid thermal annealing process, it is performed in a N 2 O gas atmosphere at 850-1200° C. for about less than five minutes. In case of the furnace annealing process, it is performed in a N 2 O gas atmosphere at 800-1200° C. for about less than one hour. During this annealing process, nitrogen atoms (N) in the semiconductor substrate are moved to the interface between the oxide film and the semiconductor substrate to thus increase the nitrogen concentration of the interface portion, and nitrogen atoms (N) in the oxide film go outside to thus decrease the nitrogen concentration of the gate oxide film.
  • FIG. 5 is a graph illustrating the changes in the number of nitrogen atoms in the gate oxide film in both cases of including the annealing process and not including the annealing process after the formation of the gate oxide film. That is, FIG. 5 shows the results of the SIMS (secondary ion mass spectroscopy) analysis after the annealing process.
  • white plots (“ ⁇ ”, “ ⁇ ”, “ ⁇ ”, “ ⁇ ”) show the number of oxygen atoms
  • black plots (“ ⁇ ”, “ ⁇ ”, “ ⁇ ”, “ ⁇ ”, “ ⁇ ””
  • plots “ ⁇ ” and “ ⁇ ” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is not per-formed.
  • the plots “ ⁇ ” and “ ⁇ ” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a N 2 atmosphere at 1050° C. for 30 seconds.
  • the plots “ ⁇ ” and “ ⁇ ” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a NO atmosphere.
  • the plots “ ⁇ ” and “ ⁇ ” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a N 2 O atmosphere.
  • FIG. 5 illustrates the changes in the number of nitrogen atoms according to a sputtering time.
  • the graph of FIG. 5 corresponds to the profile of nitrogen atoms in the oxide film and the semiconductor substrate.
  • a zone in which the number of oxygen atoms is large shows the depth profile of the distribution of concentration of oxygen atoms in the oxide film region
  • C zone in which the number of oxygen atoms is small shows the depth profile of the distribution of concentration of oxygen atoms in the silicon substrate region
  • the middle region (“B” zone) shows the profile of oxygen atoms in the interface portion between the oxide film and the semiconductor substrate.
  • FIG. 5 As illustrated in FIG. 5, as the result of performing annealing in a N 2 O atmosphere at 1050° for 30 seconds by the rapid thermal annealing method, it is shown that the number of nitrogen atoms in the oxide film (“A” zone) is decreased as compared to the case of not performing annealing. This is because the nitrogen atoms are discharged to the outside during the annealing process. In addition, it is shown that the number of nitrogen atoms is slightly increased in the interface portion (“B” zone) between the oxide film and the silicon substrate. This is because nitrogen ions in the semiconductor substrate move toward the interface portion during the annealing process.
  • the annealing is performed in a N 2 O atmosphere so as to improve the characteristics of the semiconductor device.
  • FIG. 6 is a graph illustrating the increase of the amount of leakage current after forming a gate oxide film and performing annealing. As illustrated therein, in case of performing the annealing in a N 2 O atmosphere, it can be known that the amount of leakage current is decreased as compared to the case of not performing the annealing.
  • FIG. 7 is a graph illustrating the characteristics of the oxide film, which shows the amount of electric charge (Qbd) accumulated in the oxide film to the breakdown of the oxide film.
  • the plot “ ⁇ ” shows the case of not performing the annealing
  • the plot “ ⁇ ” shows the case of performing the annealing
  • the plot “ ⁇ ” shows the case of not performing a nitrogen ion implantation.
  • the Qbd after the annealing is larger than the Qbd prior to the annealing, after the nitrogen ion implantation.
  • the concentration of nitrogen in the gate oxide film is decreased, and the concentration of nitrogen in the interface between the gate oxide film and the semiconductor substrate is increased, by additionally including an annealing process after the formation of the gate oxide film, in fabricating multiple gate oxide films using a nitrogen ion implantation.
  • an annealing process after the formation of the gate oxide film, in fabricating multiple gate oxide films using a nitrogen ion implantation.
  • the concentration of nitrogen in the interface between the gate oxide film and the semiconductor substrate is increased, in case of a P-MOS transistor, boron in a gate electrode is prevented from penetrating into the semiconductor substrate, thus making the change in threshold voltage of the transistor and improving the characteristics of the semiconductor device.

Abstract

The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a gate oxide film of a semiconductor device by which semiconductor devices having different electrical characteristics can be implemented in the same chip. The present invention provides a method for fabricating a gate oxide film of a semiconductor device which includes the steps of: forming a screen oxide film on the top surface of a semiconductor substrate; forming an ion implantation mask on parts of the top surface of the screen oxide film; implanting nitrogen ions into the semiconductor substrate using the ion implantation mask; removing the ion implantation mask and the screen oxide film; forming an oxide film on the top surface of the semiconductor substrate; and annealing the semiconductor substrate in a N2O or O3 atmosphere.

Description

  • This application claims the benefit of Korean Application No. 47183/1999, filed in the Republic of Korea on Aug. 16, 2000, which is hereby incorporated by reference. [0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a gate oxide film of a semiconductor device by which semiconductor devices having different electrical characteristics can be implemented in the same chip. [0003]
  • 2. Description of the Background Art [0004]
  • Recently, as the degree of integration of a semiconductor, in particular, a DRAM (dynamic random access memory) increases, it is often the case that a transistor of a memory cell unit and a transistor of a peripheral circuit have a different operating voltage with each other. In other words, the transistor of the memory cell unit fabricated with a fine line width operates at a voltage less than 1.8V, and the transistor of the peripheral circuit operates at a voltage of 3.3V or 5V for matching with exterior system equipment. [0005]
  • Accordingly, as devices having different operating voltages are formed in the same chip, there occurs a problem that a gate oxide film of the transistors formed in the same semiconductor chip must have different thicknesses. [0006]
  • Methods conventionally known as a method for forming a gate electrode having different thicknesses in the same chip will now be described. [0007]
  • First, FIGS. 1A through 1D illustrate a method for fabricating a gate oxide film by a dual step oxidation process. [0008]
  • As illustrated in FIG. 1A, a [0009] semiconductor substrate 10 is prepared.
  • Next, as illustrated in FIG. 1B, a first [0010] gate oxide film 11 is formed on the top surface of the semiconductor substrate 10.
  • Next, as illustrated in FIG. 1C, the first [0011] gate oxide film 11 of a portion on which a relatively thin gate oxide film is to be selectively etched and removed to thereby expose parts of the top surface of the semiconductor substrate 10.
  • Next, as illustrated in FIG. 1D, a second [0012] gate oxide film 12 is formed on the top surface of the first gate oxide film 11 and the top surface of the semiconductor device 10.
  • Besides the above-said method using the dual step oxidation process, there is a method for fabricating a gate oxide film using an ion implantation process. This method will now be described with reference to FIGS. 2A through 2D and FIGS. 3A through 3D. [0013]
  • First, FIGS. 2A through 2D illustrates a method for fabricating a gate oxide film using a nitrogen ion implantation process. [0014]
  • As illustrated in FIG. 2A, a [0015] semiconductor substrate 20 is prepared.
  • Next, as illustrated in FIG. 2B, a [0016] screen oxide film 21 is formed on the top surface of the semiconductor substrate 20. Then, an ion implantation mask 22 is formed on the screen oxide film 21 of a portion on which a relatively thick oxide film is to be formed. Then, nitrogen (N2) ions are implanted into the semiconductor substrate 20 of a portion being not covered with the ion implantation mask 22.
  • Next, as illustrated in FIG. 2C, the [0017] screen oxide film 21 and the ion implantation mask are removed.
  • Next, when a [0018] gate oxide film 23 is formed on the top surface of the semiconductor substrate 20, as illustrated in FIG. 2D, a thin oxide film 23 a is formed on a portion into which nitrogen ions are implanted, because oxidation is restrained, and a relatively thick oxide film 23 b is formed on a portion into which nitrogen ions are not implanted.
  • In addition, a method for fabricating a gate oxide film using a fluoride ion implantation process will now be described with reference to FIGS. 3A through 3D. [0019]
  • First, as illustrated in FIG. 3A, a [0020] semiconductor substrate 30 is prepared.
  • Next, as illustrated in FIG. 3B, a [0021] screen oxide film 31 is formed on the top surface of the semiconductor substrate 30. Next, an ion implantation mask 32 is formed on the top surface of the screen oxide film 31 of a portion on which a relatively thin gate oxide film is to be formed. Then, fluoride ions are implanted into the semiconductor substrate 30 using the ion implantation mask 32.
  • Next, as illustrated in FIG. 3C, the [0022] ion implantation mask 32 and the screen oxide film 31 are removed.
  • Next, as illustrated in FIG. 3D, a [0023] gate oxide film 33 having different thicknesses is formed on the top surface of the semiconductor substrate 30 by oxidation of the semiconductor substrate 30. That is, a thick gate oxide film is formed on the top surface of the semiconductor of a portion into which fluoride ions are implanted, and a thin gate oxide film is formed on a portion into which fluoride ions are not implanted.
  • However, the above-described conventional methods for fabricating a gate oxide film has the following problems. First, the method for fabricating a gate oxide film by the dual step oxidation process has a complicated procedure, and a peripheral portion of a fabricated, thick gate oxide film becomes thinner and a breakdown is easily occurred on a thinned portion. [0024]
  • Second, in case of the fluoride ion implantation process, since a large amount of fluoride ions must be implanted in order to make the thickness of a gate oxide film different according to its portion, the semiconductor substrate is largely damaged to thus increase the amount of leakage current. [0025]
  • Third, the nitrogen implantation process is disadvantageous in that, in case of forming a gate oxide film on the top surface of the semiconductor substrate into which nitrogen ions are implanted, the gate oxide film is degraded, although it is advantageous in that a smaller amount of ions can be implanted as to compared to the fluoride ion implantation process, which rather decreases the amount of leakage current. [0026]
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention provides a method for fabricating a gate oxide film of a semiconductor device having a small leakage current amount and a high reliability by reducing the concentration of nitrogen in the gate oxide film when a gate oxide film having different thicknesses according to its portion is fabricated on the top surface of a semiconductor substrate using a nitrogen ion implantation process. [0027]
  • A method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the steps of: forming a screen oxide film on the top surface of a semiconductor substrate; forming an ion implantation mask on parts of the top surface of the screen oxide film; implanting nitrogen ions into the semiconductor substrate using the ion implantation mask; removing the ion implantation mask and the screen oxide film; forming an oxide film on the top surface of the semiconductor substrate; and annealing the semiconductor substrate. [0028]
  • There is provided a method for fabricating a gate oxide film of a semiconductor device according to the present invention which further includes a pre-annealing step after the ion implantation step. [0029]
  • A method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the pre-annealing step by a process of annealing at 500-900° C. by a furnace annealing method. [0030]
  • In a further aspect of the invention, there is provided a method for fabricating a gate oxide film of a semiconductor device wherein the pre-annealing step is a process of annealing at 850-1200° C. by a rapid thermal annealing method. [0031]
  • In another aspect of the invention, there is provided a method for fabricating a gate oxide film of a semiconductor device wherein the oxide film formation step being a method for thermal oxidation at a furnace of 700-950° C. [0032]
  • A method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the oxide film formation step being a method for thermal oxidation at 850-1200° C. at the rapid thermal annealing method. [0033]
  • A method for fabricating a gate oxide film of a semiconductor device according to the present invention includes the annealing step being performed by means of the rapid thermal annealing method in a N[0034] 2O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
  • The annealing step can also be performed by means of the thermal annealing method in an O[0035] 3 atmosphere at a temperature of 400-1200° C. for about five minutes.
  • The annealing step can also be performed by means of the furnace annealing method in a N[0036] 2O atmosphere at a temperature of 850-1200° C. for about one hour.
  • In another aspect of the invention, there is provided a method for fabricating a gate oxide film of a semiconductor device according to the present invention wherein the annealing step is performed by means of the rapid thermal annealing method in a N[0037] 2O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
  • Additional advantages, aspects and features of the invention will become more apparent from the description which follows.[0038]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: [0039]
  • FIGS. 1A through 1D are a process chart illustrating one example of a method for fabricating a gate oxide film according to the conventional art; [0040]
  • FIGS. 2A through 2D are a process chart illustrating another example of a method for fabricating a gate oxide film according to the conventional art; [0041]
  • FIGS. 3A through 3D are a process chart illustrating still another example of a method for fabricating a gate oxide film according to the conventional art; [0042]
  • FIGS. 4A through 4D are a process chart illustrating a method for fabricating a gate oxide film according to the present invention; [0043]
  • FIG. 5 is a graph illustrating the results of the SIMS analysis after annealing; [0044]
  • FIG. 6 is a graph illustrating the changes in leakage current after annealing of a gate oxide film; and [0045]
  • FIG. 7 is a graph illustrating the characteristics of an oxide film, e.g., a graph illustrating the amount of electric charge accumulated in the oxide film to the breakdown of the oxide film.[0046]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A first embodiment of the present invention will now be described with reference to the accompanying drawings. [0047]
  • First, as illustrated in FIGS. 4A and 4B, a [0048] screen oxide film 41 is formed on the top surface of a semiconductor device at a thickness of less than 200 Å.
  • Next, as illustrated in FIG. 4B, an [0049] ion implantation mask 42 is formed on the top surface of the screen oxide film 41. The ion implantation mask 42 is formed only on the top surface of a portion on which a relatively thick gate oxide film is to be formed. Then, nitrogen ions are implanted into the semiconductor substrate 40. At this time, the ion implantation process is performed with the implantation amount of nitrogen ions ranging from 5×1013 cm2 to 5×1011 cm2 and the ion implantation energy of 5-50 KeV.
  • Next, in order to prevent the damage to the semiconductor substrate occurred due to the ion implantation process and move the distribution of nitrogen (N) atoms in the vicinity of the [0050] screen oxide film 41, a pre-annealing process is performed. At this time, in case of furnace annealing, the pre-annealing process is performed at a furnace temperature of 500-900° C. for less than six hours. Meanwhile, in case of rapid thermal annealing (RTA), the pre-annealing process is performed at 850-1200° C. for less than five minutes.
  • Next, as illustrated in FIG. 4C, the [0051] screen oxide film 41 and the ion implantation mask 42 are removed.
  • Next, as illustrated in FIG. 4D, a [0052] gate oxide film 43 is formed on the top surface of the semiconductor substrate 40. At this time, a relatively thin gate oxide film 43 a is formed on the top surface of the semiconductor substrate of a portion into which nitrogen ions are implanted, and a relatively thick gate oxide film 43 b is formed on the top surface of the semiconductor substrate of a portion into which nitrogen ions are not implanted. In addition, the oxide film formation process is a process of wet oxidation at a furnace temperature of 700-950° C. by the rapid thermal annealing method, or a process of dry oxidation at a furnace temperature of 850-1200° C. by the same method.
  • Next, as illustrated in FIG. 4D, the [0053] semiconductor substrate 40 on which the gate oxide film 43 is fabricated is annealed. The conditions of the annealing process are as follows. In case of the rapid thermal annealing process, it is performed in a N2O gas atmosphere at 850-1200° C. for about less than five minutes. In case of the furnace annealing process, it is performed in a N2O gas atmosphere at 800-1200° C. for about less than one hour. During this annealing process, nitrogen atoms (N) in the semiconductor substrate are moved to the interface between the oxide film and the semiconductor substrate to thus increase the nitrogen concentration of the interface portion, and nitrogen atoms (N) in the oxide film go outside to thus decrease the nitrogen concentration of the gate oxide film.
  • FIG. 5 is a graph illustrating the changes in the number of nitrogen atoms in the gate oxide film in both cases of including the annealing process and not including the annealing process after the formation of the gate oxide film. That is, FIG. 5 shows the results of the SIMS (secondary ion mass spectroscopy) analysis after the annealing process. In FIG. 5, white plots (“□”, “∘”, “Δ”, “∇”) show the number of oxygen atoms, while black plots (“▪”, “”, “▴”, “▾”) show the number of nitrogen atoms. In particular, plots “□” and “▪” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is not per-formed. The plots “∘” and “” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a N[0054] 2 atmosphere at 1050° C. for 30 seconds. The plots “Δ” and “▴” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a NO atmosphere. The plots “∇” and “▾” show the number of oxygen atoms and the number of nitrogen atoms, respectively, when the annealing is performed in a N2O atmosphere.
  • FIG. 5 illustrates the changes in the number of nitrogen atoms according to a sputtering time. In addition, the graph of FIG. 5 corresponds to the profile of nitrogen atoms in the oxide film and the semiconductor substrate. In FIG. 5, it is assumed that a region (“A” zone) in which the number of oxygen atoms is large shows the depth profile of the distribution of concentration of oxygen atoms in the oxide film region, a region (“C” zone) in which the number of oxygen atoms is small shows the depth profile of the distribution of concentration of oxygen atoms in the silicon substrate region, and the middle region (“B” zone) shows the profile of oxygen atoms in the interface portion between the oxide film and the semiconductor substrate. [0055]
  • As illustrated in FIG. 5, as the result of performing annealing in a N[0056] 2O atmosphere at 1050° for 30 seconds by the rapid thermal annealing method, it is shown that the number of nitrogen atoms in the oxide film (“A” zone) is decreased as compared to the case of not performing annealing. This is because the nitrogen atoms are discharged to the outside during the annealing process. In addition, it is shown that the number of nitrogen atoms is slightly increased in the interface portion (“B” zone) between the oxide film and the silicon substrate. This is because nitrogen ions in the semiconductor substrate move toward the interface portion during the annealing process.
  • Meanwhile, in case of performing annealing in a NO atmosphere, there is almost no change in the profile of nitrogen atoms in the oxide film as compared to prior to the annealing, and the number of nitrogen atoms in the interface between the semiconductor substrate and the oxide film is increased. [0057]
  • On the contrary, in case of performing annealing in a N[0058] 2 atmosphere, there is no change in the profile of nitrogen atoms in the oxide film.
  • Thus, it is most appropriate that the annealing is performed in a N[0059] 2O atmosphere so as to improve the characteristics of the semiconductor device.
  • Meanwhile, FIG. 6 is a graph illustrating the increase of the amount of leakage current after forming a gate oxide film and performing annealing. As illustrated therein, in case of performing the annealing in a N[0060] 2O atmosphere, it can be known that the amount of leakage current is decreased as compared to the case of not performing the annealing.
  • In addition, FIG. 7 is a graph illustrating the characteristics of the oxide film, which shows the amount of electric charge (Qbd) accumulated in the oxide film to the breakdown of the oxide film. In FIG. 7, the plot “▪” shows the case of not performing the annealing, the plot “” shows the case of performing the annealing, and the plot “▴” shows the case of not performing a nitrogen ion implantation. [0061]
  • As illustrated therein, it can be known that the Qbd after the annealing is larger than the Qbd prior to the annealing, after the nitrogen ion implantation. [0062]
  • Therefore, when the annealing is performed in a N[0063] 2O or O3 atmosphere after the nitrogen ion implantation, the degree of degradation of the oxide film becomes lower, and the reliability of the oxide film become higher, as compared to the case of not performing the annealing.
  • According to the present invention, the concentration of nitrogen in the gate oxide film is decreased, and the concentration of nitrogen in the interface between the gate oxide film and the semiconductor substrate is increased, by additionally including an annealing process after the formation of the gate oxide film, in fabricating multiple gate oxide films using a nitrogen ion implantation. As the result, there is an effect of decreasing the degradation of the gate oxide film and the amount of leakage current for thereby increasing the reliability of the gate oxide film. In addition, since the concentration of nitrogen in the interface between the gate oxide film and the semiconductor substrate is increased, in case of a P-MOS transistor, boron in a gate electrode is prevented from penetrating into the semiconductor substrate, thus making the change in threshold voltage of the transistor and improving the characteristics of the semiconductor device. [0064]
  • As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims. What is claimed is:[0065]

Claims (15)

1. A method for fabricating a gate oxide film of a semiconductor device, comprising the steps of:
forming a screen oxide film on a top surface of a semiconductor substrate;
forming an ion implantation mask on parts of a top surface of the screen oxide film;
implanting nitrogen ions into the semiconductor substrate using the ion implantation mask;
removing the ion implantation mask and the screen oxide film;
forming an oxide film on the top surface of the semiconductor substrate; and
annealing the semiconductor substrate.
2. The method according to claim 1, wherein the method further comprises a pre-annealing step after the ion implantation step.
3. The method according to claim 2, wherein the pre-annealing step is a process of annealing at 500-900° C. by a furnace annealing method.
4. The method according to claim 2, wherein the pre-annealing step is a process of annealing at 850-1200° C. by a rapid thermal annealing method.
5. The method according to claim 1, wherein the oxide film formation step is a method for thermal oxidation at a furnace of 700-950°C.
6. The method according to claim 1, wherein the oxide film formation step is a method for thermal oxidation at 850-1200° C. at a rapid thermal annealing method.
7. The method according to claim 1, wherein the annealing step is performed by means of a rapid thermal annealing method in a N2O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
8. The method according to claim 1, wherein the annealing step is performed by means of a thermal annealing method in an O3 atmosphere at a temperature of 400-1200° C. for about five minutes.
9. The method according to claim 1, wherein the annealing step is performed by means of a furnace annealing method in a N2O atmosphere at a temperature of 850-1200° C. for about one hour.
10. The method according to claim 3, wherein the annealing step is performed by means of a rapid thermal annealing method in a N2O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
11. The method according to claim 3, wherein the annealing step is performed by means of a rapid thermal annealing method in an O3 atmosphere at a temperature of 400-1200° C. for about five minutes.
12. The method according to claim 4, wherein the annealing step is performed by means of a furnace annealing method in a N2O atmosphere at a temperature of 850-1200° C. for about one hour.
13. The method according to claim 4, wherein the annealing step is performed by means of the rapid thermal annealing method in a N2O atmosphere at a temperature of 900-1200° C. for about less than five minutes.
14. The method according to claim 4, wherein the annealing step is performed by means of a rapid thermal annealing method in an O3 atmosphere at a temperature of 400-1200° C. for about five minutes.
15. The method according to claim 4, wherein the annealing step is performed by means of a furnace annealing method in a N2O atmosphere at a temperature of 850-1200° C. for about one hour.
US09/770,672 2000-08-16 2001-01-29 Method for fabricating gate oxide film of semiconductor device Expired - Lifetime US6380102B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2000-0047183A KR100367740B1 (en) 2000-08-16 2000-08-16 Method for fabricating gate oxide film
KR47183/2000 2000-08-16
KR2000-47183 2000-08-16

Publications (2)

Publication Number Publication Date
US20020022376A1 true US20020022376A1 (en) 2002-02-21
US6380102B1 US6380102B1 (en) 2002-04-30

Family

ID=19683280

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/770,672 Expired - Lifetime US6380102B1 (en) 2000-08-16 2001-01-29 Method for fabricating gate oxide film of semiconductor device

Country Status (2)

Country Link
US (1) US6380102B1 (en)
KR (1) KR100367740B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849508B2 (en) * 2001-06-07 2005-02-01 Amberwave Systems Corporation Method of forming multiple gate insulators on a strained semiconductor heterostructure
US20050142729A1 (en) * 2003-12-30 2005-06-30 Hyunsoo Shin Methods for forming a field effect transistor
US20050164444A1 (en) * 2004-01-22 2005-07-28 International Business Machines Corporation Selective nitridation of gate oxides
US20090081859A1 (en) * 2007-09-20 2009-03-26 Macronix International Co., Ltd. Metallization process
US20110165758A1 (en) * 2008-08-06 2011-07-07 Konstantin Bourdelle Method for making a structure comprising a step for implanting ions in order to stabilize the adhesive bonding interface

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531410B2 (en) * 2001-02-27 2003-03-11 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process
US6569781B1 (en) * 2002-01-22 2003-05-27 International Business Machines Corporation Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation
KR100412143B1 (en) * 2002-05-07 2003-12-31 주식회사 하이닉스반도체 Method of manufacturing semiconductor device applying a triple gate oxide
US6759302B1 (en) * 2002-07-30 2004-07-06 Taiwan Semiconductor Manufacturing Company Method of generating multiple oxides by plasma nitridation on oxide
JP3944455B2 (en) * 2003-01-31 2007-07-11 松下電器産業株式会社 Semiconductor device and manufacturing method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595922A (en) * 1994-10-28 1997-01-21 Texas Instruments Process for thickening selective gate oxide regions
US6110842A (en) * 1996-06-07 2000-08-29 Texas Instruments Incorporated Method of forming multiple gate oxide thicknesses using high density plasma nitridation
US6080682A (en) * 1997-12-18 2000-06-27 Advanced Micro Devices, Inc. Methodology for achieving dual gate oxide thicknesses
JPH11330262A (en) * 1998-05-15 1999-11-30 Mitsubishi Electric Corp Manufacture of semiconductor device
JP2000003965A (en) * 1998-06-15 2000-01-07 Mitsubishi Electric Corp Semiconductor device and its manufacture
US6147008A (en) * 1999-11-19 2000-11-14 Chartered Semiconductor Manufacturing Ltd. Creation of multiple gate oxide with high thickness ratio in flash memory process
US6258673B1 (en) * 1999-12-22 2001-07-10 International Business Machines Corporation Multiple thickness of gate oxide
US6261972B1 (en) * 2000-11-06 2001-07-17 Infineon Technologies Ag Dual gate oxide process for uniform oxide thickness

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7172935B2 (en) 2001-06-07 2007-02-06 Amberwave Systems Corporation Method of forming multiple gate insulators on a strained semiconductor heterostructure
US20050098774A1 (en) * 2001-06-07 2005-05-12 Amberwave Systems Corporation Method of forming multiple gate insulators on a strained semiconductor heterostructure
US6849508B2 (en) * 2001-06-07 2005-02-01 Amberwave Systems Corporation Method of forming multiple gate insulators on a strained semiconductor heterostructure
US20050142729A1 (en) * 2003-12-30 2005-06-30 Hyunsoo Shin Methods for forming a field effect transistor
US7402484B2 (en) * 2003-12-30 2008-07-22 Dongbu Electronics Co., Ltd. Methods for forming a field effect transistor
US20050164444A1 (en) * 2004-01-22 2005-07-28 International Business Machines Corporation Selective nitridation of gate oxides
US20060281265A1 (en) * 2004-01-22 2006-12-14 International Business Machines Corporation Selective nitridation of gate oxides
US7138691B2 (en) 2004-01-22 2006-11-21 International Business Machines Corporation Selective nitridation of gate oxides
US7759260B2 (en) 2004-01-22 2010-07-20 International Business Machines Corporation Selective nitridation of gate oxides
US20100187614A1 (en) * 2004-01-22 2010-07-29 International Business Machines Corporation Selective nitridation of gate oxides
US20090081859A1 (en) * 2007-09-20 2009-03-26 Macronix International Co., Ltd. Metallization process
TWI393187B (en) * 2007-09-20 2013-04-11 Macronix Int Co Ltd Metallization process
US20110165758A1 (en) * 2008-08-06 2011-07-07 Konstantin Bourdelle Method for making a structure comprising a step for implanting ions in order to stabilize the adhesive bonding interface

Also Published As

Publication number Publication date
US6380102B1 (en) 2002-04-30
KR100367740B1 (en) 2003-01-10
KR20020014095A (en) 2002-02-25

Similar Documents

Publication Publication Date Title
US20030092238A1 (en) Method of forming insulating film and method of producing semiconductor device
US20080296704A1 (en) Semiconductor device and manufacturing method thereof
US7208360B2 (en) Semiconductor device and method of manufacturing the same
US20060292799A1 (en) Memory embedded semiconductor device and method for fabricating the same
US6380102B1 (en) Method for fabricating gate oxide film of semiconductor device
US6855994B1 (en) Multiple-thickness gate oxide formed by oxygen implantation
US6653192B1 (en) Method of manufacturing semiconductor devices using nitrification
US6501125B2 (en) Semiconductor device and manufacturing method thereof
US6977205B2 (en) Method for manufacturing SOI LOCOS MOSFET with metal oxide film or impurity-implanted field oxide
US5407839A (en) MOS manufacturing process having reduced gate insulator defects
EP1308995A2 (en) Semiconductor Device Having A Dielectric Layer With A Uniform Nitrogen Profile
US6060369A (en) Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET
US5970350A (en) Semiconductor device having a thin gate oxide and method of manufacture thereof
US6127248A (en) Fabrication method for semiconductor device
US6103582A (en) Method to suppress boron penetration in P+ mosfets
JP3453764B2 (en) Method for manufacturing semiconductor device
US7081419B2 (en) Gate dielectric structure for reducing boron penetration and current leakage
US6455381B1 (en) Method of manufacturing a semiconductor device having a trench isolation structure
JP2812217B2 (en) Method for manufacturing semiconductor device
US6977207B2 (en) Method for fabricating dual-gate semiconductor device
EP0887842A1 (en) Field effect devices with improved gate insulator and method of manufacturing the same
US20030008466A1 (en) Semiconductor device and method of fabricating the same
JPH06350079A (en) Manufacture of semiconductor device
JP2005191145A (en) Semiconductor device and its manufacturing method
JP2831805B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OH, JONG-HYUK;REEL/FRAME:011488/0378

Effective date: 20010109

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12