US20020008989A1 - MRAM memory cell - Google Patents
MRAM memory cell Download PDFInfo
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- US20020008989A1 US20020008989A1 US09/907,778 US90777801A US2002008989A1 US 20020008989 A1 US20020008989 A1 US 20020008989A1 US 90777801 A US90777801 A US 90777801A US 2002008989 A1 US2002008989 A1 US 2002008989A1
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- memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
Definitions
- the present invention relates to an MRAM (Magneto-Resistive Random Access Memory) memory cell that includes a magnetoresistive resistor and a switching transistor.
- the magnetoresistive resistor is located between two interconnects that cross essentially perpendicularly, one interconnect of which runs in a topmost metallization plane.
- the source or drain, gate, and drain or source of the switching transistor are connected by interconnects in a zeroth, first, and second metallization plane, respectively.
- the source or drain is connected to a bit line of a memory cell array, which bit line runs in the zeroth metallization plane.
- the gate is connected via a word line and a stitch contact to the interconnect of the first metallization plane of the memory cell array.
- MRAM memory cells are ideally embodied without any switching elements, that is to say purely as a resistor matrix in which the individual memory cells are embodied at crossover points between word lines and bit lines.
- each memory cell includes a layer made of a hard-magnetic material, an insulating layer made, for example, of a tunnel oxide, and a soft-magnetic material.
- An MRAM constructed in this way is distinguished by an extremely simple structure.
- it has the disadvantage that non-negligible parasitic currents flow away in the individual memory cell arrays via the memory cells that are not addressed, specifically in the event of reading.
- FIG. 4 illustrates a conventional MRAM cell, in which a magnetoresistive or TMR element 1 is configured between two metallization planes M 3 and M 2 .
- the metallization plane M 2 is connected to the source or the drain of a MOS field-effect switching transistor 2 which is provided in a semiconductor body and whose drain or source is connected to a bit line BL in a metallization plane M 0 .
- a gate conductor GC is connected to a word line WL, this preferably being done by means of a so-called stitch contact 3 to the metallization plane M 1 .
- the metallization planes M 0 to M 3 are configured in order above the gate conductor GC, with the result that, proceeding from the semiconductor body, the gate conductor and the metallization planes form a row GC, M 0 , M 1 , M 2 and M 3 .
- the metallization plane M 1 serves for reducing the resistance of the word line WL, which is in each case connected to the interconnect in the metallization plane M 1 via the individual stitch contacts 3 .
- the gate conductor GC of the switching transistor 2 is preferably made of doped polycrystalline silicon and extends as far as the stitch contact 3 .
- a current of the order of magnitude of about 1 to 2 mA is required to be provided in the interconnects of the metallization planes M 2 and M 3 . If these currents generate a unidirectional magnetic field in the magnetoresistive resistor 1 , then this magnetic field determines the direction of polarization in the soft-magnetic layer, which may then be parallel or antiparallel with respect to the direction of polarization in the hard-magnetic layer. A high value of resistance is present in the case of antiparallel polarization, while parallel polarization leads to a lower value of resistance. During such a write operation, the voltage across the magnetoresistive resistor must not exceed about 0.5 V, since otherwise the insulating layer, and with it the memory cell, would be destroyed.
- a voltage of about 0.5 V is applied to the interconnect of the metallization plane M 3 and the current flowing through the magnetoresistive resistor 1 is measured via the switching transistor 2 , which is then in the on state.
- This current depending on the value of resistance and thus the directions of magnetization in the soft-magnetic layer and in the hard-magnetic layer—can assume a high or low value.
- This measurement result is obtained on the bit line BL in the metallization plane M 0 .
- the conventional MRAM memory cell illustrated in FIG. 4 requires a total of four metallization planes for the bit line BL (M 0 ), the word line and word line stitch (M 1 ) and the two interconnects which cross and between which, at their crossover point, the magnetoresistive resistor 1 is located (M 2 and M 3 ).
- an MRAM memory cell that includes a zeroth metallization plane having an interconnect, a first metallization plane having an interconnect, and a second metallization plane having an interconnect.
- the second metallization plane forms a topmost metallization plane.
- the interconnect of the second metallization plane crosses the interconnect of the first metallization plane essentially perpendicularly.
- the MRAM memory cell also includes a bit line running in the zeroth metallization plane, a word line having a stitch contact connected to the interconnect of the first metalization plane, and a switching transistor having a gate connected to the interconnect of the first metalization plane by the word line and the stitch contact.
- the switching transistor has a source-drain path connected between the interconnect of the zeroth metallization plane and the interconnect of the second metallization plane.
- the source-drain path is connected to the bit line.
- the MRAM memory cell also includes a magnetoresistive resistor extending between the interconnect of the first metallization plane and the interconnect of the second metallization plane such that the interconnect of the first metallization plane is connected to the stitch contact of the word line and such that the magnetoresistive resistor can perform a dual function of a word line stitch and of a write line for the magnetoresistive resistor.
- the stitch contact connects the gate of the switching transistor to the interconnect in the first metallization plane.
- a level shifter is provided for the gate of the switching transistor and the level shifter is located near the stitch contact.
- the level shifter is provided between the gate of the switching transistor and the stitch contact.
- the objects are achieved in the inventive MRAM memory cell by virtue of the fact that the topmost metallization plane is the second metallization plane and the magnetoresistive resistor extends between the interconnects of the first and of the second metallization planes with the result that the interconnect of the first metallization plane is connected to the stitch contact of the word line and the magnetoresistive resistor and can thus fulfill a dual function of a word line stitch and of a write line for the magnetoresistive resistor.
- the inventive MRAM memory cell is initially based on the insight that hitherto (cf. FIG. 4) the metallization plane M 2 is inherently utilized only during writing, but not during the reading of the magnetoresistive resistor 1 or the memory cell thereof.
- the magnetoresistive resistor 1 is relocated between the second metallization plane—serving as the upper metallization plane—and the first metallization plane.
- level shifter BOOST circuit
- This level shifter is preferably configured in the respective stitch regions via which the gate conductors and the word lines are connected to the interconnect of the first metallization plane.
- the inventive MRAM memory cell now only requires three metallization planes, which constitutes a significant simplification. This simplification far outweighs the outlay required for the level shifter.
- the interconnect which runs in the first metallization plane and serves for “stitching” the word line is at the same time also used as the write line for the magnetoresistive resistor.
- the level shifter provided in the stitch region ensures that the critical voltage exceeding 0.5 V is not reached across the magnetoresistive resistor, but that the switching transistors can nevertheless readily be turned on.
- FIG. 1 shows a schematic illustration of a first exemplary embodiment of an MRAM memory cell
- FIG. 2 shows a plan view of the arrangement of a plurality of MRAM memory cells and the metallization planes of the cells;
- FIG. 3 shows a schematic side view of the first metallization plane in the MRAM memory cell
- FIG. 4 shows a schematic illustration of a prior art MRAM memory cell.
- FIG. 1 there is shown a magnetoresistive resistor (TMR element) 1 that is between an interconnect of an upper metallization plane M 2 and an interconnect of a central metallization plane M 1 .
- the central metallization plane M 1 is connected via a stitch contact 3 and a level shifter B to a gate conductor GC of a switching transistor 2 , whose source-drain path is located between the interconnect of the metallization plane M 2 and an interconnect—forming a bit line BL—in a lower metallization plane M 0 .
- the level shifter B is of customary design and constitutes a BOOST circuit.
- the gate conductor GC is preferably fabricated from doped polycrystalline silicon. This gate conductor GC forms a word line WL, which is connected to the interconnect of the metallization plane M 1 via the stitch contact 3 .
- FIG. 2 shows, in a schematic plan view, how the interconnects in metallization planes M 0 , M 1 , M 2 and the gate conductor GC may be routed with respect to one another.
- the interconnects of the metallization planes M 1 and M 2 at whose crossover points the magnetoresistive resistors 1 or TMR elements are formed, run perpendicularly with respect to one another.
- the course of the interconnect of the metallization plane M 0 which forms the bit line BL, is preferably configured perpendicularly to that of the interconnect of the metallization plane M 1 and the gate conductor GC, which represents the word line.
- FIG. 3 schematically shows, in a side view, the interconnect of the metallization plane M 1 from which stitch contacts 3 are routed perpendicularly downward and are connected to the gate conductors GC of the respective switching transistors 2 via level shifters B located in the region of the stitch contacts 3 .
- a current of about 1 to 2 mA is impressed between the interconnects of the metallization planes M 1 and M 2 .
- the voltage present in this case should not exceed about 0.5 V since otherwise the magnetoresistive resistor 1 or the TMR element might be destroyed.
- the resistance of the magnetoresistive resistor 1 is defined by this write operation.
- a voltage of about 0.5 V is applied to the interconnect of the metallization plane M 2 .
- the resistance of the magnetoresistive resistor 1 is then measured via the interconnect of the metallization plane M 1 . Since the voltage drop across the magnetoresistive resistor 1 must not exceed 0.5 V in this case, voltage amplification must be performed for the purpose of driving the switching transistor 2 , this being done by the level shifter B which is inserted between the gate conductor GC of the switching transistor 2 and the stitch contact 3 in the region thereof. The level shifter B thus ensures that the critical voltage is not reached across the magnetoresistive resistor 1 , but that the switching transistor 2 can nevertheless be turned on.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates to an MRAM (Magneto-Resistive Random Access Memory) memory cell that includes a magnetoresistive resistor and a switching transistor. The magnetoresistive resistor is located between two interconnects that cross essentially perpendicularly, one interconnect of which runs in a topmost metallization plane. The source or drain, gate, and drain or source of the switching transistor are connected by interconnects in a zeroth, first, and second metallization plane, respectively. The source or drain is connected to a bit line of a memory cell array, which bit line runs in the zeroth metallization plane. The gate is connected via a word line and a stitch contact to the interconnect of the first metallization plane of the memory cell array.
- MRAM memory cells are ideally embodied without any switching elements, that is to say purely as a resistor matrix in which the individual memory cells are embodied at crossover points between word lines and bit lines. In this case each memory cell includes a layer made of a hard-magnetic material, an insulating layer made, for example, of a tunnel oxide, and a soft-magnetic material. An MRAM constructed in this way is distinguished by an extremely simple structure. However, it has the disadvantage that non-negligible parasitic currents flow away in the individual memory cell arrays via the memory cells that are not addressed, specifically in the event of reading.
- For this reason, for MRAMs, structures are currently being proposed, inter alia, which are based on a DRAM (Dynamic Random Access Memory) and in which switching or selection elements, such as transistors and diodes for example, are employed.
- FIG. 4 illustrates a conventional MRAM cell, in which a magnetoresistive or
TMR element 1 is configured between two metallization planes M3 and M2. The metallization plane M2 is connected to the source or the drain of a MOS field-effect switching transistor 2 which is provided in a semiconductor body and whose drain or source is connected to a bit line BL in a metallization plane M0. A gate conductor GC is connected to a word line WL, this preferably being done by means of a so-calledstitch contact 3 to the metallization plane M1. In this case, the metallization planes M0 to M3 are configured in order above the gate conductor GC, with the result that, proceeding from the semiconductor body, the gate conductor and the metallization planes form a row GC, M0, M1, M2 and M3. - In an MRAM memory cell constructed in this way, the metallization plane M1 serves for reducing the resistance of the word line WL, which is in each case connected to the interconnect in the metallization plane M1 via the
individual stitch contacts 3. The gate conductor GC of theswitching transistor 2 is preferably made of doped polycrystalline silicon and extends as far as thestitch contact 3. - In order to write to the conventional memory cell shown in FIG. 4, a current of the order of magnitude of about 1 to 2 mA is required to be provided in the interconnects of the metallization planes M2 and M3. If these currents generate a unidirectional magnetic field in the
magnetoresistive resistor 1, then this magnetic field determines the direction of polarization in the soft-magnetic layer, which may then be parallel or antiparallel with respect to the direction of polarization in the hard-magnetic layer. A high value of resistance is present in the case of antiparallel polarization, while parallel polarization leads to a lower value of resistance. During such a write operation, the voltage across the magnetoresistive resistor must not exceed about 0.5 V, since otherwise the insulating layer, and with it the memory cell, would be destroyed. - In order to read from the memory cell, a voltage of about 0.5 V is applied to the interconnect of the metallization plane M3 and the current flowing through the
magnetoresistive resistor 1 is measured via theswitching transistor 2, which is then in the on state. This current—depending on the value of resistance and thus the directions of magnetization in the soft-magnetic layer and in the hard-magnetic layer—can assume a high or low value. This measurement result is obtained on the bit line BL in the metallization plane M0. - The conventional MRAM memory cell illustrated in FIG. 4 requires a total of four metallization planes for the bit line BL (M0), the word line and word line stitch (M1) and the two interconnects which cross and between which, at their crossover point, the
magnetoresistive resistor 1 is located (M2 and M3). - It is accordingly an object of the invention to provide an MRAM memory cell which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide an MRAM memory cell which manages with fewer metallization planes and is thus structured significantly more simply than the existing MRAM memory cell.
- With the foregoing and other objects in view there is provided, in accordance with the invention an MRAM memory cell that includes a zeroth metallization plane having an interconnect, a first metallization plane having an interconnect, and a second metallization plane having an interconnect. The second metallization plane forms a topmost metallization plane. The interconnect of the second metallization plane crosses the interconnect of the first metallization plane essentially perpendicularly. The MRAM memory cell also includes a bit line running in the zeroth metallization plane, a word line having a stitch contact connected to the interconnect of the first metalization plane, and a switching transistor having a gate connected to the interconnect of the first metalization plane by the word line and the stitch contact. The switching transistor has a source-drain path connected between the interconnect of the zeroth metallization plane and the interconnect of the second metallization plane. The source-drain path is connected to the bit line. The MRAM memory cell also includes a magnetoresistive resistor extending between the interconnect of the first metallization plane and the interconnect of the second metallization plane such that the interconnect of the first metallization plane is connected to the stitch contact of the word line and such that the magnetoresistive resistor can perform a dual function of a word line stitch and of a write line for the magnetoresistive resistor.
- In accordance with an added feature of the invention, the stitch contact connects the gate of the switching transistor to the interconnect in the first metallization plane.
- In accordance with an additional feature of the invention, a level shifter is provided for the gate of the switching transistor and the level shifter is located near the stitch contact.
- In accordance with another feature of the invention, the level shifter is provided between the gate of the switching transistor and the stitch contact.
- In the case of an MRAM memory cell of the type mentioned in the introduction, the objects are achieved in the inventive MRAM memory cell by virtue of the fact that the topmost metallization plane is the second metallization plane and the magnetoresistive resistor extends between the interconnects of the first and of the second metallization planes with the result that the interconnect of the first metallization plane is connected to the stitch contact of the word line and the magnetoresistive resistor and can thus fulfill a dual function of a word line stitch and of a write line for the magnetoresistive resistor.
- The inventive MRAM memory cell is initially based on the insight that hitherto (cf. FIG. 4) the metallization plane M2 is inherently utilized only during writing, but not during the reading of the
magnetoresistive resistor 1 or the memory cell thereof. In order, then, to obviate the metallization plane M2 which is required only during writing but not during reading, in the inventive MRAM memory cell, themagnetoresistive resistor 1 is relocated between the second metallization plane—serving as the upper metallization plane—and the first metallization plane. However, since the voltages are only permitted to reach about 0.5 V in the interconnects of the first metallization plane, in order to avoid destruction of the memory cell, it is necessary to provide a level shifter (BOOST circuit) for driving the selection transistor. This level shifter is preferably configured in the respective stitch regions via which the gate conductors and the word lines are connected to the interconnect of the first metallization plane. - As a result, instead of four metallization planes, the inventive MRAM memory cell now only requires three metallization planes, which constitutes a significant simplification. This simplification far outweighs the outlay required for the level shifter.
- What is essential to the MRAM memory cell according to the invention, then, is that the interconnect which runs in the first metallization plane and serves for “stitching” the word line is at the same time also used as the write line for the magnetoresistive resistor. The level shifter provided in the stitch region ensures that the critical voltage exceeding 0.5 V is not reached across the magnetoresistive resistor, but that the switching transistors can nevertheless readily be turned on.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a MRAM memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 shows a schematic illustration of a first exemplary embodiment of an MRAM memory cell;
- FIG. 2 shows a plan view of the arrangement of a plurality of MRAM memory cells and the metallization planes of the cells;
- FIG. 3 shows a schematic side view of the first metallization plane in the MRAM memory cell; and
- FIG. 4 shows a schematic illustration of a prior art MRAM memory cell.
- Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a magnetoresistive resistor (TMR element)1 that is between an interconnect of an upper metallization plane M2 and an interconnect of a central metallization plane M1. The central metallization plane M1 is connected via a
stitch contact 3 and a level shifter B to a gate conductor GC of aswitching transistor 2, whose source-drain path is located between the interconnect of the metallization plane M2 and an interconnect—forming a bit line BL—in a lower metallization plane M0. The level shifter B is of customary design and constitutes a BOOST circuit. As in the conventional MRAM memory cell, the gate conductor GC is preferably fabricated from doped polycrystalline silicon. This gate conductor GC forms a word line WL, which is connected to the interconnect of the metallization plane M1 via thestitch contact 3. - FIG. 2 shows, in a schematic plan view, how the interconnects in metallization planes M0, M1, M2 and the gate conductor GC may be routed with respect to one another. What is essential in this case is that the interconnects of the metallization planes M1 and M2, at whose crossover points the
magnetoresistive resistors 1 or TMR elements are formed, run perpendicularly with respect to one another. The course of the interconnect of the metallization plane M0, which forms the bit line BL, is preferably configured perpendicularly to that of the interconnect of the metallization plane M1 and the gate conductor GC, which represents the word line. - FIG. 3 schematically shows, in a side view, the interconnect of the metallization plane M1 from which stitch
contacts 3 are routed perpendicularly downward and are connected to the gate conductors GC of therespective switching transistors 2 via level shifters B located in the region of thestitch contacts 3. - For writing purposes, a current of about 1 to 2 mA is impressed between the interconnects of the metallization planes M1 and M2. The voltage present in this case should not exceed about 0.5 V since otherwise the
magnetoresistive resistor 1 or the TMR element might be destroyed. As in the conventional MRAM memory cell of FIG. 4, the resistance of themagnetoresistive resistor 1 is defined by this write operation. - During a read operation, a voltage of about 0.5 V is applied to the interconnect of the metallization plane M2. The resistance of the
magnetoresistive resistor 1 is then measured via the interconnect of the metallization plane M1. Since the voltage drop across themagnetoresistive resistor 1 must not exceed 0.5 V in this case, voltage amplification must be performed for the purpose of driving the switchingtransistor 2, this being done by the level shifter B which is inserted between the gate conductor GC of the switchingtransistor 2 and thestitch contact 3 in the region thereof. The level shifter B thus ensures that the critical voltage is not reached across themagnetoresistive resistor 1, but that the switchingtransistor 2 can nevertheless be turned on.
Claims (4)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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DE10034868A DE10034868C2 (en) | 2000-07-18 | 2000-07-18 | MRAM memory cell |
DE10034868.8 | 2000-07-18 | ||
DE10034868 | 2000-07-18 |
Publications (2)
Publication Number | Publication Date |
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US20020008989A1 true US20020008989A1 (en) | 2002-01-24 |
US6424563B2 US6424563B2 (en) | 2002-07-23 |
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US09/907,778 Expired - Fee Related US6424563B2 (en) | 2000-07-18 | 2001-07-18 | MRAM memory cell |
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EP (1) | EP1174924A2 (en) |
JP (1) | JP2002118238A (en) |
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CN (1) | CN1207719C (en) |
DE (1) | DE10034868C2 (en) |
TW (1) | TW516229B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040085810A1 (en) * | 2002-10-30 | 2004-05-06 | Heinz Hoenigschmid | Magnetic tunnel junction memory cell architecture |
US8115597B1 (en) * | 2007-03-07 | 2012-02-14 | Impinj, Inc. | RFID tags with synchronous power rectifier |
US8228175B1 (en) | 2008-04-07 | 2012-07-24 | Impinj, Inc. | RFID tag chips and tags with alternative behaviors and methods |
US8326256B1 (en) | 2008-07-15 | 2012-12-04 | Impinj, Inc. | RFID tag with MOS bipolar hybrid rectifier |
US9953692B1 (en) | 2017-04-11 | 2018-04-24 | Sandisk Technologies Llc | Spin orbit torque MRAM memory cell with enhanced thermal stability |
US10211393B2 (en) | 2017-02-23 | 2019-02-19 | Sandisk Technologies Llc | Spin accumulation torque MRAM |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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DE10059181C2 (en) * | 2000-11-29 | 2002-10-24 | Infineon Technologies Ag | Integrated magnetoresistive semiconductor memory and manufacturing process therefor |
US7782661B2 (en) * | 2007-04-24 | 2010-08-24 | Magic Technologies, Inc. | Boosted gate voltage programming for spin-torque MRAM array |
US8102700B2 (en) | 2008-09-30 | 2012-01-24 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US7876603B2 (en) | 2008-09-30 | 2011-01-25 | Micron Technology, Inc. | Spin current generator for STT-MRAM or other spintronics applications |
US8310861B2 (en) * | 2008-09-30 | 2012-11-13 | Micron Technology, Inc. | STT-MRAM cell structure incorporating piezoelectric stress material |
US7944738B2 (en) * | 2008-11-05 | 2011-05-17 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US8553449B2 (en) | 2009-01-09 | 2013-10-08 | Micron Technology, Inc. | STT-MRAM cell structures |
US7957182B2 (en) * | 2009-01-12 | 2011-06-07 | Micron Technology, Inc. | Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same |
US10242946B2 (en) | 2017-01-27 | 2019-03-26 | Globalfoundries Inc. | Circuit design having aligned power staples |
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US6169687B1 (en) * | 1995-04-21 | 2001-01-02 | Mark B. Johnson | High density and speed magneto-electronic memory for use in computing system |
US5734605A (en) * | 1996-09-10 | 1998-03-31 | Motorola, Inc. | Multi-layer magnetic tunneling junction memory cells |
DE19744095A1 (en) * | 1997-10-06 | 1999-04-15 | Siemens Ag | Memory cell array has stacked layer magnetoresistive effect layer memory elements |
US6172903B1 (en) * | 1998-09-22 | 2001-01-09 | Canon Kabushiki Kaisha | Hybrid device, memory apparatus using such hybrid devices and information reading method |
-
2000
- 2000-07-18 DE DE10034868A patent/DE10034868C2/en not_active Expired - Fee Related
-
2001
- 2001-07-05 EP EP01116329A patent/EP1174924A2/en not_active Withdrawn
- 2001-07-16 TW TW090117339A patent/TW516229B/en not_active IP Right Cessation
- 2001-07-17 JP JP2001217382A patent/JP2002118238A/en active Pending
- 2001-07-18 US US09/907,778 patent/US6424563B2/en not_active Expired - Fee Related
- 2001-07-18 CN CNB011259639A patent/CN1207719C/en not_active Expired - Fee Related
- 2001-07-18 KR KR10-2001-0043079A patent/KR100444743B1/en not_active IP Right Cessation
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040085810A1 (en) * | 2002-10-30 | 2004-05-06 | Heinz Hoenigschmid | Magnetic tunnel junction memory cell architecture |
WO2004040580A1 (en) * | 2002-10-30 | 2004-05-13 | Infineon Technologies Ag | Magnetic tunnel junction memory cell architecture |
US6944049B2 (en) | 2002-10-30 | 2005-09-13 | Infineon Technologies Ag | Magnetic tunnel junction memory cell architecture |
US8115597B1 (en) * | 2007-03-07 | 2012-02-14 | Impinj, Inc. | RFID tags with synchronous power rectifier |
US8228175B1 (en) | 2008-04-07 | 2012-07-24 | Impinj, Inc. | RFID tag chips and tags with alternative behaviors and methods |
US8326256B1 (en) | 2008-07-15 | 2012-12-04 | Impinj, Inc. | RFID tag with MOS bipolar hybrid rectifier |
US10211393B2 (en) | 2017-02-23 | 2019-02-19 | Sandisk Technologies Llc | Spin accumulation torque MRAM |
US9953692B1 (en) | 2017-04-11 | 2018-04-24 | Sandisk Technologies Llc | Spin orbit torque MRAM memory cell with enhanced thermal stability |
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CN1334567A (en) | 2002-02-06 |
EP1174924A2 (en) | 2002-01-23 |
JP2002118238A (en) | 2002-04-19 |
KR20020008057A (en) | 2002-01-29 |
KR100444743B1 (en) | 2004-08-16 |
DE10034868A1 (en) | 2002-02-07 |
DE10034868C2 (en) | 2002-06-27 |
TW516229B (en) | 2003-01-01 |
CN1207719C (en) | 2005-06-22 |
US6424563B2 (en) | 2002-07-23 |
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