US20020003277A1 - Technique for forming shallow trench isolation structure without corner exposure and resulting structure - Google Patents
Technique for forming shallow trench isolation structure without corner exposure and resulting structure Download PDFInfo
- Publication number
- US20020003277A1 US20020003277A1 US09/944,506 US94450601A US2002003277A1 US 20020003277 A1 US20020003277 A1 US 20020003277A1 US 94450601 A US94450601 A US 94450601A US 2002003277 A1 US2002003277 A1 US 2002003277A1
- Authority
- US
- United States
- Prior art keywords
- trench
- film layer
- buffer film
- semiconductor device
- precursor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- the present invention relates to an apparatus and method for forming a shallow trench isolation structure. More particularly, the present invention relates to forming the shallow trench isolation structure using a buffer film layer etched such that a capped trench structure is formed which isolates the shallow trench corners.
- the semiconductor industry continually strives to increase semiconductor device performance and density by miniaturizing the individual semiconductor components and by miniaturizing the overall semiconductor device dimensions.
- the semiconductor device density can be increased by more densely integrating the components on the semiconductor chip.
- increasing integration densities by placing the individual circuit elements in closer proximity increases the potential for interactions between the circuit elements. Therefore, it has become necessary to include isolation structures to prevent any significant interaction between circuit elements on the same chip.
- Contemporary CMOS technologies generally employ field effect transistors that are adjacent or bounded by trenches. These trenches provide isolation (shallow trench isolation or “STI”) for the semiconductor devices. However, the close proximity of each semiconductor device to an edge or corner of the trench may create parasitic leakage paths. The parasitic leakage paths result from an enhancement of the gate electric field near the trench corners. This gate electric field is enhanced by the trench corner's small radius of curvature and the proximity of the gate conductor. As a result of the enhanced gate electric field, the trench corner has a lower threshold voltage (V t ) than the planar portion of the device.
- V t threshold voltage
- U.S. Pat. No. 5,436,488, issued Jul. 25, 1995 to Poon et al. teaches improving trench isolation by increasing the thickness of the gate dielectric overlying the trench corner between the substrate and gate electrode.
- the process taught in this patent also requires numerous additional fabrication steps and structures, which of course increase the overall cost of the semiconductor component.
- the present invention relates to a shallow isolation trench structure which is formed using a buffer film layer.
- the buffer film layer is etched in such a manner that an isolation material within the shallow trench has a cap which covers the shallow trench corners to prevent corner effects.
- the method of the present invention comprises providing a semiconductor substrate, preferably a silicon substrate, with a dielectric layer, preferably silicon dioxide, formed on at least one surface of the semiconductor substrate to a thickness of between 50 and 300 ⁇ .
- the dielectric layer can be formed by any known technique, including thermally oxidizing the surface of the semiconductor substrate, chemical vapor deposition, sputtering, or the like.
- a buffer film layer, preferably silicon nitride, is then formed over the dielectric layer by any known deposition technique, preferably chemical vapor deposition.
- the buffer layer may be any known material which is oxidation resistant and can be etched selectively to oxide films.
- a photoresist mask is applied and patterned on the buffer film layer.
- the buffer film layer, the dielectric layer, and semiconductor substrate are then etched either simultaneously with a non-selective etch or in steps with selective etches to form a shallow trench with sidewalls and a bottom.
- the photoresist mask is then removed to form a trenched structure.
- a thin layer of oxide is grown on the shallow trench sidewalls and bottom, preferably by thermal oxidization.
- the buffer film layer is then selectively etched horizontally and vertically to move the buffer film layer back from the shallow trench.
- the purpose for using a buffer film layer, which is oxidation resistant, as discussed above, is shown in FIG. 11. If an oxidizable material is used as a buffer film layer 202 over a dielectric layer 204 and a substrate 206 , the formation of a thin oxide layer 208 in trench 210 would also cause the formation of an additional thin layer of oxide 212 to form on the buffer film layer 202 .
- oxidizable materials such as silicon dioxide
- the additional thin oxide layer 212 is relatively thicker than the thin oxide layer 208 , which results in a narrowing of the opening at the mouth of the trench 210 . This narrowing makes it difficult to fill the trench 210 with an isolation material 214 , and may even cause the formation of voids 216 in the isolation material 214 during the application of the isolation material 214 .
- the shallow trench is then filled with an isolation material.
- the resulting structure is preferably annealed to densify the deposited isolation material. Densification of the deposited isolation material is required to enhance the resistance of the isolation material to etching during subsequent processing.
- a portion of the isolation material over the buffer film layer is then removed to the level of the buffer film layer. The removal of isolation material is preferably achieved with a process such as chemical mechanical planarization which abrades away the isolation material down to the buffer film layer.
- the buffer film layer is then selectively etched away to form an isolation structure. When this isolation structure is etched during a subsequent wet oxide etch process, the isolation structure will form the capped shallow trench isolation structure which covers the trench corners. This capped shallow trench isolation structure substantially minimizes corner effects.
- FIGS. 1 - 10 are cross-sectional views of the method of forming a shallow trench isolation structure of the present invention.
- FIG. 11 is a cross-sectional view of a shallow trench isolation structure formed with a conventional oxidizable buffer film layer.
- FIGS. 1 through 10 illustrate, in cross-section, a method for forming a shallow trench isolation structure in accordance with one embodiment of the present invention.
- the method comprises forming a layered structure 100 of a semiconductor substrate 102 , a dielectric layer 104 , and a buffer film layer 106 .
- the semiconductor substrate 102 preferably includes silicon and the dielectric layer 104 preferably includes silicon dioxide.
- the dielectric layer 104 is preferably between 50 and 300 ⁇ thick (a convenient range for process integration) and can be formed by any known technique including thermally oxidizing the surface of the semiconductor substrate 102 , chemical vapor deposition, sputtering, or the like.
- the buffer film layer 106 preferably comprising silicon nitride, is formed over the dielectric layer 104 by any known deposition technique, preferably chemical vapor deposition.
- a photoresist mask 108 is applied over the buffer film layer 106 and patterned using standard photolithographic patterning techniques, as shown in FIG. 2.
- the buffer film layer 106 and the dielectric layer 104 are then etched by standard etching techniques to form patterned recess 110 , as shown in FIG. 3.
- the silicon substrate 102 is then dry etched to form a shallow trench 112 with sidewalls 114 and a bottom 116 , seen in FIG. 4. It is, of course, understood that the buffer film layer 106 , the dielectric layer 104 , and semiconductor substrate 102 can be etched in one non-selective etching step.
- the photoresist mask 108 is removed using standard photoresist stripping techniques, preferably by plasma etch, to form a trenched structure 118 , as shown in FIG. 4.
- a thin layer of oxide 120 is grown on the shallow trench sidewalls 114 and the shallow trench bottom 116 , preferably by thermal oxidization, as shown in FIG. 5.
- the buffer film layer 106 is then selectively etched horizontally and vertically to move the buffer film layer 106 back from the shallow trench 112 .
- the etching of the buffer film layer 106 is preferably a wet etch process including an application of a 100:1 HF (hydrofluoric acid) solution followed by an application of a H 3 PO 4 (phosphoric acid) solution or an H2O/N(CH 2 CH 3 ) 4 OH (“TMAH”) solution.
- a 100:1 HF hydrofluoric acid
- H 3 PO 4 phosphoric acid
- TMAH H2O/N(CH 2 CH 3 ) 4 OH
- the shallow trench 112 is then filled with an isolation material 122 , as shown in FIG. 7.
- the isolation material 122 is preferably silicon dioxide deposited by any known technique including chemical vapor deposition using tetraethylorthosilane (TEOS) or ozone as source gases, electron cyclotron resonance deposition, spin-on deposition, and the like.
- TEOS tetraethylorthosilane
- the isolation material 122 can be annealed to densify the deposited isolation material 122 . Densification of the deposited isolation material 122 is used to enhance the resistance of the isolation material 122 to etching during subsequent processing.
- the annealing is preferably conducted in a nitrogen or other inert gas atmosphere to prevent oxidation of the semiconductor substrate 102 beneath the isolation material 122 .
- the isolation material 122 is removed down to the buffer film layer 106 , preferably by a mechanical abrasion process, such as chemical/mechanical planarization.
- the buffer film layer 106 is then selectively etched away, by any known technique such as a hot H 3 PO 4 (phosphoric acid), to form an isolation structure 124 , as shown in FIG. 9.
- this isolation structure 124 is etched during a subsequent wet oxide process to expose the upper surface 132 of said semiconductor substrate 102
- the isolation structure 124 will form a capped shallow trench isolation structure 126 which covers the trench corners 128 of the shallow trench 112 with ledges 130 , as shown in FIG. 10.
- the ledges 130 preferably extend horizontally between about 50 and 150 521 from the trench corners 128 . These ledges 130 prevent the aforementioned corner effects.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer which is atop a semiconductor substrate. The buffer film layer comprises a material which is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure which covers the shallow trench corners is created.
Description
- This application is a continuation of application Ser. No. 08/789,470, filed Jan. 27,
- 1. Field of the Invention
- The present invention relates to an apparatus and method for forming a shallow trench isolation structure. More particularly, the present invention relates to forming the shallow trench isolation structure using a buffer film layer etched such that a capped trench structure is formed which isolates the shallow trench corners.
- 2. State of the Art
- The semiconductor industry continually strives to increase semiconductor device performance and density by miniaturizing the individual semiconductor components and by miniaturizing the overall semiconductor device dimensions. For example, the semiconductor device density can be increased by more densely integrating the components on the semiconductor chip. However, increasing integration densities by placing the individual circuit elements in closer proximity increases the potential for interactions between the circuit elements. Therefore, it has become necessary to include isolation structures to prevent any significant interaction between circuit elements on the same chip.
- Contemporary CMOS technologies generally employ field effect transistors that are adjacent or bounded by trenches. These trenches provide isolation (shallow trench isolation or “STI”) for the semiconductor devices. However, the close proximity of each semiconductor device to an edge or corner of the trench may create parasitic leakage paths. The parasitic leakage paths result from an enhancement of the gate electric field near the trench corners. This gate electric field is enhanced by the trench corner's small radius of curvature and the proximity of the gate conductor. As a result of the enhanced gate electric field, the trench corner has a lower threshold voltage (Vt) than the planar portion of the device.
- Presently known formation techniques for such trenches generally involve a wet etch, which can exacerbate the parasitic leakage problem by sharpening the trench corners and thinning the gate dielectric near the trench corner. Furthermore, present trench formation techniques generally expose the trench corners before gate electrode deposition. The exposure of trench corners will increase the sub-Vt leakage and degrade gate oxide integrity. The aforementioned problems will be hereinafter referred to collectively as “corner effects.”
- Corner effects can even dominate on-currents in applications such as DRAM chips that require narrow channel widths to achieve high density. This parallel current-carrying corner effect becomes the dominant MOSFET contributor to standby current in low standby power logic applications and to leakage in DRAM cells. Furthermore, there exists concern that the enhanced electric fields due to field crowding at the trench corner may impact dielectric integrity.
- Numerous techniques have been proposed to overcome the above discussed corner effects. Commonly-owned U.S. Pat. No. 5,433,794, issued Jul. 18, 1995 to Fazan et al., hereby incorporated herein by reference, and U.S. Pat. No. 5,521,422, issued May 28, 1996 to Mandelman et al., each teach forming shallow trench isolation structures wherein insulating material spacers are formed abutting the trench corners and the isolating material filling and extending above the trench. When a wet pad oxide etch is performed, the isolating material combines with the spacers to form an isolation trench having a dome or cap-like covering the peripheral edges of the trench which substantially overcomes the corner effects and consequential leakage between active areas on the substrate. Although the techniques taught in these patents are effective in minimizing corner effects, the techniques require additional fabrication steps which increase the overall cost of the semiconductor component.
- U.S. Pat. No. 5,436,488, issued Jul. 25, 1995 to Poon et al., teaches improving trench isolation by increasing the thickness of the gate dielectric overlying the trench corner between the substrate and gate electrode. However, the process taught in this patent also requires numerous additional fabrication steps and structures, which of course increase the overall cost of the semiconductor component.
- Therefore, it would be advantageous to develop a shallow isolation trench and a technique for forming the trench which substantially eliminates the aforementioned corner effects, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and apparatus.
- The present invention relates to a shallow isolation trench structure which is formed using a buffer film layer. The buffer film layer is etched in such a manner that an isolation material within the shallow trench has a cap which covers the shallow trench corners to prevent corner effects.
- The method of the present invention comprises providing a semiconductor substrate, preferably a silicon substrate, with a dielectric layer, preferably silicon dioxide, formed on at least one surface of the semiconductor substrate to a thickness of between 50 and 300 Å. The dielectric layer can be formed by any known technique, including thermally oxidizing the surface of the semiconductor substrate, chemical vapor deposition, sputtering, or the like. A buffer film layer, preferably silicon nitride, is then formed over the dielectric layer by any known deposition technique, preferably chemical vapor deposition. Although silicon nitride is preferred, the buffer layer may be any known material which is oxidation resistant and can be etched selectively to oxide films.
- A photoresist mask is applied and patterned on the buffer film layer. The buffer film layer, the dielectric layer, and semiconductor substrate are then etched either simultaneously with a non-selective etch or in steps with selective etches to form a shallow trench with sidewalls and a bottom. The photoresist mask is then removed to form a trenched structure.
- After stripping the photoresist and cleaning the trenched structure, a thin layer of oxide, between about 50 and 150 Å thick, is grown on the shallow trench sidewalls and bottom, preferably by thermal oxidization. The buffer film layer is then selectively etched horizontally and vertically to move the buffer film layer back from the shallow trench. The purpose for using a buffer film layer, which is oxidation resistant, as discussed above, is shown in FIG. 11. If an oxidizable material is used as a
buffer film layer 202 over adielectric layer 204 and asubstrate 206, the formation of athin oxide layer 208 intrench 210 would also cause the formation of an additional thin layer ofoxide 212 to form on thebuffer film layer 202. Most oxidizable materials, such as silicon dioxide, used for forming thebuffer film layer 202 have a greater affinity for growing oxides than the semiconductor substrate. As a result, the additionalthin oxide layer 212 is relatively thicker than thethin oxide layer 208, which results in a narrowing of the opening at the mouth of thetrench 210. This narrowing makes it difficult to fill thetrench 210 with anisolation material 214, and may even cause the formation ofvoids 216 in theisolation material 214 during the application of theisolation material 214. - In the method of the present invention, after etching back the buffer film layer, the shallow trench is then filled with an isolation material. The resulting structure is preferably annealed to densify the deposited isolation material. Densification of the deposited isolation material is required to enhance the resistance of the isolation material to etching during subsequent processing. A portion of the isolation material over the buffer film layer is then removed to the level of the buffer film layer. The removal of isolation material is preferably achieved with a process such as chemical mechanical planarization which abrades away the isolation material down to the buffer film layer. The buffer film layer is then selectively etched away to form an isolation structure. When this isolation structure is etched during a subsequent wet oxide etch process, the isolation structure will form the capped shallow trench isolation structure which covers the trench corners. This capped shallow trench isolation structure substantially minimizes corner effects.
- While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
- FIGS.1-10 are cross-sectional views of the method of forming a shallow trench isolation structure of the present invention; and
- FIG. 11 is a cross-sectional view of a shallow trench isolation structure formed with a conventional oxidizable buffer film layer.
- FIGS. 1 through 10 illustrate, in cross-section, a method for forming a shallow trench isolation structure in accordance with one embodiment of the present invention. As shown in FIG. 1, the method comprises forming a
layered structure 100 of asemiconductor substrate 102, adielectric layer 104, and abuffer film layer 106. Thesemiconductor substrate 102 preferably includes silicon and thedielectric layer 104 preferably includes silicon dioxide. Thedielectric layer 104 is preferably between 50 and 300 Å thick (a convenient range for process integration) and can be formed by any known technique including thermally oxidizing the surface of thesemiconductor substrate 102, chemical vapor deposition, sputtering, or the like. Thebuffer film layer 106, preferably comprising silicon nitride, is formed over thedielectric layer 104 by any known deposition technique, preferably chemical vapor deposition. - A
photoresist mask 108, either a positive or negative resist (preferably positive) as known in the art, is applied over thebuffer film layer 106 and patterned using standard photolithographic patterning techniques, as shown in FIG. 2. Thebuffer film layer 106 and thedielectric layer 104 are then etched by standard etching techniques to form patternedrecess 110, as shown in FIG. 3. Thesilicon substrate 102 is then dry etched to form ashallow trench 112 with sidewalls 114 and a bottom 116, seen in FIG. 4. It is, of course, understood that thebuffer film layer 106, thedielectric layer 104, andsemiconductor substrate 102 can be etched in one non-selective etching step. Thephotoresist mask 108 is removed using standard photoresist stripping techniques, preferably by plasma etch, to form a trenchedstructure 118, as shown in FIG. 4. - After stripping the photoresist and cleaning (preferably with an H2O2/H2SO4 or H2O2/HCl mixture) the trenched
structure 118, a thin layer ofoxide 120, between about 50 and 150 Å thick, is grown on the shallow trench sidewalls 114 and theshallow trench bottom 116, preferably by thermal oxidization, as shown in FIG. 5. As shown in FIG. 6, thebuffer film layer 106 is then selectively etched horizontally and vertically to move thebuffer film layer 106 back from theshallow trench 112. The etching of thebuffer film layer 106 is preferably a wet etch process including an application of a 100:1 HF (hydrofluoric acid) solution followed by an application of a H3PO4 (phosphoric acid) solution or an H2O/N(CH2CH3)4OH (“TMAH”) solution. - The
shallow trench 112 is then filled with anisolation material 122, as shown in FIG. 7. Theisolation material 122 is preferably silicon dioxide deposited by any known technique including chemical vapor deposition using tetraethylorthosilane (TEOS) or ozone as source gases, electron cyclotron resonance deposition, spin-on deposition, and the like. Optionally, theisolation material 122 can be annealed to densify the depositedisolation material 122. Densification of the depositedisolation material 122 is used to enhance the resistance of theisolation material 122 to etching during subsequent processing. The annealing is preferably conducted in a nitrogen or other inert gas atmosphere to prevent oxidation of thesemiconductor substrate 102 beneath theisolation material 122. - As shown in FIG. 8, the
isolation material 122 is removed down to thebuffer film layer 106, preferably by a mechanical abrasion process, such as chemical/mechanical planarization. Thebuffer film layer 106 is then selectively etched away, by any known technique such as a hot H3PO4 (phosphoric acid), to form anisolation structure 124, as shown in FIG. 9. When thisisolation structure 124 is etched during a subsequent wet oxide process to expose theupper surface 132 of saidsemiconductor substrate 102, theisolation structure 124 will form a capped shallowtrench isolation structure 126 which covers thetrench corners 128 of theshallow trench 112 withledges 130, as shown in FIG. 10. Theledges 130 preferably extend horizontally between about 50 and 150 521 from thetrench corners 128. Theseledges 130 prevent the aforementioned corner effects. - Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations are possible without departing from the spirit or scope thereof.
Claims (24)
1. A precursor to a semiconductor device structure, comprising:
a semiconductor device layered structure comprising a semiconductor substrate;
a buffer film layer located over at least a portion of said semiconductor substrate;
at least one trench formed in said semiconductor device layered structure; and
at least one shallow trench isolation structure positioned at least partially within said at least one trench and including:
a substantially flat surface; and
an integral ledge which extends laterally outward from said trench so as to contact only an area of an active surface of the semiconductor substrate adjacent said trench.
2. The precursor of claim 1 , wherein said buffer film layer comprises substantially oxidation resistant material.
3. The precursor of claim 2 , wherein said substantially oxidation resistant material is selectively etchable.
4. The precursor of claim 1 , wherein a lateral edge of said integral ledge contacts said buffer film layer.
5. The precursor of claim 1 , wherein said at least one trench isolation structure comprises densified material.
6. The precursor of claim 1 , wherein said buffer film layer comprises silicon nitride.
7. An intermediate semiconductor device structure, comprising:
a semiconductor substrate including at least one trench formed therein and at least one trench corner located at a juncture between said at least one trench and an active surface of said semiconductor substrate; and
a buffer film layer over at least portions of said active surface; and
at least one densified trench isolation structure including a substantially flat surface exposed through said buffer film layer, said at least one trench corner being covered by said at least one densified trench isolation structure.
8. The intermediate semiconductor device structure of claim 7 , wherein said buffer film layer comprises a substantially oxidation resistant material
9. The intermediate semiconductor device structure of claim 7 , further comprising:
a layer comprising silicon oxide disposed within said at least one trench and between said semiconductor substrate and said buffer film layer.
10. The intermediate semiconductor device structure of claim 9 , wherein said layer comprises densified silicon dioxide.
11. The intermediate semiconductor device structure of claim 7 , wherein said at least one trench isolation structure comprises densified material.
12. The intermediate semiconductor device structure of claim 7 , wherein said buffer film layer comprises silicon nitride.
13. An intermediate semiconductor device structure, comprising:
a semiconductor substrate including at least one trench formed therein and at least one trench corner located at a juncture between said at least one trench and an active surface of said semiconductor substrate; and
at least one trench isolation structure including a substantially flat surface, said at least one trench isolation structure extending laterally only over a portion of said active surface adjacent said at least one trench corner so as to electrically isolate said at least one trench corner.
14. The intermediate semiconductor device structure of claim 13 , wherein said at least one trench isolation structure comprises densified silicon dioxide.
15. The intermediate semiconductor device structure of claim 13 , further comprising:
a silicon oxide layer disposed between said semiconductor substrate and said at least one trench isolation structure.
16. The intermediate semiconductor device structure of claim 15 , wherein said silicon oxide layer comprises densified silicon dioxide.
17. The intermediate semiconductor device structure of claim 13 , wherein said buffer film layer comprises silicon nitride.
18. A precursor to a semiconductor device structure, comprising:
a semiconductor substrate;
at least one trench formed in said semiconductor substrate;
a buffer film layer over an active surface of said semiconductor substrate;
and at least one shallow trench isolation structure at least partially within said at least one trench and exposed through said buffer film layer, said at least one shallow trench isolation structure including at least one integral ledge extending laterally outward from said at least one trench so as to contact an area of said active surface adjacent said at least one trench.
19. The precursor of claim 18 , wherein said at least one shallow trench isolation structure includes a substantially planar surface.
20. The precursor of claim 18 , wherein said at least one shall trench isolation structure comprises densified silicon oxide.
21. The precursor of claim 18 , wherein said buffer film layer comprises silicon nitride.
22. The precursor of claim 18 , wherein said buffer film layer comprises densified material.
23. The precursor of claim 18 , wherein said buffer film layer comprises substantially oxidation resistant material.
24. The precursor of claim 23 , wherein said substantially oxidation resistant material is selectively etchable.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/944,506 US20020003277A1 (en) | 1997-01-27 | 2001-08-30 | Technique for forming shallow trench isolation structure without corner exposure and resulting structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/789,470 US6322634B1 (en) | 1997-01-27 | 1997-01-27 | Shallow trench isolation structure without corner exposure |
US09/944,506 US20020003277A1 (en) | 1997-01-27 | 2001-08-30 | Technique for forming shallow trench isolation structure without corner exposure and resulting structure |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/789,470 Continuation US6322634B1 (en) | 1997-01-27 | 1997-01-27 | Shallow trench isolation structure without corner exposure |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020003277A1 true US20020003277A1 (en) | 2002-01-10 |
Family
ID=25147740
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/789,470 Expired - Fee Related US6322634B1 (en) | 1997-01-27 | 1997-01-27 | Shallow trench isolation structure without corner exposure |
US09/072,959 Expired - Fee Related US7892941B2 (en) | 1997-01-27 | 1998-05-05 | Technique for forming shallow trench isolation structure without corner exposure |
US09/944,506 Abandoned US20020003277A1 (en) | 1997-01-27 | 2001-08-30 | Technique for forming shallow trench isolation structure without corner exposure and resulting structure |
US13/023,282 Expired - Fee Related US8338264B2 (en) | 1997-01-27 | 2011-02-08 | Methods for forming isolation structures for semiconductor devices |
US13/610,303 Expired - Fee Related US8637956B2 (en) | 1997-01-27 | 2012-09-11 | Semiconductor devices structures including an isolation structure |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/789,470 Expired - Fee Related US6322634B1 (en) | 1997-01-27 | 1997-01-27 | Shallow trench isolation structure without corner exposure |
US09/072,959 Expired - Fee Related US7892941B2 (en) | 1997-01-27 | 1998-05-05 | Technique for forming shallow trench isolation structure without corner exposure |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/023,282 Expired - Fee Related US8338264B2 (en) | 1997-01-27 | 2011-02-08 | Methods for forming isolation structures for semiconductor devices |
US13/610,303 Expired - Fee Related US8637956B2 (en) | 1997-01-27 | 2012-09-11 | Semiconductor devices structures including an isolation structure |
Country Status (1)
Country | Link |
---|---|
US (5) | US6322634B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110129985A1 (en) * | 1997-01-27 | 2011-06-02 | Micron Technology, Inc. | Methods for forming isolation structures for semiconductor devices |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6818559B2 (en) | 2001-03-21 | 2004-11-16 | Intel Corporation | Method of fabrication to sharpen corners of Y-branches in integrated optical components and other micro-devices |
US6716719B2 (en) | 2002-05-29 | 2004-04-06 | Micron Technology, Inc. | Method of forming biasable isolation regions using epitaxially grown silicon between the isolation regions |
US6821857B1 (en) | 2003-06-10 | 2004-11-23 | International Business Machines Corporation | High on-current device for high performance embedded DRAM (eDRAM) and method of forming the same |
US7119403B2 (en) * | 2003-10-16 | 2006-10-10 | International Business Machines Corporation | High performance strained CMOS devices |
JP4577680B2 (en) * | 2004-04-13 | 2010-11-10 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
US7332408B2 (en) | 2004-06-28 | 2008-02-19 | Micron Technology, Inc. | Isolation trenches for memory devices |
US20070235783A9 (en) * | 2005-07-19 | 2007-10-11 | Micron Technology, Inc. | Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions |
US7772672B2 (en) | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Semiconductor constructions |
US20070212874A1 (en) * | 2006-03-08 | 2007-09-13 | Micron Technology, Inc. | Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device |
US7799694B2 (en) | 2006-04-11 | 2010-09-21 | Micron Technology, Inc. | Methods of forming semiconductor constructions |
US8440540B2 (en) * | 2009-10-02 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for doping a selected portion of a device |
US8785291B2 (en) | 2011-10-20 | 2014-07-22 | International Business Machines Corporation | Post-gate shallow trench isolation structure formation |
US8466496B2 (en) | 2011-11-17 | 2013-06-18 | International Business Machines Corporation | Selective partial gate stack for improved device isolation |
US8603895B1 (en) * | 2012-09-11 | 2013-12-10 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4307180A (en) * | 1980-08-22 | 1981-12-22 | International Business Machines Corp. | Process of forming recessed dielectric regions in a monocrystalline silicon substrate |
US4786954A (en) * | 1984-04-19 | 1988-11-22 | Nippon Telegraph & Telephone Public Corporation | Dynamic ram cell with trench surrounded switching element |
US4835584A (en) * | 1986-11-27 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench transistor |
US4849344A (en) * | 1986-12-11 | 1989-07-18 | Fairchild Semiconductor Corporation | Enhanced density modified isoplanar process |
US5173439A (en) * | 1989-10-25 | 1992-12-22 | International Business Machines Corporation | Forming wide dielectric-filled isolation trenches in semi-conductors |
US5272117A (en) * | 1992-12-07 | 1993-12-21 | Motorola, Inc. | Method for planarizing a layer of material |
US5296392A (en) * | 1990-03-06 | 1994-03-22 | Digital Equipment Corporation | Method of forming trench isolated regions with sidewall doping |
US5297082A (en) * | 1992-11-12 | 1994-03-22 | Micron Semiconductor, Inc. | Shallow trench source eprom cell |
US5346587A (en) * | 1993-08-12 | 1994-09-13 | Micron Semiconductor, Inc. | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5436488A (en) * | 1993-09-30 | 1995-07-25 | Motorola Inc. | Trench isolator structure in an integrated circuit |
US5459096A (en) * | 1994-07-05 | 1995-10-17 | Motorola Inc. | Process for fabricating a semiconductor device using dual planarization layers |
US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
US5506168A (en) * | 1992-10-27 | 1996-04-09 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4835585A (en) * | 1984-11-26 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench gate structures |
US4693781A (en) * | 1986-06-26 | 1987-09-15 | Motorola, Inc. | Trench formation process |
DE4300986C2 (en) * | 1992-01-17 | 1999-08-26 | Mitsubishi Electric Corp | Semiconductor device for element isolation and manufacturing method thereof |
US5516625A (en) | 1993-09-08 | 1996-05-14 | Harris Corporation | Fill and etchback process using dual photoresist sacrificial layer and two-step etching process for planarizing oxide-filled shallow trench structure |
CA2131668C (en) | 1993-12-23 | 1999-03-02 | Carol Galli | Isolation structure using liquid phase oxide deposition |
DE69516769T2 (en) * | 1994-03-15 | 2000-12-28 | National Semiconductor Corp., Sunnyvale | PLANARIZED INSULATION TRENCH AND FIELD OXIDE INSULATION STRUCTURE |
US5455194A (en) * | 1995-03-06 | 1995-10-03 | Motorola Inc. | Encapsulation method for localized oxidation of silicon with trench isolation |
KR0151051B1 (en) * | 1995-05-30 | 1998-12-01 | 김광호 | Method of forming insulation film for semiconductor device |
JP2762976B2 (en) * | 1995-12-25 | 1998-06-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
US6322634B1 (en) | 1997-01-27 | 2001-11-27 | Micron Technology, Inc. | Shallow trench isolation structure without corner exposure |
US5811346A (en) * | 1997-04-14 | 1998-09-22 | Vlsi Technology, Inc. | Silicon corner rounding in shallow trench isolation process |
US5960297A (en) | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US5801083A (en) * | 1997-10-20 | 1998-09-01 | Chartered Semiconductor Manufacturing, Ltd. | Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners |
-
1997
- 1997-01-27 US US08/789,470 patent/US6322634B1/en not_active Expired - Fee Related
-
1998
- 1998-05-05 US US09/072,959 patent/US7892941B2/en not_active Expired - Fee Related
-
2001
- 2001-08-30 US US09/944,506 patent/US20020003277A1/en not_active Abandoned
-
2011
- 2011-02-08 US US13/023,282 patent/US8338264B2/en not_active Expired - Fee Related
-
2012
- 2012-09-11 US US13/610,303 patent/US8637956B2/en not_active Expired - Fee Related
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4307180A (en) * | 1980-08-22 | 1981-12-22 | International Business Machines Corp. | Process of forming recessed dielectric regions in a monocrystalline silicon substrate |
US4786954A (en) * | 1984-04-19 | 1988-11-22 | Nippon Telegraph & Telephone Public Corporation | Dynamic ram cell with trench surrounded switching element |
US4835584A (en) * | 1986-11-27 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench transistor |
US4849344A (en) * | 1986-12-11 | 1989-07-18 | Fairchild Semiconductor Corporation | Enhanced density modified isoplanar process |
US5173439A (en) * | 1989-10-25 | 1992-12-22 | International Business Machines Corporation | Forming wide dielectric-filled isolation trenches in semi-conductors |
US5296392A (en) * | 1990-03-06 | 1994-03-22 | Digital Equipment Corporation | Method of forming trench isolated regions with sidewall doping |
US5506168A (en) * | 1992-10-27 | 1996-04-09 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
US5297082A (en) * | 1992-11-12 | 1994-03-22 | Micron Semiconductor, Inc. | Shallow trench source eprom cell |
US5272117A (en) * | 1992-12-07 | 1993-12-21 | Motorola, Inc. | Method for planarizing a layer of material |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5346587A (en) * | 1993-08-12 | 1994-09-13 | Micron Semiconductor, Inc. | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation |
US5436488A (en) * | 1993-09-30 | 1995-07-25 | Motorola Inc. | Trench isolator structure in an integrated circuit |
US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
US5459096A (en) * | 1994-07-05 | 1995-10-17 | Motorola Inc. | Process for fabricating a semiconductor device using dual planarization layers |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110129985A1 (en) * | 1997-01-27 | 2011-06-02 | Micron Technology, Inc. | Methods for forming isolation structures for semiconductor devices |
US8338264B2 (en) | 1997-01-27 | 2012-12-25 | Micron Technology, Inc. | Methods for forming isolation structures for semiconductor devices |
US8637956B2 (en) | 1997-01-27 | 2014-01-28 | Micron Technology, Inc. | Semiconductor devices structures including an isolation structure |
Also Published As
Publication number | Publication date |
---|---|
US8338264B2 (en) | 2012-12-25 |
US7892941B2 (en) | 2011-02-22 |
US20130001737A1 (en) | 2013-01-03 |
US8637956B2 (en) | 2014-01-28 |
US6322634B1 (en) | 2001-11-27 |
US20010014511A1 (en) | 2001-08-16 |
US20110129985A1 (en) | 2011-06-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8637956B2 (en) | Semiconductor devices structures including an isolation structure | |
KR100306935B1 (en) | How to Form Trench Isolation in Integrated Circuits | |
EP0736897B1 (en) | Method for forming a trench isolation structure in an integrated circuit | |
US6524931B1 (en) | Method for forming a trench isolation structure in an integrated circuit | |
US6165854A (en) | Method to form shallow trench isolation with an oxynitride buffer layer | |
US5989977A (en) | Shallow trench isolation process | |
US6627512B2 (en) | Method of manufacturing a semiconductor device | |
US5960298A (en) | Method of fabricating semiconductor device having trench isolation structure | |
US7611950B2 (en) | Method for forming shallow trench isolation in semiconductor device | |
US6518635B1 (en) | Semiconductor device and manufacturing method thereof | |
KR100230816B1 (en) | Method of forming an element isolation in a semiconductor device | |
US20030209760A1 (en) | Semiconductor integrated circuit and method of fabricating the same | |
JPH1041291A (en) | Element isolation film forming method of semiconductor device | |
US6682987B2 (en) | Methods of forming a trench isolation region in a substrate by removing a portion of a liner layer at a boundary between a trench etching mask and an oxide layer in a trench and integrated circuit devices formed thereby | |
US6255218B1 (en) | Semiconductor device and fabrication method thereof | |
US6635537B2 (en) | Method of fabricating gate oxide | |
JPS61247051A (en) | Manufacture of semiconductor device | |
US6521509B2 (en) | Semiconductor device and method of manufacturing the same | |
US20010012675A1 (en) | Shallow trench isolation process | |
KR101026481B1 (en) | Method for manufacturing semiconductor device | |
KR20030001965A (en) | Method for fabricating semiconductor device | |
KR20040050554A (en) | Method of forming an isolation layer in a semiconductor device | |
KR20000051041A (en) | Trench isolation method of semiconductor integrated circuit | |
KR20030085997A (en) | Method for fabricating semiconductor device | |
KR20040055019A (en) | Method of forming an isolation layer in a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |