US20020000857A1 - High performance impulse flip-flops - Google Patents
High performance impulse flip-flops Download PDFInfo
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- US20020000857A1 US20020000857A1 US09/874,866 US87486601A US2002000857A1 US 20020000857 A1 US20020000857 A1 US 20020000857A1 US 87486601 A US87486601 A US 87486601A US 2002000857 A1 US2002000857 A1 US 2002000857A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
- H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
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Abstract
A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.
Description
- The present invention pertains to the field of electronic circuits. More particularly, the present invention relates to the design of flip-flop circuitry.
- Flip-flop circuits are used to maintain an output state (Q) based upon the sampling of an input data signal (D) at a particular point in time determined by a clock signal (CLK). The sampling of the input data signal is activated either by the edge or the level of the clock signal. At all other times, the output of the flip-flop circuit will not respond to changes in the input data signal.
- Typical flip-flops have shortcomings. One such typical flip-flop is the master-slave flip-flop, which consists of two stages, the master and the slave. To change the output of the master-slave flip-flop, a signal must propagate through both the master and the slave stages. In fast circuits, this delay can pose problems.
- Additionally, the number of logic devices used to build both the master and the slave can be large. This large number of devices may consume more power than desirable.
- Also, the master-slave flip-flop requires that the data input be present and stable for a given time before the clock activates the sampling for the flip-flop to accurately respond to the data input. This is called the data “setup” time. Setup time affects the speed at which a flip-flop may operate. Thus, a setup time may pose a problem.
- The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
- FIG. 1 is a block diagram of a flip-flop;
- FIG. 2 is a block diagram of a computer system;
- FIG. 3 is a circuit diagram of an embodiment of a flip-flop;
- FIG. 4 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 3;
- FIG. 5 is a circuit diagram of another embodiment of a flip-flop;
- FIG. 6 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 5.
- A method and apparatus for a flip-flop are described. The invention has a clock-to-output delay of two inverters in one embodiment. In another embodiment the clock-to-output delay is an inverter and a pass transistor. Because of the reduced clock-to-output delay, the flip-flops are extremely fast. The flip-flops do not require any setup time. The output of the flip-flops is also buffered. This buffering isolates the keeper circuit from the load. The flip-flops require fewer transistors than conventional flip-flop implementations, so may be smaller in size and/or consume less power.
- FIG. 1 is a block diagram of a flip-flop. An input signal in the form of a clock is received102. The clock input signal is next checked to determine if it is requesting a
data input sample 104. If the input clock signal is not requesting a data input sample, then the input clock signal is checked again at 104. If the input clock signal is requesting a data input sample, then the data input signal is sampled 106. After the data input signal is sampled 106, the data input signal sample is transferred to astorage element 108. The storage element, representing the data input signal sample, is then buffered 110, and the buffered signal is presented as theoutput 112. - FIG. 2 is a block diagram of a computer system. The block diagram is a high level conceptual representation and may be implemented in a variety of ways and by various architectures.
Bus system 202 interconnects a Central Processing Unit (CPU) 204, Read Only Memory (ROM) 206, Random Access Memory (RAM) 208,storage 210,display 220, audio, 222,keyboard 224,pointer 226, miscellaneous inputloutput (I/O)devices 228, andcommunications 230. Thebus system 202 may be for example, one or more of such buses as a system bus, Peripheral Component Interconnect (PCI), Advanced Graphics Port (AGP), Small Computer System Interface (SCSI), Institute of Electrical and Electronics Engineers (IEEE) standard number 1394 (FireWire), etc. TheCPU 204 may be a single, multiple, or even a distributed computing resource. TheROM 206 may be any type of non-volatile memory, which may be programmable such as, mask programmable, flash, etc.RAM 208 may be, for example, static, dynamic, synchronous, asynchronous, or any combination.Storage 210, may be Compact Disc (CD), Digital Versatile Disk (DVD), hard disks, optical disks, tape, flash, memory sticks, video recorders, etc.Display 220 might be, for example, a Cathode Ray Tube (CRT), Liquid Crystal Display (LCD), a projection system, Television (TV), etc.Audio 222 may be a monophonic, stereo, three dimensional sound card, etc. Thekeyboard 224 may be a keyboard, a musical keyboard, a keypad, a series of switches, etc. Thepointer 226, may be, for example, a mouse, a touchpad, a trackball, joystick, etc. I/O devices 228, might be a voice command input device, a thumbprint input device, a smart card slot, a Personal Computer Card (PC Card) interface, virtual reality accessories, etc., which may optionally connect via an input/output port 229 to other devices or systems. An example of a miscellaneous I/O device 228 would be a Musical Instrument Digital Interface (MIDI) card.Communications device 230 might be, for example, an Ethernet adapter for local area network (LAN) connections, a satellite connection, a settop box adapter, a Digital Subscriber Line (xDSL) adapter, a wireless modem, a conventional telephone modem, a direct telephone connection, a Hybrid-Fiber Coax (HFC) connection, cable modem, etc. Note that depending upon the actual implementation of a computer system, the computer system may include some, all, more, or a rearrangement of components in the block diagram. For example, a thin client might consist of a wireless hand held device that lacks, for example, a traditional keyboard. Thus, many variations on the system of FIG. 2 are possible. - The present invention is capable of being embodied in each of the blocks of the computer system described above. Flip-
flop 205 in theCPU 204 may be used to store the results of processing. Flip-flop 205 may be used to latch the signals received from thebus system 202. A flip-flop 207 used inROM 206, may store the results of an access for presentation as an output onbus system 202. Likewise, theROM 206 may embody the flip-flop 207 to latch an address that thebus system 202 presents to theROM 206. A flip-flop 209 used inRAM 208, may store the results of an access for presentation as an output onbus system 202.RAM 208 may embody the flip-flop 209 to latch an address that thebus system 202 presents to theRAM 208. TheRAM 208 may also use a flip-flop 209 as a storage element for either main storage, or cache storage.Storage 210 may for example, embody a flip-flop 211, as an output storage device to present its output to thebus 202. Flip-flop 211 may also store such things as user options for operation of thestorage 210 which are received from thebus 202.Display 220 might use flip-flop 221 to latch a display signal, for example, ifdisplay 220 is an LCD display, flip-flop 221 might be used in an active-matrix as the storage element for a pixel. Ifdisplay 220 is a CRT, flip-flop 221, might be used to store correction parameters, such as pin cushion correction.Audio 222 may use flip-flop 223 to store input and/or output signals received/sent tobus system 202. Thekeyboard 224 may use flip-flop 225 to store the status of indicators such as the numeric lock, caps lock, scroll lock, etc. Thepointer 226, for example as a mouse, may use flip-flop 227 to store the status of a user click. An I/O device 228, for example in a thumbprint input device, may use flip-flop 229 to store the results of a thumbprint scan.Communications device 230 might be, for example, an Ethernet adapter which may use flip-flop 231 to store the results of a received packet. - FIG. 3 is a circuit diagram of an embodiment of a flip-flop. Flip-
flop 300, has aData input 301 to receive data. TheData input 301 is connected to the gate of a P-type transistor 302 and the gate of an N-type transistor 312. The source oftransistor 302 is connected to a positive power supply Vcc. The source oftransistor 312 is connected to a less positive power supply than Vcc, designated as ground by the ground symbol. The drain oftransistor 302 is connected to the source of a P-type transistor 304. The drain oftransistor 304 is connected to the source of a P-type transistor 306. The drain oftransistor 306 is connected to the drain of a N-type transistor 308. The source oftransistor 308 is connected to the drain of a N-type transistor 310. The source oftransistor 310 it connected to the drain oftransistor 312. Flip-flop 300, has aclock input 319, denoted Clk, to receive a clock. TheClk input 319 is connected to the input of aninverter 320, and the gate oftransistor 306. The output ofinverter 320 is denoted asClkb 321, and is connected to the input ofinverter 322, and the gate oftransistor 308. The output ofinverter 322, denoted 323, is coupled to the input ofinverter 324. The output ofinverter 324, denotedClkbd 325, is coupled to the input ofinverter 326, and the gate oftransistor 304. The output ofinverter 326, denotedClkd 327, id coupled to the gate oftransistor 310. The drain oftransistor 306 and the drain oftransistor 308 are coupled to thenode 307.Node 307 is coupled to the input ofinverter 314. The output ofinverter 314, denoted as 315, is coupled to the input ofinverter 316. The output ofinverter 316 is coupled to the input ofinverter 314. Thenode 307 is coupled to the input of theinverter 318. The output ofinverter 318, denoted asQ 317, is the output of the flip-flop 300. - FIG. 4 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 3. Operation is illustrated for the flip-
flop 300 when the Data is in a binary high state at the sequence labeled 402, and operation is illustrated for the flip-flop 300 when the Data is in a binary low state at the sequence labeled 404. -
Sequence 402 begins when the Clk signal makes a high to low transition. This Clk high to low transition propagates through the flip-flop circuitry and causes the Clkb low to high transition, the Clkbd low to high transition, the Clkd high to low transition. The Clkb transition from low to high “samples” the Data, which in this example, is in a high state, the result is that the output Q is in a high state. -
Sequence 404 begins when the Clk signal makes a high to low transition. This Clk high to low transition propagates through the flip-flop circuitry and causes the Clkb low to high transition, the Clkbd low to high transition, the Clkd high to low transition. The Clk transition from high to low “samples” the Data, which in this example, is in a low state, the result is that the output Q is in a high low. - Operation of the flip-
flop 300 may be more easily understood by consideringtransistors Data 301, will be transferred at the “gated” output junction of 306 and 308, denoted asnode 307. The signal atnode 307 will be “kept” by the keeper circuit of 314 and 316, and the signal atnode 307 will be buffered byinverter 318 and output asQ 317. When the “gated” inverter is not active, that is, it is no longer actively driving thenode 307 and has entered a high impedance (Hi-Z) state, then theoutput Q 317 will be maintained because the keeper circuit has maintained the state when the “gated” inverter was actively drivingnode 307. - The “gated” inverter is actively driving
node 307 toward a high state when the gates oftransistors signals Data 301,Clkbd 325 andClk 319 respectively, are in a low state. Conversely, the “gated” inverter is actively drivingnode 307 toward a low state when the gates oftransistors signals Clkb 321,Clkd 327, andData 301 respectively, are in a high state. - FIG. 5 is a circuit diagram of another embodiment of a flip-flop. Flip-
flop 500, has aData input 501 to receive data. TheData input 501 is connected to the input of atransmission gate 530. The output oftransmission gate 530, denoted bynode 531, is connected to the input ofinverter 532. The output ofinverter 532, is connected to the input oftransmission gate 534. The output oftransmission gate 534 is coupled to thenode 507.Node 507 is coupled to the input ofinverter 514. The output ofinverter 514, denoted as 515, is coupled to the input ofinverter 516. The output ofinverter 516 is coupled to the input ofinverter 514. Thenode 507 is coupled to the input of theinverter 518. The output ofinverter 518, denoted asQ 517, is the output of the flip-flop 500. Flip-flop 500, has aclock input 519, denoted Clk, to receive a clock. TheClk input 519 is connected to the input of aninverter 520, and the N-type transistor control gate oftransmission gate 534. The output ofinverter 520 is denoted asClkb 521, and is connected to the input ofinverter 522, and the P-type transistor control gate oftransmission gate 534. The output ofinverter 522, denotedClkd 523, is coupled to the P-type transistor control gate oftransmission gate 530. The output ofinverter 524, denoted 5Clkbd 525, is coupled to the N-type transistor control gate oftransmission gate 530. - FIG. 6 is a waveform diagram illustrating the operation of the circuit depicted in FIG. 5. Operation is illustrated for the flip-
flop 500 when the Data is in a binary high state at the sequence labeled 602, and operation is illustrated for the flip-flop 500 when the Data is in a binary low state at the sequence labeled 604. -
Sequence 602 begins when the Clk signal makes a low to high transition. This Clk low to high transition propagates through the flip-flop circuitry and causes the Clkb high to low transition, the Clkd low to high transition, the Clkdb high to low transition. - The Clk transition from low to high “samples” the Data, which in this example, is in a high state, the result is that the output Q is in a high state.
-
Sequence 604 begins when the Clk signal makes a low to high transition. This Clk low to high transition propagates through the flip-flop circuitry and causes the Clkb high to low transition, the Clkd low to high transition, the Clkdb high to low transition. - The Clk transition from low to high “samples” the Data, which in this example, is in a low state, the result is that the output Q is in a high low.
- Operation of the flip-
flop 500 may be more easily understood by consideringtransmission gates Data input 501 signal to pass toinverter 532 and then ontonode 507. As used in this discussion, a transmission gate is considered to be “on” then the transmission gate has a low impedance between the input and output terminals of the transmission gate. Conversely, the transmission gate is considered “off” when there is a high impedance between the input and the output terminals of the transmission gate. TheData input signal 501 will propagate to the input ofinverter 532, denoted asnode 531, when thetransmission gate 530 is on. The signal from the output ofinverter 532 will propagate tonode 507 whentransmission gate 534 is on. The timing of whentransmission gates - In instances where flip-
flop 500 may be operated with a low speed clock signal (Clk) or where the clock signal (Clk) may be stopped or paused, it may be desirable to place a keeper circuit attached tonode 531. Such a keeper circuit may be one as is illustrated by theinverter 514,node 515,inverter 516, and connection tonode 507. The purpose of such a keeper circuit attached tonode 531 would be to maintain the signal transferred whentransmission gate 530 was on but is now off. - Thus, a method and apparatus for flip-flop have been described. Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (27)
1. A flip-flop circuit comprising:
a data signal input to receive a data signal;
a clock signal input to receive a clock signal;
a clocking circuit to generate control clocks;
a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output;
a keeper circuit to receive the output of the multiple input conditional inverter; and
a buffer circuit to receive the output of the multiple input conditional inverter and to generate the flip-flop circuit output.
2. The flip-flop circuit according to claim I, wherein the multiple input conditional inverter further receives the clock signal.
3. The flip-flop circuit according to claim 1 , wherein the clocking circuit receives the clock signal.
4. A flip-flop circuit comprising:
a first transistor, the first transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive an data input signal and the input terminal is coupled to a positive supply voltage;
a second transistor, the second transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a third clock signal and the input terminal is coupled to the output terminal of the first transistor;
a third transistor, the third transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a first clock signal and the input terminal is coupled to the output terminal of the second transistor;
a fourth transistor, the fourth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a second clock signal and the output terminal is coupled to the output terminal of the third transistor;
a fifth transistor, the fifth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a fourth clock signal and the output terminal is coupled to the input terminal of the fourth transistor;
a sixth transistor, the sixth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive the input data signal, the output terminal is coupled to the input terminal of the fifth transistor, and input terminal is coupled to a supply voltage less positive than the positive supply voltage;
a first inverter, the first inverter having an input and an output, wherein the input is coupled to receive the first clock signal;
a second inverter, the second inverter having an input and an output, wherein the input is coupled to the output terminal of the first inverter to receive the second clock signal;
a third inverter, the third inverter having an input and an output, wherein the input is coupled to the output terminal of the second inverter;
a fourth inverter, the fourth inverter having an input and an output, wherein the input is coupled to the output terminal of the third inverter to receive the third clock signal, and the output is coupled to the fourth clock;
a keeper circuit, the keeper circuit having an input and output, wherein the input and output are coupled to the output terminal of the third transistor; and
a buffer, the buffer having an input and an output, wherein the buffer input is coupled to the output terminal of the third transistor, and the buffer output is the flip-flop latched output signal.
5. The flip-flop according to claim 4 , wherein the first clock signal is the flip-flop clock input signal.
6. The flip-flop according to claim 4 , wherein the buffer output has the inverse digital polarity of the data input signal.
7. The flip-flop according to claim 4 , wherein the buffer is an inverter and the inverter output has the same digital polarity as the data input signal.
8. The flip-flop according to claim 4 , wherein the supply voltage less positive than the positive supply voltage is substantially electrical ground.
9. A flip-flop circuit comprising:
a first transmission gate, the first transmission gate having an input terminal, an output terminal, a P control terminal, and an N control terminal, wherein the input terminal is coupled to a data input, the P control terminal is coupled to a third clock signal, and the N control terminal is coupled to a fourth clock signal;
a first inverter, the first inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the first transmission gate output terminal;
a second transmission gate, the second transmission gate having an input terminal, an output terminal, a P control terminal, and an N control terminal, wherein the input terminal is coupled to the first inverter output, the P control terminal is coupled to a second clock signal, and the N control terminal is coupled to a first clock signal;
a keeper circuit, the keeper circuit having an input and an output, wherein the input and output are coupled to the second transmission gate output terminal;
an output circuit, the output circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the second transmission gate output terminal, and the output terminal is the flip-flop output;
a second inverter, the second inverter having an input terminal and an output terminal, the input terminal coupled to a clock signal;
a third inverter, the third inverter having an input terminal and an output terminal, the input terminal coupled to the second inverter output terminal to receive the second clock; and
a fourth inverter, the fourth inverter having an input terminal and an output terminal, the input terminal coupled to the third inverter output terminal to receive the third clock, and the fourth inverter output terminal to generate the fourth clock.
10. The flip-flop according to claim 9 , wherein the first clock signal is the clock signal.
11. The flip-flop according to claim 9 , wherein the buffer output has the inverse digital polarity of the data input.
12. The flip-flop according to claim 9 , wherein the buffer is an inverter and the inverter output has the same digital polarity as the data input.
13. A method for latching an input signal, comprising:
receiving the input signal;
receiving a clock signal;
sampling the input signal;
transferring the sample of the input signal to a keeper circuit upon receiving the clock signal; and
buffering the keeper circuit to generate the latched input signal.
14. The method according to claim 13 , wherein transferring the sample of the input signal comprises:
coupling the input signal to the keeper circuit; and
disconnecting the input signal from the keeper circuit.
15. The method according to claim 14 , wherein the coupling and disconnecting of the input signal to/from the keeper circuit is self-timed.
16. An apparatus for latching an input signal, comprising:
means for receiving the input signal;
means for receiving a clock signal;
means for sampling the input signal;
means for transferring the sample of the input signal to a keeper circuit upon receiving the clock signal; and
means for buffering the keeper circuit to generate the latched input signal.
17. The apparatus according to claim 16 , wherein means for trasferring the sample of the input signal comprises:
means for substantially coupling the input signal to the keeper circuit; and
means for substantially disconnecting the input signal from the keeper circuit.
18. The apparatus according to claim 16 , wherein the means for substantially coupling and disconnecting of the input signal to/from the keeper circuit is a self-timed means.
19. A machine-readable medium having stored thereon instructions, which when executed by a set of processors, cause said set of processors to perform the following:
receive an input signal;
receive a clock signal;
sample the input signal;
transfer the sample of the input signal to a keeper circuit upon receiving the clock signal; and
buffer the keeper circuit to generate a latched output representation of the input signal.
20. The machine-readable medium according to claim 19 , wherein transferring the sample of the input signal comprises:
coupling the input signal to the keeper circuit; and
disconnecting the input signal from the keeper circuit.
21. The machine-readable medium according to claim 20 , wherein the coupling and disconnecting of the input signal tb/from the keeper circuit is self-timed.
22. A processing system comprising:
a processing element;
a clock input;
a data input; and
a flip-flop having a multiple input conditional inverter.
23. The processing system according to claim 22 , wherein the flip-flop comprises:
a first transistor, the first transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive an data input signal and the input terminal is coupled to a positive supply voltage;
a second transistor, the second transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a third clock signal and the input terminal is coupled to the output terminal of the first transistor;
a third transistor, the third transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a first clock signal and the input terminal is coupled to the output terminal of the second transistor;
a fourth transistor, the fourth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a second clock signal and the output terminal is coupled to the output terminal of the third transistor;
a fifth transistor, the fifth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive a fourth clock signal and the output terminal is coupled to the input terminal of the fourth transistor;
a sixth transistor, the sixth transistor having a control terminal, an input terminal, and an output terminal, wherein the control terminal is coupled to receive the input data signal, the output terminal is coupled to the input terminal of the fifth transistor, and input terminal is coupled to a supply voltage less positive than the positive supply voltage;
first inverter, the first inverter having an input and an output, wherein the input is coupled to receive the first clock signal;
second inverter, the second inverter having an input and an output, wherein the input is coupled to the output terminal of the first inverter to receive the second clock signal;
a third inverter, the third inverter having an input and an output, wherein the input is coupled to the output terminal of the second inverter;
a fourth inverter, the fourth inverter having an input and an output, wherein the input is coupled to the output terminal of the third inverter to receive the third clock signal, and the output is coupled to the fourth clock;
a keeper circuit, the keeper circuit having an input and output, wherein the input and output are coupled to the output terminal of the third transistor; and
a buffer, the buffer having an input and an output, wherein the buffer input is coupled to the output terminal of the third transistor, and the buffer output is the flip-flop latched output signal.
24. The processing system according to claim 23 , wherein the flip-flop and the processing element are fabricated on an integrated circuit.
25. A computer based system comprising:
a processing element;
a clock input;
a data input; and
a flip-flop having a plurality of transmission gates and a keeper circuit.
26. The computer based system according to claim 25 , wherein the flip-flop comprises:
a first transmission gate, the first transmission gate having an input terminal, an output terminal, a P control terminal, and an N control terminal, wherein the input terminal is coupled to a data input, the P control terminal is coupled to a third clock signal, and the N control terminal is coupled to a fourth clock signal;
a first inverter, the first inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the first transmission gate output terminal; a second transmission gate, the second transmission gate having an input
terminal, an output terminal, a P control terminal, and an N control terminal, wherein the input terminal is coupled to the first inverter output, the P control terminal is coupled to a second clock signal, and the N control terminal is coupled to a first clock signal;
a keeper circuit, the keeper circuit having an input and an output, wherein the input and output are coupled to the second transmission gate output terminal;
an output circuit, the output circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the second transmission gate output terminal, and the output terminal is the flip-flop output;
a second inverter, the second inverter having an input terminal and an output terminal, the input terminal coupled to a clock signal;
a third inverter, the third inverter having an input terminal and an output terminal, the input terminal coupled to the second inverter output terminal to receive the second clock; and
a fourth inverter, the fourth inverter having an input terminal and an output terminal, the input terminal coupled to the third inverter output terminal to receive the third clock, and the fourth inverter output terminal to generate the fourth clock.
27. The computer based system according to claim 25 , wherein the flip-flop and the processing element are fabricated on an integrated circuit.
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JP3614125B2 (en) * | 2000-10-23 | 2005-01-26 | 三星電子株式会社 | CP flip-flop |
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US6956421B1 (en) * | 2003-07-10 | 2005-10-18 | Intel Corporation | Slave-less edge-triggered flip-flop |
US7429882B2 (en) * | 2006-06-08 | 2008-09-30 | Toshiba America Electronic Components, Inc. | AC-DC input buffer |
KR20090099735A (en) * | 2008-03-18 | 2009-09-23 | 삼성전자주식회사 | Flip-flop capable of high speed operation |
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US5459421A (en) | 1994-03-31 | 1995-10-17 | Intel Corporation | Dynamic-static master slave flip-flop circuit |
US5612632A (en) * | 1994-11-29 | 1997-03-18 | Texas Instruments Incorporated | High speed flip-flop for gate array |
US5656962A (en) | 1994-11-30 | 1997-08-12 | Intel Corporation | Master-slave flip-flop circuit with bypass |
US5557225A (en) | 1994-12-30 | 1996-09-17 | Intel Corporation | Pulsed flip-flop circuit |
US5764089A (en) * | 1995-09-11 | 1998-06-09 | Altera Corporation | Dynamic latching device |
US5774005A (en) * | 1995-09-11 | 1998-06-30 | Advanced Micro Devices, Inc. | Latching methodology |
US6002285A (en) * | 1996-05-28 | 1999-12-14 | International Business Machines Corporation | Circuitry and method for latching information |
US5867049A (en) * | 1996-11-21 | 1999-02-02 | Sun Microsystems, Inc. | Zero setup time flip flop |
US5917355A (en) * | 1997-01-16 | 1999-06-29 | Sun Microsystems, Inc. | Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism |
US5939915A (en) * | 1997-08-06 | 1999-08-17 | International Business Machines Corporation | Noise-immune pass gate latch |
US6204708B1 (en) * | 1998-10-29 | 2001-03-20 | Microchip Technology Incorporated | Apparatus and method for an improved master-slave flip-flop with non-overlapping clocks |
US6181180B1 (en) * | 1999-06-28 | 2001-01-30 | Intel Corporation | Flip-flop circuit |
-
2000
- 2000-06-29 US US09/608,687 patent/US6369631B1/en not_active Expired - Lifetime
-
2001
- 2001-06-04 US US09/874,866 patent/US6366147B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7191975B2 (en) | 2018-03-30 | 2022-12-19 | アイデックス ラボラトリーズ インコーポレイテッド | Flow cytometer, its laser optic assembly, and method of assembling the laser optic assembly |
Also Published As
Publication number | Publication date |
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US6369631B1 (en) | 2002-04-09 |
US6366147B2 (en) | 2002-04-02 |
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