US20010051401A1 - Production of a semiconductor device - Google Patents
Production of a semiconductor device Download PDFInfo
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- US20010051401A1 US20010051401A1 US09/876,072 US87607201A US2001051401A1 US 20010051401 A1 US20010051401 A1 US 20010051401A1 US 87607201 A US87607201 A US 87607201A US 2001051401 A1 US2001051401 A1 US 2001051401A1
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- insulation film
- gate insulation
- region
- forming
- indium
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000009413 insulation Methods 0.000 claims abstract description 98
- 229910052738 indium Inorganic materials 0.000 claims abstract description 64
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 230000000694 effects Effects 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 12
- 230000006866 deterioration Effects 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Definitions
- This invention relates to a process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed thereon and a N-channel region formed in the predetermined MOSFET region thereof using indium, in particular to the process for preparing a semiconductor device that is capable of implanting indium effectively.
- boron that has large re-distributed amount of impurities is being replaced by another element such as indium that has large atomic weight, small amount of diffusion and small re-distributed amount of impurities.
- a SOC System On a Chip
- MOSFET MOSFET for use in a portion of a core region
- MOSFET for low electric power use MOSFET for use in a peripheral input/output circuit
- high 5 density MOSFET for use in a high speed SRAM (Static Random Access Memory) on one semiconductor chip.
- RTP Rapid Thermal Process
- a gate insulation film with different levels of thickness In order to form a gate insulation film with different levels of thickness, techniques such as thermal oxidation using an oxidation furnace for forming a gate insulation film of a MOSFET for use in a portion of an I/O (Input/Output) region, RTP (Rapid Thermal Process) for forming a gate insulation film of a MOSFET for use in a portion of a core region are adopted.
- RTP includes, for example, a process including the steps of annealing at predetermined temperature (e.g., 800° C.) for predetermined period of time (e.g., 1 minute) using NH 3 gas.
- indium has such a property that it is easy to be absorbed out of a channel region into the gate insulation film in case of forming a gate insulation film applying thermal oxidation. As a result, such a problem will occur that effects imparted by indium are lowered though indium ion implantation has been done with considerable effort.
- An object of the present invention is to provide a process for preparing a semiconductor device which is capable of forming micro-devices of, e.g., 0.1 ⁇ m or less using indium and at the same time implanting indium effectively during the process of forming a gate insulation film with different levels of thickness.
- a process is directed for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region and thereafter forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask and thereafter forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, (4) 4th step of forming a P-well region inside theist gate insulation film partially removed region and thereafter forming a
- the thickness of the 2nd gate insulation film is thinner than that of the 1st gate insulation film.
- the 2nd gate insulation film is formed by RTP.
- a process is directed for preparing a semiconductor device having a gate insulation films with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the gate insulation film, thereafter, forming a P-well region in the predetermined region except the 1st N-channel region through the gate insulation film before forming a 2nd N-channel region containing indium on this
- the thickness of the gate insulation film on the 2nd N-channel region is 20 ⁇ or less.
- FIGS. 1 (A) to (D) fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 1 of the present invention
- FIGS. 4 (A) to (C) fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 2 of the present invention
- a process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, (4) 4th step of forming a P-well region inside the region in which the 1st gate insulation film is removed before forming a 2nd N-channel region containing indium on
- FIGS. 1 and 2 are a fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 1 of the present invention.
- an element isolation region 2 is formed on a P-type silicon substrate (cf. FIG. 1(A)).
- a resist pattern is formed applying photoresist (formation of a resist mask 10 ), and then 2 ⁇ 10 13 /cm 2 of P-type impurities such as boron undergo ion implantation in a region for forming a NMOSFET for use in a portion of an I/O region (hereinafter shortened as “for I/O use”) at 150 keV to form a P-well region 3 . Thereafter 1 ⁇ 10 13 /cm 2 of P-type impurities such as boron undergo ion implantation at 30 keV before forming a N-channel region 4 (cf. FIG. 1(B)).
- the resist mask 10 is exfoliated, and then the surface is washed before forming a thick gate insulation film of 26 ⁇ in thickness designed to be used for I/O over the surface by thermal oxidation (cf. FIG. 1( c )).
- a resist pattern is formed applying photoresist (formation of a resist mask 20 ), and then the gate insulation film existing on the region for forming a NMOSFET for use in a portion of a core region (hereinafter shortened as “for core use”) is removed by wet etching (cf. FIG. 1(D)).
- the resist mask 20 is exfoliated, and then the surface is washed before forming a gate insulation film of 16 ⁇ in thickness over the surface by RTP (Rapid Thermal Process). Accordingly, a MOSFET having a gate insulation film with different levels of thickness is formed in such a way that a gate insulation film 5 is made thick in the region of a NMOSFET for I/O use, and at the same time that gate insulation film 10 is made thin in the region of a NMOSFET for core use (cf. FIG. 2(F)).
- a gate electrode 9 of about 1,500 ⁇ in thickness made of polysilicon or the like is formed by CVD (Chemical Vapor Deposition) (cf. FIG. 2(G)).
- indium is never absorbed into the gate insulation film for I/O use, thereby the deterioration of effects taken by the use of indium can be prevented by ion-implanting indium into the region of a NMOSFET for core use after forming a gate insulation film for I/O use by thermal oxidation.
- indium is never absorbed into the gate insulation film 5 through the thermal oxidation process. As a result, the deterioration of the effects taken by the use of indium can be prevented.
- FIGS. 3 and 4 are a partially sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 2 of the present invention.
- an element isolation region 2 is formed on a P-type silicon substrate (cf. FIG. 3(A)).
- a resist pattern is formed applying photoresist (formation of a resist mask 10 ), then 2 ⁇ 10 13 /cm 2 of P-type impurities such as boron undergo ion implantation in a region for forming a NMOSFET for I/O use at 150 keV to form a P-well region 3 . Thereafter 1 ⁇ 10 13 /cm 2 of P-type impurities such as boron undergo ion implantation at 30 keV before forming a N-channel region 4 (cf. FIG. 3(B)).
- the resist mask 10 is exfoliated, and then the surface is washed before forming a thick gate insulation film of 26 ⁇ in thickness designed to be used for I/O over the surface by thermal oxidation (cf. FIG. 3( c )).
- the same procedures of Example 1 are repeated until here.
- a resist pattern is formed (formation of a resist mask 20 ), then 2 ⁇ 10 13 /cm 2 of P-type impurities such as boron undergo ion implantation through the gate insulation film 5 formed on the occasion of forming the NMOSFET for core use to form a P-well region 6 before ion-implanting 1 ⁇ 10 13 /cm 2 of P-type impurity of indium at 30 keV to form a N-channel region 7 (cf. FIG. 3(D)).
- the gate insulation film 5 functions as a through insulation film in this way, such an advantage that the surface of a device can be protected from metallic pollution caused in an ion implantation apparatus.
- the gate insulation film 5 on the region for forming a NMOSFET for core use undergoes wet etching with the resist mask left, and a part of the gate insulation film 5 is thinly removed thereby (cf. FIG. 4(E)).
- Example 2 on the occasion of forming a N-channel region in a MOSFET having a gate insulation film with different levels of thickness formed thereon using indium correspondingly to respective MOSFET's such as MOSFET for core use and MOSFET for I/O use, indium undergoes ion implantation into the region of a NMOSFET for core use through the gate insulation film after forming a gate insulation film I/O use by thermal oxidation. Thereby, indium is never absorbed into the gate insulation film for I/O use. Accordingly, the deterioration of effects taken by the use of indium can be prevented, and at the same time the surface of a device can be protected from metallic pollution caused in an ion implantation apparatus.
- FIG. 5 is a fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to the example of the conventional process.
- the P-well region 103 and the N-channel region 104 of a NMOSFET for I/O use as well as the P-well region 106 and the indium N-channel region 107 of a NMOSFET for core use were formed applying photoresist two times (cf. FIG. 5(A)).
- a thick gate insulation film of 26 ⁇ in thickness designed to be used for I/O is formed on the whole surface of a silicon substrate by thermal oxidation (cf. FIG. 5(B)).
- thermal oxidation cf. FIG. 5(B)
- indium contained in the indium N-channel region is absorbed into the gate insulation film, thereby the concentration of indium becomes decreased to deteriorate the indium effects in the indium N-channel region.
- a resist pattern (resist mask 110 ) is formed applying photoresist before removing the gate insulation film in the region of the NMOSFET for core use by wet etching (cf. FIG. 5(C)).
- a thin gate insulation film 108 of 16 ⁇ is formed over the surface by RTP (FIG. 5(D)).
- a thin gate insulation film of 16 ⁇ is formed in the NMOSFET region for core use, and a thick gate insulation film 105 is formed in the NMOSFET region for I/O use.
- a polysilicon layer 109 designed to be used for a gate electrode is deposited by CVD (cf. FIG. 5(E)), and subsequent procedures after that are the same with those found in the examples of the present invention.
- the conventional method causes the absorption of indium existing in the indium N-channel region 107 into the gate insulation film 105 on the occasion of forming a gate insulation film 105 shown in FIG. 5(B) by thermal oxidation using a furnace or the like. As a result, the channel concentration of indium in the indium N-channel region is decreased and indium effects are deteriorated thereby.
- Example 1 of the present invention indium is implanted after forming the gate insulation film 5 (FIG. 1(D) to FIG. 2(E)) so that indium is never absorbed into the gate insulation film because there is no indium existing also during the period of forming a gate insulation film in an oxidation furnace. This holds true for Example 2.
- indium is not absorbed into the gate insulation film for I/O use by ion-implanting indium into a NMOSFET region for core use after forming a gate insulation film for I/O use, and the deterioration of effects taken by the use of indium can be prevented.
- gate insulation film as a through insulation film makes it possible to protect the surface of a device from metallic pollution.
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Abstract
Description
- This invention relates to a process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed thereon and a N-channel region formed in the predetermined MOSFET region thereof using indium, in particular to the process for preparing a semiconductor device that is capable of implanting indium effectively.
- With the miniaturization of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the necessity of forming super-micro devices of such sizes that are 0.1 μm or less arises. Accompanied by this event, how to restrain the deterioration of short channel properties such as forward and reverse short channel effects conspicuously appearing in proportion to the miniaturization is in problem. The reverse short channel effect appears resulting from the re-distribution of channel impurity concentration induced by diffusion. On account of this, as for a channel impurity in a NMOSFET, boron that has large re-distributed amount of impurities is being replaced by another element such as indium that has large atomic weight, small amount of diffusion and small re-distributed amount of impurities.
- On the other hand, along with the miniaturization of the MOSFET, a SOC (System On a Chip) process for mounting various MOSFET's each having a gate insulation film of different thickness from each other such as MOSFET for use in a portion of a core region, MOSFET for low electric power use, MOSFET for use in a peripheral input/output circuit, high5 density MOSFET for use in a high speed SRAM (Static Random Access Memory) on one semiconductor chip. In order to form a gate insulation film with different levels of thickness, techniques such as thermal oxidation using an oxidation furnace for forming a gate insulation film of a MOSFET for use in a portion of an I/O (Input/Output) region, RTP (Rapid Thermal Process) for forming a gate insulation film of a MOSFET for use in a portion of a core region are adopted. Here, RTP includes, for example, a process including the steps of annealing at predetermined temperature (e.g., 800° C.) for predetermined period of time (e.g., 1 minute) using NH3 gas.
- However, there is much desired in the art. Namely indium has such a property that it is easy to be absorbed out of a channel region into the gate insulation film in case of forming a gate insulation film applying thermal oxidation. As a result, such a problem will occur that effects imparted by indium are lowered though indium ion implantation has been done with considerable effort.
- An object of the present invention is to provide a process for preparing a semiconductor device which is capable of forming micro-devices of, e.g., 0.1 μm or less using indium and at the same time implanting indium effectively during the process of forming a gate insulation film with different levels of thickness.
- In a first aspect of the present invention, a process is directed for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region and thereafter forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask and thereafter forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, (4) 4th step of forming a P-well region inside theist gate insulation film partially removed region and thereafter forming a 2nd N-channel region containing indium on this P-well region, and (5) 5th step of removing the 2nd resist mask and thereafter forming a 2nd gate insulation film on the surface of the 2nd N-channel region.
- In the above process, it is preferable that the thickness of the 2nd gate insulation film is thinner than that of the 1st gate insulation film.
- It is also preferable in the above process that the 2nd gate insulation film is formed by RTP.
- In a second aspect of the present invention, a process is directed for preparing a semiconductor device having a gate insulation films with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the gate insulation film, thereafter, forming a P-well region in the predetermined region except the 1st N-channel region through the gate insulation film before forming a 2nd N-channel region containing indium on this P-well region; and (4) 4th step of removing thinly the surface of the gate insulation film formed on the 2nd N-channel region.
- It is preferable with regard to the aforementioned processes that the thickness of the gate insulation film on the 2nd N-channel region is 20 Å or less.
- FIGS.1(A) to (D): fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 1 of the present invention
- FIGS.2(A) to (C): fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 1 of the present invention
- FIGS.3(A) to (D): fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 2 of the present invention
- FIGS.4(A) to (C): fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 2 of the present invention
- FIGS.5(A) to (E): fragmentary sectional view showing schematically the steps of one conventional process for preparing a semiconductor device
- When a process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, (4) 4th step of forming a P-well region inside the region in which the 1st gate insulation film is removed before forming a 2nd N-channel region containing indium on this P-well region, and (5) 5th step of removing the 2nd resist mask before forming a 2nd gate insulation film on the surface of the 2nd N-channel region, indium absorbed into the gate insulation films can be minimized to prevent the deterioration of indium effects.
- Taking a device using a N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) prepared according to 0.1 μm design rule and driven at source voltage Vdd=1.2V as a NMOSFET for use in a portion of a core region and having NMOSFET for use in a portion of a peripheral I/O (Input/Output) region and NMOSFET having a gate insulation film with different levels of thickness formed thereon as an example, an example of the present invention will be explained below in reference to the accompanying Drawings. FIGS. 1 and 2 are a fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 1 of the present invention.
- At first, according to the conventional process, an
element isolation region 2 is formed on a P-type silicon substrate (cf. FIG. 1(A)). - Next, a resist pattern is formed applying photoresist (formation of a resist mask10), and then 2×1013/cm2 of P-type impurities such as boron undergo ion implantation in a region for forming a NMOSFET for use in a portion of an I/O region (hereinafter shortened as “for I/O use”) at 150 keV to form a P-
well region 3. Thereafter 1×1013/cm2 of P-type impurities such as boron undergo ion implantation at 30 keV before forming a N-channel region 4 (cf. FIG. 1(B)). - Next, the
resist mask 10 is exfoliated, and then the surface is washed before forming a thick gate insulation film of 26 Å in thickness designed to be used for I/O over the surface by thermal oxidation (cf. FIG. 1(c)). - Next, a resist pattern is formed applying photoresist (formation of a resist mask20), and then the gate insulation film existing on the region for forming a NMOSFET for use in a portion of a core region (hereinafter shortened as “for core use”) is removed by wet etching (cf. FIG. 1(D)).
- After that, 2×1013/cm2 of P-type impurities such as boron undergo ion implantation at 150 keV to form a P-
well region 6, and further 1×1013/cm2 of P-type impurity of indium undergoes ion implantation at 30 keV to form a N-channel region 7 (cf. FIG. 2(E)). - Next, the
resist mask 20 is exfoliated, and then the surface is washed before forming a gate insulation film of 16 Å in thickness over the surface by RTP (Rapid Thermal Process). Accordingly, a MOSFET having a gate insulation film with different levels of thickness is formed in such a way that agate insulation film 5 is made thick in the region of a NMOSFET for I/O use, and at the same time thatgate insulation film 10 is made thin in the region of a NMOSFET for core use (cf. FIG. 2(F)). - Next, a
gate electrode 9 of about 1,500 Å in thickness made of polysilicon or the like is formed by CVD (Chemical Vapor Deposition) (cf. FIG. 2(G)). - Subsequent steps and also steps for forming a P-channel are the same with conventional ones.
- In forming a N-channel region in a MOSFET having a gate insulation film with different levels of thickness formed thereon using indium correspondingly to respective MOSFET's such as MOSFET for core use and MOSFET for I/O use, indium is never absorbed into the gate insulation film for I/O use, thereby the deterioration of effects taken by the use of indium can be prevented by ion-implanting indium into the region of a NMOSFET for core use after forming a gate insulation film for I/O use by thermal oxidation.
- In short, by virtue of ion implantation of indium after forming a
gate insulation film 5 shown in FIG. 1(C), indium is never absorbed into thegate insulation film 5 through the thermal oxidation process. As a result, the deterioration of the effects taken by the use of indium can be prevented. - Next, another example of the present invention will be explained below with reference to the attached drawings. Here, the example of the present invention will be illustrated taking a NMOSFET having NMOSFET for core use and NMOSFET for I/O use each having a gate insulation film of different thickness from each other mounted thereon. FIGS. 3 and 4 are a partially sectional view showing schematically the steps of a process for preparing a semiconductor device according to Example 2 of the present invention.
- At first, according to the conventional process, an
element isolation region 2 is formed on a P-type silicon substrate (cf. FIG. 3(A)). - Next, a resist pattern is formed applying photoresist (formation of a resist mask10), then 2×1013/cm2 of P-type impurities such as boron undergo ion implantation in a region for forming a NMOSFET for I/O use at 150 keV to form a P-
well region 3. Thereafter 1×1013/cm2 of P-type impurities such as boron undergo ion implantation at 30 keV before forming a N-channel region 4 (cf. FIG. 3(B)). - Next, the
resist mask 10 is exfoliated, and then the surface is washed before forming a thick gate insulation film of 26 Å in thickness designed to be used for I/O over the surface by thermal oxidation (cf. FIG. 3(c)). The same procedures of Example 1 are repeated until here. - Next, a resist pattern is formed (formation of a resist mask20), then 2×1013/cm2 of P-type impurities such as boron undergo ion implantation through the
gate insulation film 5 formed on the occasion of forming the NMOSFET for core use to form a P-well region 6 before ion-implanting 1×1013/cm2 of P-type impurity of indium at 30 keV to form a N-channel region 7 (cf. FIG. 3(D)). In case that thegate insulation film 5 functions as a through insulation film in this way, such an advantage that the surface of a device can be protected from metallic pollution caused in an ion implantation apparatus. - Next, the
gate insulation film 5 on the region for forming a NMOSFET for core use undergoes wet etching with the resist mask left, and a part of thegate insulation film 5 is thinly removed thereby (cf. FIG. 4(E)). - Next, the resist mask is removed and the whole surface is washed (cf. FIG. 4(F)) before forming a
gate electrode 9 of about 1,500 Å in thickness made of polysilicon or the like by CVD (Chemical Vapor Deposition) (cf. FIG. 4(G)). Subsequent steps and also steps for forming a P-channel are the same with conventional ones. - In this Example 2, on the occasion of forming a N-channel region in a MOSFET having a gate insulation film with different levels of thickness formed thereon using indium correspondingly to respective MOSFET's such as MOSFET for core use and MOSFET for I/O use, indium undergoes ion implantation into the region of a NMOSFET for core use through the gate insulation film after forming a gate insulation film I/O use by thermal oxidation. Thereby, indium is never absorbed into the gate insulation film for I/O use. Accordingly, the deterioration of effects taken by the use of indium can be prevented, and at the same time the surface of a device can be protected from metallic pollution caused in an ion implantation apparatus.
- In short, by virtue of ion-implanting indium through the gate insulation film after forming a
gate insulation film 5 shown in FIG. 1(C), indium is never absorbed into thegate insulation film 5 through the thermal oxidation process. As a result, the deterioration of the indium effects can be prevented. - Next, the examples of the present invention will be compared with the conventional process in reference to the accompanying drawings. Here, a process for preparing a semiconductor device having a gate insulation film with different levels of thickness in such manners that NMOSFET for I/O use in and NMOSFET for core use have is taken as an example of the conventional process. FIG. 5 is a fragmentary sectional view showing schematically the steps of a process for preparing a semiconductor device according to the example of the conventional process.
- Conventionally, the P-
well region 103 and the N-channel region 104 of a NMOSFET for I/O use as well as the P-well region 106 and the indium N-channel region 107 of a NMOSFET for core use were formed applying photoresist two times (cf. FIG. 5(A)). - Next, a thick gate insulation film of 26 Å in thickness designed to be used for I/O is formed on the whole surface of a silicon substrate by thermal oxidation (cf. FIG. 5(B)). During this period of time, indium contained in the indium N-channel region is absorbed into the gate insulation film, thereby the concentration of indium becomes decreased to deteriorate the indium effects in the indium N-channel region.
- Next, a resist pattern (resist mask110) is formed applying photoresist before removing the gate insulation film in the region of the NMOSFET for core use by wet etching (cf. FIG. 5(C)).
- After exfoliating the resist
mask 110, a thin gate insulation film 108 of 16 Å is formed over the surface by RTP (FIG. 5(D)). Thereby, a thin gate insulation film of 16 Å is formed in the NMOSFET region for core use, and a thickgate insulation film 105 is formed in the NMOSFET region for I/O use. - Next, a
polysilicon layer 109 designed to be used for a gate electrode is deposited by CVD (cf. FIG. 5(E)), and subsequent procedures after that are the same with those found in the examples of the present invention. - As is evident from the above, the conventional method causes the absorption of indium existing in the indium N-
channel region 107 into thegate insulation film 105 on the occasion of forming agate insulation film 105 shown in FIG. 5(B) by thermal oxidation using a furnace or the like. As a result, the channel concentration of indium in the indium N-channel region is decreased and indium effects are deteriorated thereby. - On the other hand, in Example 1 of the present invention, indium is implanted after forming the gate insulation film5 (FIG. 1(D) to FIG. 2(E)) so that indium is never absorbed into the gate insulation film because there is no indium existing also during the period of forming a gate insulation film in an oxidation furnace. This holds true for Example 2.
- The meritorious effects of the present invention are summarized as follows.
- According to the present invention, in forming a N-channel region in a MOSFET having a gate insulation film with different levels of thickness formed thereon using indium correspondingly to respective MOSFET's such as MOSFET for core use and MOSFET for I/O use, indium is not absorbed into the gate insulation film for I/O use by ion-implanting indium into a NMOSFET region for core use after forming a gate insulation film for I/O use, and the deterioration of effects taken by the use of indium can be prevented.
- In brief, there is no absorption of indium into the gate insulation film resulting from thermal oxidation process because of ion-implanting indium after forming a gate insulation film. Accordingly, the deterioration of indium effects can be inhibited.
- In addition, use of the gate insulation film as a through insulation film makes it possible to protect the surface of a device from metallic pollution.
- It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
- Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items might fall under the modifications aforementioned.
Claims (7)
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JP2000174075A JP2001351987A (en) | 2000-06-09 | 2000-06-09 | Manufacturing method of semiconductor device |
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US6362059B2 US6362059B2 (en) | 2002-03-26 |
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KR100399356B1 (en) * | 2001-04-11 | 2003-09-26 | 삼성전자주식회사 | Method of forming cmos type semiconductor device having dual gate |
JP4540993B2 (en) | 2004-01-20 | 2010-09-08 | パナソニック株式会社 | Manufacturing method of semiconductor device |
US7309629B2 (en) | 2002-01-02 | 2007-12-18 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
JP3506694B1 (en) * | 2002-09-02 | 2004-03-15 | 沖電気工業株式会社 | MOSFET device and manufacturing method thereof |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
FR2847077B1 (en) * | 2002-11-12 | 2006-02-17 | Soitec Silicon On Insulator | SEMICONDUCTOR COMPONENTS, PARTICULARLY OF THE MIXED SOI TYPE, AND METHOD OF MAKING SAME |
KR100496551B1 (en) * | 2002-11-20 | 2005-06-22 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
US6946349B1 (en) * | 2004-08-09 | 2005-09-20 | Chartered Semiconductor Manufacturing Ltd. | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses |
KR100827435B1 (en) * | 2006-01-31 | 2008-05-06 | 삼성전자주식회사 | Method of fabricating gate with oxygen free ashing process in semiconductor device |
US9373501B2 (en) * | 2013-04-16 | 2016-06-21 | International Business Machines Corporation | Hydroxyl group termination for nucleation of a dielectric metallic oxide |
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US6080682A (en) * | 1997-12-18 | 2000-06-27 | Advanced Micro Devices, Inc. | Methodology for achieving dual gate oxide thicknesses |
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