US20010050414A1 - Semiconductor device and method of making same - Google Patents
Semiconductor device and method of making same Download PDFInfo
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- US20010050414A1 US20010050414A1 US09/354,742 US35474299A US2001050414A1 US 20010050414 A1 US20010050414 A1 US 20010050414A1 US 35474299 A US35474299 A US 35474299A US 2001050414 A1 US2001050414 A1 US 2001050414A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims description 61
- 229910010272 inorganic material Inorganic materials 0.000 claims description 12
- 239000011147 inorganic material Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 239000011368 organic material Substances 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- GUHKMHMGKKRFDT-UHFFFAOYSA-N 1785-64-4 Chemical compound C1CC(=C(F)C=2F)C(F)=C(F)C=2CCC2=C(F)C(F)=C1C(F)=C2F GUHKMHMGKKRFDT-UHFFFAOYSA-N 0.000 claims description 3
- 239000004952 Polyamide Substances 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical group C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 3
- 229920002647 polyamide Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 13
- 238000010008 shearing Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000007530 organic bases Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- the present invention relates generally to the formation and construction of semiconductor devices and, more particularly, to enhancing the integrity of mechanically weak dielectric substrate layers so that interfaces between such substrate layers and hard mask layer or circuitry layers can withstand subsequently applied chemical-mechanical polishing forces.
- FIGS. 1 through 4 which illustrate various stages in the conventional formation of semiconductor devices
- a hard mask layer 10 typically silicon based
- a dielectric substrate layer 12 typically carbon based
- a photomask 14 is formed on the top surface of hard mask layer 10 as illustrated in FIG. 1.
- a pattern is formed in photomask 14 (a step not illustrated), typically by lithography.
- Recesses 16 are etched, using the pattern of photomask 14 , through hard mask layer 10 and into dielectric substrate layer 12 . Recesses 16 extend only partially through dielectric substrate layer 12 , as illustrated in FIG. 2, when intended for lines and extend completely through dielectric substrate layer 12 when intended for vias.
- a metallic layer 18 is applied, for example by dipping, over hard mask layer 10 and to the walls and bottom surfaces of recesses 16 .
- the resulting structure is illustrated in FIG. 3.
- those portions of metallic layer 18 on top of hard mask layer 10 are removed by chemical-mechanical polishing (CMP).
- CMP chemical-mechanical polishing
- New, organic, low dielectric constant substrate materials typically require an inorganic hard mask layer for protection from chemical-mechanical polishing damage.
- a large, lateral interface between the organic material substrate layer and inorganic material hard mask layer is typically weak and, as indicated above, often cannot withstand chemical-mechanical polishing forces which are applied subsequent to metalization to remove the metallic circuitry layer above the hard mask.
- An object of the present invention is to provide a semiconductor device and a method of manufacture able to withstand chemical-mechanical polishing forces applied during manufacture.
- a related object is to enhance the mechanical integrity of the dielectric substrate component of a semiconductor device.
- the present invention provides a method for forming semiconductor devices.
- the method includes the steps of providing a substrate and applying a photomask to the substrate. Next, a selected thickness of selected parts of the substrate is removed by etching. After the photomask is removed, a cap dielectric layer is deposited onto the substrate with portions of the cap dielectric layer extending into spaces in the substrate from which parts of the substrate have been etched.
- a semiconductor device constructed in accordance with the present invention, includes a substrate having recesses extending inwardly from a surface of the substrate and a cap dielectric layer against the substrate having portions extending into the recesses in the substrate.
- FIGS. 1 through 4 show various stages in the conventional formation of semiconductor devices and, in particular, FIG. 1 illustrates a semiconductor device following the sequential formation of a photomask over a hard mask layer over a dielectric substrate layer;
- FIG. 2 illustrates the device of FIG. 1 after recesses are etched, using the pattern of the photomask, through the hard mask layer and into the dielectric substrate layer;
- FIG. 3 illustrates the device of FIG. 2 after the photomask is removed and a metallic layer is applied over the hard mask layer and to the walls and bottom surfaces of the recesses;
- FIG. 4 illustrates the device of FIG. 3 after those portions of the metallic layer on top of the hard mask layer are removed
- FIGS. 5 through 7 show various stages in the formation of semiconductor devices in accordance with a first embodiment of the present invention and, in particular, FIG. 5 illustrates a substrate (having a base dielectric layer and a hard mask) with a photomask applied to the substrate and a selected thickness of selected parts of the substrate removed by etching;
- FIG. 6 illustrates the device of FIG. 5 after the photomask is removed
- FIG. 7 illustrates the device of FIG. 6 after a cap dielectric layer is deposited onto the substrate
- FIGS. 8 through 10 show various stages in the formation of semiconductor devices in accordance with a second embodiment of the present invention and, in particular, FIG. 8 illustrates a base dielectric layer substrate with a photomask applied to the substrate and a selected thickness of selected parts of the substrate removed by etching;
- FIG. 9 illustrates the device of FIG. 8 after the photomask is removed.
- FIG. 10 illustrates the device of FIG. 9 after a cap dielectric layer is deposited onto the substrate.
- a semiconductor device constructed in accordance with a first embodiment of the present invention is formed as follows.
- a substrate having a base dielectric layer 30 and a hard mask 22 is provided and a photomask 24 is applied to the substrate.
- photomask 24 is applied to hard mask 22 .
- Base dielectric layer 30 can be an organic material (such as benzocyclobutanes, parylene-N, parylene-F, or polyamides) or an inorganic material (such as inorganic xerogels, SiCOH, hexametholsylsesquoixane, fluorinated spin-on glass, or spin-on glass).
- Hard mask 22 can be SiCOH, SiN, or SiO 2 .
- Photomask 24 can be a photosensitive polymer. A metal can be used but must be removed before subsequent layers are formed.
- a selected thickness of selected parts of the substrate is removed by etching.
- the etched parts of the substrate are in the form of recesses 26 in an inactive part of the semiconductor device being formed and extend completely through hard mask 22 and partially through base dielectric layer 30 .
- base dielectric layer 30 is etched in a pure oxygen-Ar mixture with at least 3:1 etch selectivity between an organic base dielectric layer and the silicon-containing photomask 24 .
- the thickness of photomask 24 preferably is less than the thickness of organic base dielectric layer 30 and the etch preferably should remove less than one-half of the total thickness of base dielectric layer 30 to achieve the desired vertical adhesion enhancement effect to be described below.
- Photomask 24 is removed.
- Photomask 24 can be removed with an acid wash, a solvent cleaning procedure, or both or by using a fluorine-based chemistry reactive ion etch, which might result in a ten percent change in the mask lateral dimension.
- the structure that results after photomask 24 is removed is illustrated in FIG. 6.
- cap dielectric layer 28 is deposited onto the substrate. Portions of cap dielectric layer 28 extend into the spaces (i.e., recesses 26 ) in the substrate from which parts of the substrate have been etched. For the embodiment of the invention being described, cap dielectric layer 28 is deposited onto hard mask 22 . The resulting structure is illustrated in FIG. 7.
- Cap dielectric layer 28 can be a spin-on glass (e.g., fluorinated oxide). Cap dielectric layer 28 typically is spun onto hard mask 22 to 300-500 ⁇ and as much as 5,000 ⁇ above the top surface of hard mask 22 . By using a liquid dielectric, cap dielectric layer 28 is locally planar in the areas that will be patterned. Cap dielectric layer 28 can serve as a hard mask (thin layer) or as the second dual damascene layer (thicker layer) for a dual damascene sequence.
- a spin-on glass e.g., fluorinated oxide
- cap dielectric layer 28 can be an inorganic material, such as SiN, SiCOH, SiO 2 , or spin-on glass, when the base dielectric material is an organic material.
- a semiconductor device constructed in accordance with a second embodiment of the present invention is formed as follows.
- a substrate comprising a base dielectric layer 40 is provided with a photomask 42 that is applied directly to base dielectric layer 40 .
- the substrate does not have a hard mask applied to base dielectric layer 40 .
- a selected thickness of selected parts of base dielectric layer 40 is removed by etching.
- the etched parts of the substrate are in the form of recesses 44 in an inactive part of the semiconductor device being formed and extend partially through base dielectric layer 40 .
- cap dielectric layer 46 is deposited onto the substrate with portions of cap dielectric layer 46 extending into the spaces (i.e., recesses 44 ) in base dielectric layer 40 from which parts of base dielectric layer 40 have been etched.
- cap dielectric layer 46 is deposited directly onto base dielectric layer 40 and functions as a hard mask.
- Cap dielectric layer 46 can be inorganic material, such as Dow Chemical Fox, 650F, when base dielectric layer 40 is an organic material.
- base dielectric layer 40 at an inactive part of the semiconductor device, whereby adhesion to the base dielectric layer is enhanced by the interlock of the parts of cap dielectric layer 46 and recesses 44 in base dielectric layer 40 .
- the interlock between base dielectric layer 40 and cap dielectric layer 46 enhances the resistance to shearing or tearing away as a metallic circuitry layer (not shown in FIG. 10 but which is deposited over cap dielectric layer 46 ) is subjected to chemical-mechanical polishing.
Abstract
Description
- The present invention relates generally to the formation and construction of semiconductor devices and, more particularly, to enhancing the integrity of mechanically weak dielectric substrate layers so that interfaces between such substrate layers and hard mask layer or circuitry layers can withstand subsequently applied chemical-mechanical polishing forces.
- Referring to FIGS. 1 through 4, which illustrate various stages in the conventional formation of semiconductor devices, a
hard mask layer 10, typically silicon based, is deposited on adielectric substrate layer 12, typically carbon based. Next, aphotomask 14 is formed on the top surface ofhard mask layer 10 as illustrated in FIG. 1. A pattern is formed in photomask 14 (a step not illustrated), typically by lithography. Recesses 16 are etched, using the pattern ofphotomask 14, throughhard mask layer 10 and intodielectric substrate layer 12. Recesses 16 extend only partially throughdielectric substrate layer 12, as illustrated in FIG. 2, when intended for lines and extend completely throughdielectric substrate layer 12 when intended for vias. - After
photomask 14 is removed, ametallic layer 18 is applied, for example by dipping, overhard mask layer 10 and to the walls and bottom surfaces of recesses 16. The resulting structure is illustrated in FIG. 3. Next, those portions ofmetallic layer 18 on top ofhard mask layer 10 are removed by chemical-mechanical polishing (CMP). The resulting structure is illustrated in FIG. 4. - The lateral forces, applied during chemical-mechanical polishing, are transferred as shear forces to the interface20 between
hard mask layer 10 anddielectric substrate layer 12. Such shear forces tend to cause separation ofhard mask layer 10 fromdielectric substrate layer 12. It should be noted that similar shearing or tearing problems can arise during chemical-mechanical polishing when the semiconductor device is formed without a hard mask layer (i.e., when the metallic circuitry layer is applied directly to the substrate). The exposure ofdielectric substrate layer 12 to the chemical solution used during chemical-mechanical polishing can have adverse effects on the nature and character ofdielectric substrate layer 12. - New, organic, low dielectric constant substrate materials typically require an inorganic hard mask layer for protection from chemical-mechanical polishing damage. A large, lateral interface between the organic material substrate layer and inorganic material hard mask layer is typically weak and, as indicated above, often cannot withstand chemical-mechanical polishing forces which are applied subsequent to metalization to remove the metallic circuitry layer above the hard mask.
- Mechanical integrity of the material at interface20 between the lower surface of the
hard mask layer 10 and the upper surface of thedielectric substrate layer 12 during chemical-mechanical polishing tends to be a problem when processing materials that are softer or weaker than, for example, oxide or nitride. Although many improvements have been made to theupper interface 21 between the top surface ofhard mask layer 10 and the lower surfacemetallic layer 18 placed on top ofhard mask layer 10, mechanical integrity is still a major problem with lower interface 20. - The deficiencies of the conventional semiconductor devices show that a need still exists for an improved device and method of manufacture. An object of the present invention is to provide a semiconductor device and a method of manufacture able to withstand chemical-mechanical polishing forces applied during manufacture. A related object is to enhance the mechanical integrity of the dielectric substrate component of a semiconductor device.
- To achieve these and other objects, and in view of its purposes, the present invention provides a method for forming semiconductor devices. In accordance with the present invention, the method includes the steps of providing a substrate and applying a photomask to the substrate. Next, a selected thickness of selected parts of the substrate is removed by etching. After the photomask is removed, a cap dielectric layer is deposited onto the substrate with portions of the cap dielectric layer extending into spaces in the substrate from which parts of the substrate have been etched.
- A semiconductor device, constructed in accordance with the present invention, includes a substrate having recesses extending inwardly from a surface of the substrate and a cap dielectric layer against the substrate having portions extending into the recesses in the substrate.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
- The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:
- FIGS. 1 through 4 show various stages in the conventional formation of semiconductor devices and, in particular, FIG. 1 illustrates a semiconductor device following the sequential formation of a photomask over a hard mask layer over a dielectric substrate layer;
- FIG. 2 illustrates the device of FIG. 1 after recesses are etched, using the pattern of the photomask, through the hard mask layer and into the dielectric substrate layer;
- FIG. 3 illustrates the device of FIG. 2 after the photomask is removed and a metallic layer is applied over the hard mask layer and to the walls and bottom surfaces of the recesses;
- FIG. 4 illustrates the device of FIG. 3 after those portions of the metallic layer on top of the hard mask layer are removed;
- FIGS. 5 through 7 show various stages in the formation of semiconductor devices in accordance with a first embodiment of the present invention and, in particular, FIG. 5 illustrates a substrate (having a base dielectric layer and a hard mask) with a photomask applied to the substrate and a selected thickness of selected parts of the substrate removed by etching;
- FIG. 6 illustrates the device of FIG. 5 after the photomask is removed;
- FIG. 7 illustrates the device of FIG. 6 after a cap dielectric layer is deposited onto the substrate;
- FIGS. 8 through 10 show various stages in the formation of semiconductor devices in accordance with a second embodiment of the present invention and, in particular, FIG. 8 illustrates a base dielectric layer substrate with a photomask applied to the substrate and a selected thickness of selected parts of the substrate removed by etching;
- FIG. 9 illustrates the device of FIG. 8 after the photomask is removed; and
- FIG. 10 illustrates the device of FIG. 9 after a cap dielectric layer is deposited onto the substrate.
- Referring now to FIGS. 5 through 7, in which like reference numbers refer to like elements throughout, a semiconductor device constructed in accordance with a first embodiment of the present invention is formed as follows. A substrate having a base dielectric layer30 and a
hard mask 22 is provided and aphotomask 24 is applied to the substrate. For the embodiment of the invention being described, and as illustrated in FIG. 5,photomask 24 is applied tohard mask 22. Base dielectric layer 30 can be an organic material (such as benzocyclobutanes, parylene-N, parylene-F, or polyamides) or an inorganic material (such as inorganic xerogels, SiCOH, hexametholsylsesquoixane, fluorinated spin-on glass, or spin-on glass).Hard mask 22 can be SiCOH, SiN, or SiO2. Photomask 24 can be a photosensitive polymer. A metal can be used but must be removed before subsequent layers are formed. - Next, also as illustrated in FIG. 5, a selected thickness of selected parts of the substrate is removed by etching. The etched parts of the substrate are in the form of
recesses 26 in an inactive part of the semiconductor device being formed and extend completely throughhard mask 22 and partially through base dielectric layer 30. For the embodiment of the invention being described, base dielectric layer 30 is etched in a pure oxygen-Ar mixture with at least 3:1 etch selectivity between an organic base dielectric layer and the silicon-containingphotomask 24. The thickness ofphotomask 24 preferably is less than the thickness of organic base dielectric layer 30 and the etch preferably should remove less than one-half of the total thickness of base dielectric layer 30 to achieve the desired vertical adhesion enhancement effect to be described below. -
Next photomask 24 is removed. Photomask 24 can be removed with an acid wash, a solvent cleaning procedure, or both or by using a fluorine-based chemistry reactive ion etch, which might result in a ten percent change in the mask lateral dimension. The structure that results afterphotomask 24 is removed is illustrated in FIG. 6. - Next, a cap dielectric layer28 is deposited onto the substrate. Portions of cap dielectric layer 28 extend into the spaces (i.e., recesses 26) in the substrate from which parts of the substrate have been etched. For the embodiment of the invention being described, cap dielectric layer 28 is deposited onto
hard mask 22. The resulting structure is illustrated in FIG. 7. - Cap dielectric layer28 can be a spin-on glass (e.g., fluorinated oxide). Cap dielectric layer 28 typically is spun onto
hard mask 22 to 300-500 Å and as much as 5,000 Å above the top surface ofhard mask 22. By using a liquid dielectric, cap dielectric layer 28 is locally planar in the areas that will be patterned. Cap dielectric layer 28 can serve as a hard mask (thin layer) or as the second dual damascene layer (thicker layer) for a dual damascene sequence. - As a result, by using a separate masking step, vertical sidewalls have been introduced into base dielectric layer30 at an inactive part of the semiconductor device, whereby adhesion to base dielectric layer 30 is enhanced by the interlock of the parts of cap dielectric layer 28 and recesses 26 in base dielectric layer 30. The interlock between base dielectric layer 30 and cap dielectric layer 28 enhances the resistance to shearing or tearing away of
hard mask 22 as a metallic circuitry layer (not shown in FIG. 7 but which is deposited over cap dielectric layer 28) is subjected to chemical-mechanical polishing. It should be noted that cap dielectric layer 28 can be an inorganic material, such as SiN, SiCOH, SiO2, or spin-on glass, when the base dielectric material is an organic material. - Referring now to FIGS. 8 through 10, in which like reference numbers refer to like elements throughout, a semiconductor device constructed in accordance with a second embodiment of the present invention is formed as follows. A substrate comprising a
base dielectric layer 40 is provided with a photomask 42 that is applied directly tobase dielectric layer 40. In contrast to the first embodiment of the invention, the substrate does not have a hard mask applied to basedielectric layer 40. - Next, as illustrated in FIG. 8, a selected thickness of selected parts of
base dielectric layer 40 is removed by etching. The etched parts of the substrate are in the form ofrecesses 44 in an inactive part of the semiconductor device being formed and extend partially throughbase dielectric layer 40. - Next, photomask42 is removed. The structure that results after photomask 42 is removed is illustrated in FIG. 9. A cap dielectric layer 46 is deposited onto the substrate with portions of cap dielectric layer 46 extending into the spaces (i.e., recesses 44) in
base dielectric layer 40 from which parts ofbase dielectric layer 40 have been etched. For the embodiment of the invention being described, cap dielectric layer 46 is deposited directly ontobase dielectric layer 40 and functions as a hard mask. The resulting structure is illustrated in FIG. 10. Cap dielectric layer 46 can be inorganic material, such as Dow Chemical Fox, 650F, whenbase dielectric layer 40 is an organic material. - Again, by using a separate masking step, vertical sidewalls have been introduced into
base dielectric layer 40 at an inactive part of the semiconductor device, whereby adhesion to the base dielectric layer is enhanced by the interlock of the parts of cap dielectric layer 46 and recesses 44 inbase dielectric layer 40. The interlock between basedielectric layer 40 and cap dielectric layer 46 enhances the resistance to shearing or tearing away as a metallic circuitry layer (not shown in FIG. 10 but which is deposited over cap dielectric layer 46) is subjected to chemical-mechanical polishing. - Although illustrated and described above with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention. Specifically, the present invention has been described in connection with a single damascene semiconductor device. It will be apparent to those skilled in the art, however, that the present invention can be applied to dual damascene semiconductor devices.
Claims (20)
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US09/354,742 US6448629B2 (en) | 1999-07-29 | 1999-07-29 | Semiconductor device and method of making same |
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US09/354,742 US6448629B2 (en) | 1999-07-29 | 1999-07-29 | Semiconductor device and method of making same |
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Cited By (2)
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US20060264036A1 (en) * | 2003-12-08 | 2006-11-23 | International Business Machines Corporation | Line level air gaps |
US20070012950A1 (en) * | 2003-09-02 | 2007-01-18 | Paul Cain | Production of electronic devices |
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US4032373A (en) * | 1975-10-01 | 1977-06-28 | Ncr Corporation | Method of manufacturing dielectrically isolated semiconductive device |
US4385975A (en) | 1981-12-30 | 1983-05-31 | International Business Machines Corp. | Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate |
US4857988A (en) * | 1988-02-09 | 1989-08-15 | Fottler Stanley A | Leadless ceramic chip carrier |
US4952274A (en) | 1988-05-27 | 1990-08-28 | Northern Telecom Limited | Method for planarizing an insulating layer |
DE69131784T2 (en) * | 1990-07-21 | 2000-05-18 | Mitsui Chemicals Inc | Semiconductor device with a package |
DE4239075C1 (en) | 1992-11-20 | 1994-04-07 | Itt Ind Gmbh Deutsche | Process for the global planarization of surfaces of integrated semiconductor circuits |
US5494854A (en) * | 1994-08-17 | 1996-02-27 | Texas Instruments Incorporated | Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films |
US5663107A (en) | 1994-12-22 | 1997-09-02 | Siemens Aktiengesellschaft | Global planarization using self aligned polishing or spacer technique and isotropic etch process |
US5618757A (en) | 1996-01-30 | 1997-04-08 | Vlsi Technology, Inc. | Method for improving the manufacturability of the spin-on glass etchback process |
US5728507A (en) | 1996-02-20 | 1998-03-17 | Motorola, Inc. | Method for planarizing a semiconductor layer |
US6127089A (en) * | 1998-08-28 | 2000-10-03 | Advanced Micro Devices, Inc. | Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
-
1999
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Cited By (3)
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US20070012950A1 (en) * | 2003-09-02 | 2007-01-18 | Paul Cain | Production of electronic devices |
US8986793B2 (en) * | 2003-09-02 | 2015-03-24 | Plastic Logic Limited | Production of electronic devices |
US20060264036A1 (en) * | 2003-12-08 | 2006-11-23 | International Business Machines Corporation | Line level air gaps |
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