US20010050386A1 - Semiconductor integrated circuit device and the process of manufacturing the same - Google Patents
Semiconductor integrated circuit device and the process of manufacturing the same Download PDFInfo
- Publication number
- US20010050386A1 US20010050386A1 US09/795,190 US79519001A US2001050386A1 US 20010050386 A1 US20010050386 A1 US 20010050386A1 US 79519001 A US79519001 A US 79519001A US 2001050386 A1 US2001050386 A1 US 2001050386A1
- Authority
- US
- United States
- Prior art keywords
- film
- integrated circuit
- circuit device
- semiconductor integrated
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000008569 process Effects 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 43
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 23
- 239000010937 tungsten Substances 0.000 claims abstract description 23
- 238000012545 processing Methods 0.000 claims abstract description 15
- -1 tungsten nitride Chemical class 0.000 claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 61
- 238000013500 data storage Methods 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 31
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 19
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 5
- QIJNJJZPYXGIQM-UHFFFAOYSA-N 1lambda4,2lambda4-dimolybdacyclopropa-1,2,3-triene Chemical compound [Mo]=C=[Mo] QIJNJJZPYXGIQM-UHFFFAOYSA-N 0.000 claims description 3
- 229910039444 MoC Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 3
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 3
- LGLOITKZTDVGOE-UHFFFAOYSA-N boranylidynemolybdenum Chemical compound [Mo]#B LGLOITKZTDVGOE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 239000005078 molybdenum compound Substances 0.000 claims 1
- 150000002752 molybdenum compounds Chemical class 0.000 claims 1
- 229910001936 tantalum oxide Inorganic materials 0.000 claims 1
- 150000003658 tungsten compounds Chemical class 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 55
- 229910052814 silicon oxide Inorganic materials 0.000 description 55
- 238000003860 storage Methods 0.000 description 27
- 229910052581 Si3N4 Inorganic materials 0.000 description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 23
- 230000002093 peripheral effect Effects 0.000 description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 18
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 15
- 238000002955 isolation Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 239000011521 glass Substances 0.000 description 9
- 238000005204 segregation Methods 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- This invention relates to a semiconductor integrated circuit device and the method of its fabrication, and in particular to a semiconductor integrated circuit having a DRAM (dynamic random access memory).
- DRAM dynamic random access memory
- the DRAM memory cell which is provided at the intersections of the word lines and bit lines that are provided in a matrix pattern over the major surface of a semiconductor substrate, comprises a single memory-cell-selecting MISFET (metal-insulator-semiconductor field-effect transistor) and a single data-storage capacitor connected in series.
- the memory-cell-selecting MISFET mainly comprises a gate oxide film, a gate electrode that is configured in a single unit with a word line, and a pair of semiconductor regions that configure the source and drain regions.
- the bit line which is provided over the memory-cell-selecting MISFET, is electrically connected to either the source region or the drain region.
- the data-storage capacitor which is also provided over the memory-cell-selecting MISFET, is electrically connected to the other region, source or drain.
- a stacked capacitor configuration in which the data-storage capacitor is provided over the memory-cell-selecting MISFET, has been used in the DRAMs of recent years.
- the stacked capacitor configuration can roughly be classified into the following two configurations: a capacitor-under-bit-line (CUB) configuration in which the data-storage capacitor is provided below the bit line, and a capacitor-over-bit-line (COB) configuration in which the data-storage capacitor is provided over the bit line.
- CAB capacitor-under-bit-line
- COB capacitor-over-bit-line
- the surface area of the data-storage capacitor must be increased by an upward elongation of the capacitor's semiconductor form.
- the CUB configuration in which the data-storage capacitor is provided below the bit line
- the aspect ratio of the contact hole that connects the bit line and the memory-cell-selecting MISFET significantly increases, and as a result, the complete formation of the hole will become difficult. Accordingly, when the above two stacked capacitor configurations are compared, the COB configuration, in which the data-storage capacitor is provided over the bit line, is more suitable for the miniaturization of memory cells than the CUB configuration.
- the TiN film that configures part of the bit line and part of the first-layer wiring of the peripheral circuits is utilized as an etching stopper that can prevent etching of the W plug inside the contact hole that connects the first-layer wiring with the MISFET of the peripheral circuits.
- the first-layer wiring of the peripheral circuits is connected to the source and drain of the MISFET without the interposition of a plug.
- the TiN film under the W film is utilized as a barrier material to prevent the forming of an undesirable silicide layer as a result of reaction at the interface between the W film and the silicon substrate.
- a DRAM wherein the bit line and the first-layer wiring of the peripheral circuits are formed concurrently by a so-called Damascene method.
- a two-layered conductive film comprising a WN (tungsten nitride) film and a W film that is deposited over that, is embedded inside the wiring groove that is formed in the insulating film.
- the WN film under the W film acts not only as an adhesive film between the W film and insulating film in the Damascene configuration, but also as a barrier material which prevents the growth of an undesirable silicide layer at the interface between the W film and silicon substrate.
- the DRAM configuration to which this newly invented method is applied is characterized by:
- a high-dielectric film for example Ta 2 O 5 (tantalum pentoxide), as a capacitance-insulating film;
- a refractory-metal bit line for example W, the low resistivity of which improves the signal delay quality
- bit line needs to be reduced to 0.1 ⁇ m or less to ensure a margin against short-circuit between the bit line and the plug that has been embedded inside the through hole.
- the objective of this invention is to provide a technique that can effectively prevent wiring breaks in the bit lines of a DRAM that has miniaturized memory cells.
- the semiconductor integrated circuit device of this invention comprises:
- memory cells including;
- a memory-cell-selecting MISFET which is formed over the major surface of a semiconductor substrate, with a gate electrode that is configured in a single unit with a word line;
- a data-storage capacitor that is formed over a second insulating film which covers the bit line and that is electrically connected to the other part, either source or drain, of the memory-cell-selecting MISFET;
- bit line that is formed over a first insulating film which covers the memory-cell-selecting MISFET and that is electrically connected to either the source or drain of the memory-cell-selecting MISFET;
- the semiconductor integrated circuit device of this invention comprises:
- memory cells including;
- a memory-cell-selecting MISFET which is formed over the major surface of a semiconductor substrate, with a gate electrode that is configured in a single unit with a word line;
- a data-storage capacitor that is formed over a second insulating film which covers the bit line and that is electrically connected to the other part, either source or drain, of the memory-cell-selecting MISFET;
- bit line that is formed over a first insulating film which covers the memory-cell-selecting MISFET and that is electrically connected to either the source or drain of the memory-cell-selecting MISFET;
- bit line is made of a first conductive film of a W compound and a second conductive film of W that is deposited on the first conductive film, and the width of the bit line is 0.1 ⁇ m or less.
- the fabrication method for a semiconductor integrated circuit device of this invention comprises the steps of:
- bit lines made of the first and second conductive films by using a narrow etching-resistant film as a mask in etching the first and second conductive films.
- FIG. 1 is a plan view of the whole of a semiconductor chip over which the DRAM, which is one embodiment of this invention, is formed.
- FIG. 2 is a plan view of a semiconductor substrate that shows part of the storage section of the DRAM which is one embodiment of this invention.
- FIG. 3 is a cross-sectional view through the key parts of the semiconductor substrate that shows the DRAM which is one embodiment of this invention.
- FIG. 4 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 5 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 6 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 7 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 8 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 9 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 10 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 11 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 12 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 13 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 14 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 15 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 16 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 17 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 18 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 19 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 20 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 21 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 22 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 23 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 24 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 25 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 26 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 27 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 1 is a plan view of the whole of semiconductor chip 1 A over which a DRAM that is this embodiment has been formed.
- a DRAM with a storage capacity of 256 Mbits is formed over the major surface of rectangular semiconductor chip 1 A.
- This DRAM comprises the storage section made up mainly of memory arrays (MARY) and peripheral circuits PC that are provided at the periphery outside the storage section.
- MARY memory arrays
- peripheral circuits PC peripheral circuits
- a number of bonding pads BP that will be connected to wires or bump electrodes are provided in a single line.
- FIG. 2 which is a plan view of a semiconductor substrate, shows part of the storage section of the above DRAM
- FIG. 3 is a cross-sectional view through the key parts of the semiconductor substrate of the above DRAM.
- the left-hand area of FIG. 3 shows the cross-sectional view along the A-A line of FIG. 2
- the central area shows the cross-sectional view along the B-B line of FIG. 2
- the right-hand area is a cross-sectional view that shows part of the peripheral circuits.
- element-isolation groove 2 , p-type well 3 , and n-type well 4 are formed over the major surface of semiconductor substrate (hereinafter referred to as simply substrate) 1 made of p-type single-crystalline silicon.
- Memory cells each of which is made up of n-channel memory-cell-selecting MISFET Qt and data-storage capacitor C formed over that, are formed over the p-type well of the storage section.
- element-isolation groove 2 and active regions L which are isolated by element-isolation groove 2 are formed in p-type well 3 in the storage section. These active regions L are formed as long, narrow island patterns, and two memory-cell-selecting MISFETs Qt are formed in each active region L. These two MISFETs Qt use either a common source or a common drain.
- Element-isolation groove 2 that encloses active region L is formed by embedding silicon oxide film 5 in a shallow groove that is formed by etching substrate 1 . The surface of silicon oxide film 5 is flattened so that its height is almost the same as that of active region L.
- Memory-cell-selecting MISFET Qt is made up mainly of gate-insulating film 6 , gate electrode 7 A that forms word line WL in the regions outside those used for active region L, and paired n-type semiconductor regions (source and drain) 9 and 9 .
- Gate electrode 7 A (word line WL) is made of a so-called polycide film in which a W (tungsten) silicide film is deposited over an n-type polysilicon film which has been doped with, for example, phosphorus (P).
- gate electrode 7 A word line WL
- space between pairs of adjacent gate electrodes 7 A word lines WL
- photolithographic resolution for example 0.13 to 0.14 ⁇ m
- the peripheral circuits of the DRAM are made up of so-called CMOS circuits in which multiple n-channel MISFETs Qn and multiple p-channel MISFETs Qp are combined.
- Each n-channel MISFET Qn is mainly made up of gate-insulating film 6 , gate electrode 7 B, and paired n + -type semiconductor regions (source and drain) 12 and 12 , and is formed in p-type well 3 .
- Each p-channel MISFET Qp is mainly made up of gate-insulating film 6 , gate electrode 7 C, and paired p + -type semiconductor regions (source and drain) 13 and 13 , and is formed in n-type well 4 .
- gate electrodes 7 B and 7 C are made of polycide films.
- the n-channel MISFET Qn and p-channel MISFET Qp are formed on the basis of a design rule that is less stringent than that used for memory-cell-selecting MISFET Qt; the width (gate length) of gate electrodes 7 B and 7 C and the space of the pairs of adjacent MISFETs are greater than those of the memory cell.
- Silicon nitride film 8 is formed over gate electrode 7 A (word line WL) of memory-cell-selecting MISFET Qt.
- Silicon nitride film 11 is deposited over the entire surface of the substrate (including silicon nitride 8 , the sidewall of silicon nitride 8 , and the sidewall of gate electrode 7 A (word line WL)). As described later, these silicon nitride films 8 and 11 are used as etching stoppers when the contact hole is formed over the source and drain (n-type semiconductor region 9 ) of memory-cell-selecting MISFET Qs by a self-alignment method with regard to gate electrode 7 A (word line WL).
- Silicon nitride film 8 is formed over gate electrodes 7 B and 7 C of the MISFETs (Qn and Qp) of the peripheral circuits, and sidewall spacers 11 s are formed on both sidewalls of gate electrodes 7 B and 7 C by etching silicon nitride film 11 . As described later, sidewall spacers 11 s are used so that both the sources and drains of the respective n-channel MIFETs Qn and p-channel MISFETs Qp are configured in an LDD (lightly doped drain) configuration.
- LDD lightly doped drain
- Interlayer-insulating film 15 is formed over memory-cell-selecting MISFET Qt, n-channel MISFET Qn, and p-channel MISFET Qp.
- Interlayer-insulating film 15 is made of, for example, a spin-on-glass film (silicon-oxide insulating film formed by coating) and a two-layered silicon oxide film formed over that. The interlayer-insulating film is flattened so that the surface height is almost the same over the whole area of substrate 1 .
- Contact holes 16 and 17 are formed over paired n-type semiconductor regions 9 and 9 that configure the source and drain of memory-cell-selecting MISFET Qt, by etching interlayer-insulating film 15 and underlying silicon nitride film 11 .
- Plug 18 is made of a low-resistance n-type polysilicon film which is doped with, for example, phosphorus (P), and embedded in contact holes 16 and 17 .
- the diameter (both in the X direction parallel to gate electrode 7 A (word line WL) and in the Y direction perpendicular to the X direction) of contact hole 17 is nearly the same as the width (in the X-direction) of active region L.
- the diameter (in the X-direction) of the other contact hole 16 can be longer than the width (in the X-direction) of active region L.
- contact hole 16 is formed as an approximately rectangular pattern which is wider in the X-direction than it is long in the Y-direction.
- Part of contact hole 16 extends up to the upper region of element-isolation groove 2 , which is outside active region L.
- bit line BL need not be extended to the upper region of active region L by widening part of bit line BL, or part of active region L need not be extended in the direction of bit line BL, when n-type semiconductor region 9 and bit line BL are electrically connected via contact hole 16 . Consequently, it is possible to reduce the memory size.
- Silicon oxide film 19 is formed over interlayer-insulating film 15 , then through hole 20 is formed in silicon oxide film 19 within the region of contact hole 16 .
- Through hole 20 is designed to be located over element-isolation groove 2 that is situated outside of active region L.
- Plug 23 made of a two-layered conductive film in which a W film is deposited over, for example a TiN (titanium nitride) film, is embedded in through hole 20 .
- Plug 23 embedded in through hole 20 is electrically connected to either the source or drain (n-type semiconductor region 9 that is used in common by two memory-cell-selecting MISFETs Qt) of memory-cell-selecting MISFET Qt, with the interposition of plug 18 embedded in contact hole 16 under plug 23 .
- Contact holes 21 and 22 are formed in silicon oxide film 19 and underlying interlayer-insulating film 15 for the peripheral circuits.
- Contact hole 21 is formed over paired n + -type semiconductor regions (source and drain) 12 and 12 that configure the source and drain of n-channel MISFET Qn.
- Contact hole 22 is formed over paired p ⁇ -type semiconductor regions (source and drain) 13 and 13 that configure the source and drain of p-channel MISFET Qp.
- Plug 23 made of the same conductive material as plug 23 that was earlier embedded in through hole 20 of said storage section, is embedded in contact holes 21 and 22 .
- Bit lines BL for reading the data from the memory cells, are formed over silicon oxide film 19 of the storage section. These bit lines BL, provided over element-isolation groove 2 , extend with a uniform line width and spacing between lines in the direction perpendicular to gate electrode 7 A (word line WL). Each bit line BL is electrically connected, via plug 23 in said through hole 20 in silicon oxide film 19 under the bit lines and via plug 18 in contact hole 16 under silicon oxide film 19 , to either the source or drain (n-type semiconductor region 9 ) of each memory-cell-selecting MISFET Qt that runs parallel to bit lines BL.
- Bit lines BL should be as narrow as possible so that spacing is sufficient to ensure a margin against short-circuit with plug 44 that has been embedded in through hole 43 formed in the space between the adjacent bit lines. The parasitic capacitance between adjacent bit lines is thus also reduced.
- the width of bit line BL is 0.1 ⁇ m or narrower. This is narrower than the width (0.13 to 0.14 ⁇ m) of gate electrode 7 A (word line WL) as described above and the space (0.13 to 0.14 ⁇ m) between pairs of adjacent gate electrodes 7 A (word lines WL). That is, a narrower bit line BL is formed than the minimum size as determined by the limitations on photolithographic resolution. The method for forming such fine bit lines BL is described later.
- bit line BL of the DRAM of this embodiment is made of a two-layered conductive film in which W film 25 is deposited on WN (tungsten nitride) film 24 .
- W film 25 is deposited on WN (tungsten nitride) film 24 .
- WN tungsten nitride
- Vacancies and dislocations inside crystal grains contribute to the diffusion paths for atoms, so atoms are more likely to travel within grains if the grains contain many vacancies or dislocations. Accordingly, when a film is formed under conditions that readily bring the arrangement of the W atoms into disorder, the number of W atoms at the grain boundaries decreases, since many of the W atoms tend to diffuse to fill up the vacancies and dislocations. This is the case when the difference between the lattice constants of the foundation material and W is great and the W film is then subjected to high-temperature thermal processing.
- bit line BL that is made of a two-layered conductive film in which W film 25 is deposited on WN film 24 , few W atoms are diffused across the interface between W film 25 and WN film 24 under that, within crystal grains and at the grain boundaries of W film 25 . In addition, no tensile stress is generated inside W film 25 . Therefore, wiring breaks are not caused by high-temperature processing even when the wiring width is narrowed to 0.1 ⁇ m or less.
- Materials with lattice constants that are close to that of W include Mo (molybdenum) and its compounds such as MoN (molybdenum nitride), MoB (molybdenum boride), and MoC (molybdenum carbide), as well as WN.
- Mo mobdenum
- MoN mobdenum nitride
- MoB mobdenum boride
- MoC mobdenum carbide
- bit lines BL have compressive stress when it is deposited on a TiN film. Therefore, by forming bit lines BL of two-layered conductive films in which a W film is deposited on a TiN film, the wiring-break rate can be reduced even when the width of bit line BL is narrowed to 0.1 ⁇ m or less.
- first-layer wires 30 to 33 are formed over silicon oxide film 19 in the peripheral circuits.
- Wires 30 to 33 are made of two-layered conductive films in which W film 25 is deposited on WN film 24 , in a similar way to and at the same time as bit lines BL as is described later.
- Wires 30 and 31 are electrically connected to the source and drain of n-channel MISFET Qn (n + -type semiconductor region 12 ) through contact holes 21 that have been formed in silicon oxide films 19 and 15 .
- Wires 32 and 33 are electrically connected to the source and drain of p-channel MISFET Qp (p + -type semiconductor region 13 ) through contact holes 22 that have been formed in silicon oxide films 19 and 15 .
- Interlayer-insulating film 40 is formed over bit line BL and first-layer wires 30 to 33 .
- Interlayer-insulating film 40 is made of a spin-on-glass film and a two-layered silicon oxide film which is formed over the spin-on-glass film, in a similar way to the formation of lower interlayer-insulating film 15 .
- Film 40 is flattened so that the surface height is almost the same over the whole area of substrate 1 .
- through holes 43 are formed in interlayer-insulating film 40 and silicon oxide film 19 under interlayer-insulating film 40 .
- Through-holes 43 are located directly above contact holes 17 , and plugs 44 that are made of low-resistance n-type polysilicon films which have been doped with P (phosphorus) are embedded in through-holes 43 .
- Silicon nitride film 45 and thick silicon oxide film 46 are formed over interlayer-insulating film 40 .
- deep grooves 47 are formed in silicon oxide film 46 .
- Data-storage capacitors C which are configured by lower electrode 48 , capacitance-insulating film 49 , and upper electrode 50 , are formed in deep grooves 47 .
- Lower electrodes 48 of data-storage capacitors C are made of a low-resistance n-type polysilicon film which has been doped with P (phosphorus).
- Lower electrodes 48 are electrically connected to n-type semiconductor regions (source and drain) 9 of memory-cell-selecting MISFETs Qn via through hole 43 and contact hole 17 that have been formed under lower electrode 48 .
- Capacitance-insulating film 49 of data-storage capacitor C is a Ta 2 O 5 (tantalum pentoxide) film, etc.
- Upper electrode 50 is made of a TiN film, etc.
- Silicon oxide film 51 is then formed over data-storage capacitor C, and two or so layers of Al are formed as wiring (not shown) over silicon oxide film 51 .
- FIGS. 4 to 27 are now used in describing an example of a method of fabricating a DRAM that is related to the embodiment as configured above.
- the element-isolation region of substrate 1 is etched to form element-isolation groove 2 with a depth of about 350 nm on the major surface of p-type single-crystalline silicon substrate 1 .
- B (boron) ions are then implanted into parts of substrate 1 to form p-type wells 3 and P (phosphorus) ions are implanted into other parts of substrate 1 to form n-type wells 4 .
- Silicon oxide film 5 is then deposited by chemical vapor deposition (CVD) in the grooves and over substrate 1 , and the superfluous part of silicon oxide film 5 that protrudes beyond the groove is removed by chemical mechanical polishing (CMP).
- active regions L which are the long, narrow island patterns that are surrounded by element-isolation grooves 2 , are formed in substrate 1 in the storage section by the formation of element-isolation grooves 2 .
- Gate-insulating film 6 is formed of silicon oxide over p-type well 3 and n-type well 4 by the thermal oxidation of substrate 1 .
- gate electrodes 7 A word lines WL
- gate electrodes 7 B and 7 C are formed over gate-insulating film 6 in the peripheral circuits.
- a polysilicon film which has been doped with P (phosphorus) is deposited over substrate 1 by CVD to form gate electrodes 7 A, 7 B, and 7 C.
- a W silicide film is then sputtered over the polysilicon film, and silicon nitride film 8 is deposited over the W 'silicide film by CVD.
- Silicon nitride film 8 is patterned by using a photoresist film as a mask against dry etching, and the W silicide film and polysilicon film are then patterned by using silicon nitride film 8 as a mask against dry etching.
- gate electrodes 7 A (word lines WL) run perpendicularly across the longer sides of active regions L, and the gate length and the space between adjacent gate electrodes 7 A (word lines WL) are both in the 0.13 to 1.4- ⁇ m range.
- As (arsenic) ions are implanted in p-type well 3 on both sides of gate electrodes 7 A and 7 B to form n ⁇ -type semiconductor regions 9 in p-type well 3 .
- B (boron) ions are implanted in n-type well 4 on both sides of gate electrode 7 C to form p ⁇ -type semiconductor regions 10 in n-type well 4 .
- Silicon nitride film 11 is deposited over substrate 1 by CVD. As shown in FIG. 9, the storage sections of substrate 1 are then covered by a photoresist film (not shown), and silicon nitride film 11 in the peripheral circuits is anisotropically etched. As a result, side-wall spacers 11 s are formed on both sidewalls of gate electrodes 7 B and 7 C in the peripheral circuits.
- P ions are implanted into p-type well 3 to form n + -type semiconductor regions (source and drain) 12 with a high concentration of impurities
- B ions are implanted into n-type well 4 to form p + -type semiconductor regions (source and drain) 13 with a high concentration of impurities.
- interlayer-insulating film 15 made of a spin-on-glass film and a two-layered silicon oxide film is formed over gate electrodes 7 A, 7 B, and 7 C.
- Interlayer-insulating film 15 is formed by spin-coating a spin-on-glass film over gate electrodes 7 A, 7 B, and 7 C.
- the spin-on-glass film has superior characteristics in terms of filling spaces between fine wires to those of a silicon oxide film deposited by CVD. Therefore, even if the spaces between gate electrodes 7 A (word lines WL) of the storage section are extremely narrow, the space can be filled perfectly by using the spin-on-glass film.
- the silicon oxide film is polished and flattened by CMP to make the heights of the storage section and peripheral circuits uniform.
- the second silicon oxide film is then deposited by CVD over the first silicon oxide film to cover the fine scratches on the surface of the lower (first) silicon oxide film that are caused by CMP.
- interlayer-insulating films 15 over n ⁇ -type semiconductor regions 9 in the storage section are removed by dry etching.
- a photoresist film (not shown) is used as a mask.
- the condition for this etching is that the rate of etching of interlayer-insulating films 15 (the spin-on-glass film and silicon oxide film) must be greater than that of silicon nitride films 8 and 11 .
- Silicon nitride film 11 is removed from n-type semiconductor regions 9 by dry etching, using a photoresist film as a mask, and the surface of n ⁇ -type semiconductor regions 9 is then exposed so that contact holes 16 and 17 are thus formed.
- the condition for the etching of silicon nitride film 11 is that the etching rate of silicon nitride film 11 is greater than that of silicon oxide film 5 embedded in element-isolation groove 2 . This is so that silicon oxide film 5 in element-isolation groove 2 is not etched deeply.
- Silicon nitride film 11 is anisotropically etched and silicon nitride film 11 thus remains on both sidewalls of gate electrodes 7 A (word lines WL).
- contact holes 16 and 17 are formed with fine diameters by a self-alignment method with regard to gate electrodes 7 A (word lines WL). As earlier described, part of long-patterned contact hole 16 extends up to the upper region of element-isolation groove 2 , which is outside active region L.
- plugs 18 are formed in contact holes 16 and 17 .
- a low-resistance polysilicon film which has been doped with P is deposited by CVD in contact holes 16 and 17 and over interlayer-insulating film 15 , and the superfluous polysilicon film over interlayer-insulating film 15 is removed by dry etching.
- Substrate 1 is thermal-processed in an atmosphere of nitrogen and the P in the polysilicon film which configures plug 18 is diffused into n ⁇ -type semiconductor regions 9 to form low-resistance n-type semiconductor regions 9 (source and drain). The above processes complete the creation of memory-cell-selecting MISFET Qt in the storage section.
- a photoresist film (not shown) is used as a mask in the dry etching of silicon oxide film 19 and interlayer-insulating film 15 in the peripheral circuits.
- contact holes 21 are formed above the source and drain of n-channel type MISFET Qn (n + -type semiconductor region 12 ), and contact holes 22 are formed above the source and drain of p-channel type MISFET Qp (p + -type semiconductor region 13 ).
- silicon oxide film 19 in the storage section is etched to form through hole 20 over contact hole 16 .
- plugs 23 are formed in contact holes 21 and 22 that have been formed in the peripheral circuits and in through hole 20 that has been formed in the storage section.
- Plugs 23 are formed of TiN and W films that are deposited, by sputtering and CVD, over silicon oxide film 19 , in contact holes 21 and 22 , and in through hole 20 .
- the superfluous TiN and W films over silicon oxide film 19 are then removed by CMP.
- WN film 24 and W film 25 are deposited, by sputtering and in that order, over silicon oxide film 19 .
- the deposition of W film 25 on WN film 24 leads to a more tightly-packed and finely-grained W film 25 with greatly-narrow interfacial segregations and with fewer vacancies and dislocations in the crystal grains, than would be obtained by the direct deposition of W film 25 on silicon oxide film 19 .
- photoresist masks 26 are formed over W film 25 .
- the width of photoresist mask 26 formed over W film 25 in the storage section is around 0 . 18 to 0 . 2
- photoresist masks 26 are narrowed using active oxygen radicals, which can be generated by the irradiation of ozone by ultraviolet rays, in the well-known ashing process. This process narrows the line widths of photoresist masks 26 s formed over W film 25 in the storage section to, for example, around 0 . 12 to 0 . 13
- narrowed photoresist masks 26 s are used in patterning W film 25 and WN film 24 by dry etching to form bit lines BL over silicon oxide film 19 in the storage section and wires 30 to 33 over silicon oxide film 19 in the peripheral circuits.
- Etching of W film 25 and WN film 24 is, to a certain degree, isotropic. Both sidewalls of bit lines BL (and wires 30 to 33 ) are thus etched, and bit lines BL with a width of 0.1 ⁇ m or less, which is narrower than the line widths of photoresist masks 26 s, can in this way be obtained.
- bit lines BL can be formed with a high degree of accuracy in terms of size.
- bit lines BL can still be formed with a high degree of accuracy in terms of size, even when WN film 24 is replaced by an Mo film or an Mo-compound film.
- interlayer-insulating film 40 is formed over bit lines BL and wires 30 to 33 , as is shown in FIG. 22.
- Interlayer-insulating film 40 is formed by the same process as was used to form interlayer-insulating film 15 .
- through holes 43 are formed above contact holes 17 by etching of interlayer-insulating film 40 and silicon oxide film 19 in the storage section.
- Polysilicon film 41 and sidewall spacers 42 made of a polysilicon film, which are formed over interlayer-insulating film 40 are used as etching-resistant masks.
- bit lines BL are narrowed to 0.1 ⁇ m or less, and the spaces between the bit lines are thus widened, a sufficient margin against short-circuit with plug 44 , which has been embedded in through hole 43 that was formed in the space between bit lines BL, can thus be ensured.
- plug 44 is formed in through hole 43 , as is shown in FIG. 24.
- a low-resistance polysilicon film doped with P (phosphorus) is deposited in through hole 43 and over interlayer-insulating film 40 by CVD to form plug 44 .
- Any superfluous polysilicon film over interlayer-insulating film 40 is removed by dry etching (or CMP).
- Silicon nitride film 45 is deposited over interlayer-insulating film 40 by CVD, and silicon oxide film 46 is then deposited over silicon nitride film 45 by CVD. To form deep grooves 47 over through holes 44 , silicon oxide film 46 and silicon nitride film 45 are then etched, in the storage section, with a photoresist film (not shown) as the mask.
- lower electrodes 48 of data-storage capacitors C are formed of polysilicon films on the sidewalls in grooves 47 .
- an amorphous silicon film (not shown) which has been doped with P (phosphorus) is deposited by CVD in grooves 47 and over silicon oxide film 46 . Any superfluous amorphous silicon film over silicon oxide film 46 is removed by dry etching.
- the surface of the amorphous silicon film that remains in grooves 47 is wet-cleaned by using some kinds of hydrofluoric acid.
- the amorphous silicon film is then exposed to a low-pressure atmosphere that supplies monosilane (SiH 4 ) to its surface.
- Substrate 1 is then thermally processed to crystallize the surface of the amorphous silicon film into grains of silicon.
- lower electrodes 48 are formed of grainy polysilicon film. Since a grainy polysilicon film has a large surface area, it is possible to increase the storage capacitance of the refined data-storage capacitor.
- a Ta 2 O 5 (tantalum pentoxide) film is deposited, by CVD, over the surface of lower electrodes 48 formed in grooves 47 and over the surface of silicon oxide film 46 outside grooves 47 . This film forms the capacitance-insulating film 49 of data-storage capacitor C.
- Substrate 1 is thermally processed in an atmosphere of oxygen to improve and crystallize the Ta 2 O 5 film.
- This thermal processing produces a high-quality Ta 2 O 5 film, with a dielectric constant of 20 to 25, and with better current-leakage characteristics.
- This thermal processing used to improve and crystallize the Ta 2 O 5 film is carried out in an atmosphere of oxygen and at temperatures in the range from 750 to 800° C. Although bit lines BL below are exposed to high temperatures by this treatment, no wiring break occurs.
- bit lines BL are made of two-layered conductive films, in which W film 25 has been deposited over WN film 24 , and fewer atoms of W thus diffused across the interface between W film 25 and WN film 24 , within crystal grains, and at grain boundaries in W film 25 , as earlier described, and no tensile stress exists in W film 25 .
- Capacitance-insulating film 49 of data-storage capacitor C can also be made of a film which is mainly comprised of a substance with a high-dielectric constant or a ferroelectric substance with a perovskite or complex-perovskite crystal structure, such as PZT, PLT, PLZT, PbTiO 3 , SrTiO 3 , BaTiO 3 , BST, SBT, or Ta 2 O 5 .
- a film of a substance with a high-dielectric constant or of a ferroelectric substance such as is listed above is used, high-temperature thermal processing is still required to improve and crystallize the film. In the same way as is described above, however, the high-temperature thermal processing will still not cause wiring breaks in bit lines BL.
- the TiN and Ta 2 O 5 films are patterned by dry etching with a photoresist film (not shown) as a mask.
- the above processes configure data-storage capacitor C with upper electrode 50 made of the TiN film, capacitance-insulating film 49 made of the Ta 2 O 5 film, and lower electrode 48 made of a polysilicon film.
- the DRAM memory cell is thus configured by memory-cell-selecting MISFET Qt and data-storage capacitor C that is connected, in series, to memory-cell-selecting MISFET Qt.
- Silicon oxide film 50 is then deposited over data-storage capacitor C by CVD, and two or so layers of Al are formed as wiring (not shown) over silicon oxide film 50 to complete the DRAM that is this embodiment and is shown in FIGS. 2 and 3.
- the wiring breaks of the gate electrodes can still be effectively prevented by forming the gate electrode with a WN film with its lattice constant which is close to that of W, a two-layered conductive film in which the W film is deposited over an Mo film or an Mo-compound film, or a polymetal-structured conductive film in which a polysilicon film is formed under the two-layered conductive film.
- This invention effectively prevents wiring breaks in bit lines of fine width, and DRAM-memory size can thus be reduced to implement larger-scale integrated memory.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- This invention relates to a semiconductor integrated circuit device and the method of its fabrication, and in particular to a semiconductor integrated circuit having a DRAM (dynamic random access memory).
- The DRAM memory cell, which is provided at the intersections of the word lines and bit lines that are provided in a matrix pattern over the major surface of a semiconductor substrate, comprises a single memory-cell-selecting MISFET (metal-insulator-semiconductor field-effect transistor) and a single data-storage capacitor connected in series. The memory-cell-selecting MISFET mainly comprises a gate oxide film, a gate electrode that is configured in a single unit with a word line, and a pair of semiconductor regions that configure the source and drain regions. The bit line, which is provided over the memory-cell-selecting MISFET, is electrically connected to either the source region or the drain region. The data-storage capacitor, which is also provided over the memory-cell-selecting MISFET, is electrically connected to the other region, source or drain.
- To compensate for the reduction in the capacitance of the data-storage capacitor, which accompanies the miniaturization of memory cells, a stacked capacitor configuration, in which the data-storage capacitor is provided over the memory-cell-selecting MISFET, has been used in the DRAMs of recent years. The stacked capacitor configuration can roughly be classified into the following two configurations: a capacitor-under-bit-line (CUB) configuration in which the data-storage capacitor is provided below the bit line, and a capacitor-over-bit-line (COB) configuration in which the data-storage capacitor is provided over the bit line.
- In order to increase the capacitance of the data-storage capacitor, the surface area of the data-storage capacitor must be increased by an upward elongation of the capacitor's semiconductor form. In this case, however, if the CUB configuration, in which the data-storage capacitor is provided below the bit line, is to be employed, the aspect ratio of the contact hole that connects the bit line and the memory-cell-selecting MISFET significantly increases, and as a result, the complete formation of the hole will become difficult. Accordingly, when the above two stacked capacitor configurations are compared, the COB configuration, in which the data-storage capacitor is provided over the bit line, is more suitable for the miniaturization of memory cells than the CUB configuration.
- In the large-scale DRAMs that have appeared recently, for example, 64-Mbit DRAMs and 256-Mbit DRAMs, it has become difficult to obtain enough storage capacitance by applying a simple upward elongation of the data-storage capacitor's configuration to increase its surface area. Accordingly, the use of a material with a high-dielectric constant for a capacitance-insulating film has been investigated. Such materials include Ta2O5 (tantalum pentoxide), (Ba, Sr) TiO3 (barium strontium titanate; hereinafter abbreviated as BST), or SrTiO3 (strontium titanate; hereinafter abbreviated as STO).
- In Official Patent Gazettes H.11-186518 that corresponds to U.S. application Ser. No. 9/209,013 (filed on Dec. 11, 1998) and H.11-238862 that corresponds to U.S. application Ser. No. 9/215,270 (filed on Dec. 18, 1998), a DRAM having COB memory cells is disclosed. The process of fabricating the DRAM disclosed in these Official Patent Gazettes has been simplified; the bit line and the first-layer wiring of the peripheral circuits are formed by the same single step. The bit line and the first-layer wiring are made of, for example, a two-layered conductive film in which a W (tungsten) film is deposited over a TiN (titanium nitride) film.
- In Official Patent Gazette H.11-186518, when the bit line and the first-layer wiring are formed by patterning the two-layered conductive film, the TiN film that configures part of the bit line and part of the first-layer wiring of the peripheral circuits is utilized as an etching stopper that can prevent etching of the W plug inside the contact hole that connects the first-layer wiring with the MISFET of the peripheral circuits. In the Official Patent Gazette H.11-238862, the first-layer wiring of the peripheral circuits is connected to the source and drain of the MISFET without the interposition of a plug. In this configuration, the TiN film under the W film is utilized as a barrier material to prevent the forming of an undesirable silicide layer as a result of reaction at the interface between the W film and the silicon substrate.
- In the Official Gazette H.11-214650, a DRAM is disclosed wherein the bit line and the first-layer wiring of the peripheral circuits are formed concurrently by a so-called Damascene method. In the Damascene method, a two-layered conductive film, comprising a WN (tungsten nitride) film and a W film that is deposited over that, is embedded inside the wiring groove that is formed in the insulating film. In this case, the WN film under the W film acts not only as an adhesive film between the W film and insulating film in the Damascene configuration, but also as a barrier material which prevents the growth of an undesirable silicide layer at the interface between the W film and silicon substrate.
- The DRAM configuration to which this newly invented method is applied is characterized by:
- a COB configuration in which the data-storage capacitor is formed over the bit line so that the capacitance of the data-storage capacitor can be secured;
- a high-dielectric film, for example Ta2O5 (tantalum pentoxide), as a capacitance-insulating film;
- a refractory-metal bit line, for example W, the low resistivity of which improves the signal delay quality; and
- the concurrent forming of the bit line and the first-layer wiring of the peripheral circuit which reduces the number of the fabrication process steps.
- In a DRAM of this configuration, since a through hole that electrically connects the data-storage capacitor with the memory-cell-selecting MISFET is formed between adjacent bit lines, the width of the bit line needs to be reduced to 0.1 μm or less to ensure a margin against short-circuit between the bit line and the plug that has been embedded inside the through hole.
- When forming a 0.1-μm-or-narrower bit line by patterning the W film that has been deposited over the insulating film, for example, silicon oxide, the inventors found that a segregation occurs at the grain boundaries of the W that forms the bit line when high-temperature processing is applied to crystallize the high-dielectric constant material, for example Ta2O5, which forms the capacitance-insulating film of the data-storage capacitor.
- The objective of this invention is to provide a technique that can effectively prevent wiring breaks in the bit lines of a DRAM that has miniaturized memory cells.
- The objectives and novel features of this invention will be clarified by the following specification description together with accompanying drawings.
- A typical example of the invention disclosed in this application is briefly summarized in the following.
- The semiconductor integrated circuit device of this invention comprises:
- memory cells including;
- a memory-cell-selecting MISFET, which is formed over the major surface of a semiconductor substrate, with a gate electrode that is configured in a single unit with a word line; and
- a data-storage capacitor that is formed over a second insulating film which covers the bit line and that is electrically connected to the other part, either source or drain, of the memory-cell-selecting MISFET; and
- a bit line that is formed over a first insulating film which covers the memory-cell-selecting MISFET and that is electrically connected to either the source or drain of the memory-cell-selecting MISFET;
- wherein compressive stress is applied to the conductive film that configures the bit line.
- The semiconductor integrated circuit device of this invention comprises:
- memory cells including;
- a memory-cell-selecting MISFET, which is formed over the major surface of a semiconductor substrate, with a gate electrode that is configured in a single unit with a word line; and
- a data-storage capacitor that is formed over a second insulating film which covers the bit line and that is electrically connected to the other part, either source or drain, of the memory-cell-selecting MISFET; and
- a bit line that is formed over a first insulating film which covers the memory-cell-selecting MISFET and that is electrically connected to either the source or drain of the memory-cell-selecting MISFET;
- wherein the bit line is made of a first conductive film of a W compound and a second conductive film of W that is deposited on the first conductive film, and the width of the bit line is 0.1 μm or less.
- The fabrication method for a semiconductor integrated circuit device of this invention comprises the steps of:
- (a) forming a memory-cell-selecting MISFET with a gate electrode that is configured in a single unit with a word line over the major surface of a semiconductor substrate;
- (b) forming a first insulating film over the memory-cell-selecting MISFET,
- forming a first conductive film over the first insulating film,
- forming a second conductive film over the first conductive film;
- (c) forming an etching-resistant film over the second conductive film,
- thinning the etching-resistant film; and
- (d) forming bit lines made of the first and second conductive films by using a narrow etching-resistant film as a mask in etching the first and second conductive films.
- FIG. 1 is a plan view of the whole of a semiconductor chip over which the DRAM, which is one embodiment of this invention, is formed.
- FIG. 2 is a plan view of a semiconductor substrate that shows part of the storage section of the DRAM which is one embodiment of this invention.
- FIG. 3 is a cross-sectional view through the key parts of the semiconductor substrate that shows the DRAM which is one embodiment of this invention.
- FIG. 4 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 5 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 6 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 7 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 8 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 9 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 10 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 11 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 12 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 13 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 14 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 15 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 16 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 17 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 18 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 19 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 20 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 21 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 22 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 23 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 24 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 25 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 26 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- FIG. 27 is a cross-sectional view through the key parts of the semiconductor substrate that shows the method for fabricating the DRAM which is one embodiment of this invention.
- This invention is described below in detail based on the embodiment that is shown in the accompanying drawings.
- Identical numerical references in the figures describing the embodiment refer to the same items and their descriptions are not repeated. In addition, as a rule, descriptions of identical or similar sections are not repeated except where they are necessary.
- FIG. 1 is a plan view of the whole of
semiconductor chip 1A over which a DRAM that is this embodiment has been formed. A DRAM with a storage capacity of 256 Mbits is formed over the major surface ofrectangular semiconductor chip 1A. This DRAM comprises the storage section made up mainly of memory arrays (MARY) and peripheral circuits PC that are provided at the periphery outside the storage section. In the center ofsemiconductor chip 1A, a number of bonding pads BP that will be connected to wires or bump electrodes are provided in a single line. - FIG. 2, which is a plan view of a semiconductor substrate, shows part of the storage section of the above DRAM, and FIG. 3 is a cross-sectional view through the key parts of the semiconductor substrate of the above DRAM. The left-hand area of FIG. 3 shows the cross-sectional view along the A-A line of FIG. 2, the central area shows the cross-sectional view along the B-B line of FIG. 2, and the right-hand area is a cross-sectional view that shows part of the peripheral circuits.
- For example, element-
isolation groove 2, p-type well 3, and n-type well 4 are formed over the major surface of semiconductor substrate (hereinafter referred to as simply substrate) 1 made of p-type single-crystalline silicon. Memory cells, each of which is made up of n-channel memory-cell-selecting MISFET Qt and data-storage capacitor C formed over that, are formed over the p-type well of the storage section. - Referring to FIG. 2, element-
isolation groove 2 and active regions L which are isolated by element-isolation groove 2 are formed in p-type well 3 in the storage section. These active regions L are formed as long, narrow island patterns, and two memory-cell-selecting MISFETs Qt are formed in each active region L. These two MISFETs Qt use either a common source or a common drain. Element-isolation groove 2 that encloses active region L is formed by embeddingsilicon oxide film 5 in a shallow groove that is formed by etchingsubstrate 1. The surface ofsilicon oxide film 5 is flattened so that its height is almost the same as that of active region L. - Memory-cell-selecting MISFET Qt is made up mainly of gate-insulating
film 6,gate electrode 7A that forms word line WL in the regions outside those used for active region L, and paired n-type semiconductor regions (source and drain) 9 and 9.Gate electrode 7A (word line WL) is made of a so-called polycide film in which a W (tungsten) silicide film is deposited over an n-type polysilicon film which has been doped with, for example, phosphorus (P). The width (gate length) ofgate electrode 7A (word line WL), and the space between pairs ofadjacent gate electrodes 7A (word lines WL) is almost equal to the minimum size that is determined by the restriction placed on size by photolithographic resolution (for example 0.13 to 0.14 μm). - The peripheral circuits of the DRAM are made up of so-called CMOS circuits in which multiple n-channel MISFETs Qn and multiple p-channel MISFETs Qp are combined. Each n-channel MISFET Qn is mainly made up of gate-insulating
film 6,gate electrode 7B, and paired n+-type semiconductor regions (source and drain) 12 and 12, and is formed in p-type well 3. Each p-channel MISFET Qp is mainly made up of gate-insulatingfilm 6,gate electrode 7C, and paired p+-type semiconductor regions (source and drain) 13 and 13, and is formed in n-type well 4. Likegate electrode 7A (word line WL) of memory-cell-selecting MISFET Qt,gate electrodes gate electrodes -
Silicon nitride film 8 is formed overgate electrode 7A (word line WL) of memory-cell-selecting MISFET Qt.Silicon nitride film 11 is deposited over the entire surface of the substrate (includingsilicon nitride 8, the sidewall ofsilicon nitride 8, and the sidewall ofgate electrode 7A (word line WL)). As described later, thesesilicon nitride films gate electrode 7A (word line WL). -
Silicon nitride film 8 is formed overgate electrodes sidewall spacers 11 s are formed on both sidewalls ofgate electrodes silicon nitride film 11. As described later,sidewall spacers 11 s are used so that both the sources and drains of the respective n-channel MIFETs Qn and p-channel MISFETs Qp are configured in an LDD (lightly doped drain) configuration. - Interlayer-insulating
film 15 is formed over memory-cell-selecting MISFET Qt, n-channel MISFET Qn, and p-channel MISFET Qp. Interlayer-insulatingfilm 15 is made of, for example, a spin-on-glass film (silicon-oxide insulating film formed by coating) and a two-layered silicon oxide film formed over that. The interlayer-insulating film is flattened so that the surface height is almost the same over the whole area ofsubstrate 1. - Contact holes16 and 17 are formed over paired n-
type semiconductor regions film 15 and underlyingsilicon nitride film 11.Plug 18 is made of a low-resistance n-type polysilicon film which is doped with, for example, phosphorus (P), and embedded in contact holes 16 and 17. - Referring to FIG. 2, the diameter (both in the X direction parallel to
gate electrode 7A (word line WL) and in the Y direction perpendicular to the X direction) ofcontact hole 17 is nearly the same as the width (in the X-direction) of active region L. By contrast, the diameter (in the X-direction) of the other contact hole 16 (the contact hole over n-type semiconductor region 9 that is a common region for two memory-cell-selecting MISFETs Qt) can be longer than the width (in the X-direction) of active region L. Specifically,contact hole 16 is formed as an approximately rectangular pattern which is wider in the X-direction than it is long in the Y-direction. Part ofcontact hole 16 extends up to the upper region of element-isolation groove 2, which is outside active region L. By designingcontact hole 16 according to the above pattern, bit line BL need not be extended to the upper region of active region L by widening part of bit line BL, or part of active region L need not be extended in the direction of bit line BL, when n-type semiconductor region 9 and bit line BL are electrically connected viacontact hole 16. Consequently, it is possible to reduce the memory size. -
Silicon oxide film 19 is formed over interlayer-insulatingfilm 15, then throughhole 20 is formed insilicon oxide film 19 within the region ofcontact hole 16. Throughhole 20 is designed to be located over element-isolation groove 2 that is situated outside of activeregion L. Plug 23, made of a two-layered conductive film in which a W film is deposited over, for example a TiN (titanium nitride) film, is embedded in throughhole 20.Plug 23 embedded in throughhole 20 is electrically connected to either the source or drain (n-type semiconductor region 9 that is used in common by two memory-cell-selecting MISFETs Qt) of memory-cell-selecting MISFET Qt, with the interposition ofplug 18 embedded incontact hole 16 underplug 23. - Contact holes21 and 22 are formed in
silicon oxide film 19 and underlying interlayer-insulatingfilm 15 for the peripheral circuits.Contact hole 21 is formed over paired n+-type semiconductor regions (source and drain) 12 and 12 that configure the source and drain of n-channel MISFET Qn.Contact hole 22 is formed over paired p−-type semiconductor regions (source and drain) 13 and 13 that configure the source and drain of p-channel MISFET Qp.Plug 23, made of the same conductive material asplug 23 that was earlier embedded in throughhole 20 of said storage section, is embedded in contact holes 21 and 22. - Bit lines BL, for reading the data from the memory cells, are formed over
silicon oxide film 19 of the storage section. These bit lines BL, provided over element-isolation groove 2, extend with a uniform line width and spacing between lines in the direction perpendicular togate electrode 7A (word line WL). Each bit line BL is electrically connected, viaplug 23 in said throughhole 20 insilicon oxide film 19 under the bit lines and viaplug 18 incontact hole 16 undersilicon oxide film 19, to either the source or drain (n-type semiconductor region 9) of each memory-cell-selecting MISFET Qt that runs parallel to bit lines BL. - Bit lines BL should be as narrow as possible so that spacing is sufficient to ensure a margin against short-circuit with
plug 44 that has been embedded in throughhole 43 formed in the space between the adjacent bit lines. The parasitic capacitance between adjacent bit lines is thus also reduced. For the DRAM of this embodiment, the width of bit line BL is 0.1 μm or narrower. This is narrower than the width (0.13 to 0.14 μm) ofgate electrode 7A (word line WL) as described above and the space (0.13 to 0.14 μm) between pairs ofadjacent gate electrodes 7A (word lines WL). That is, a narrower bit line BL is formed than the minimum size as determined by the limitations on photolithographic resolution. The method for forming such fine bit lines BL is described later. - As a countermeasure against wiring-break failures in bit lines BL that are as narrow as 0.1 μm or narrower, bit line BL of the DRAM of this embodiment is made of a two-layered conductive film in which
W film 25 is deposited on WN (tungsten nitride)film 24. The following paragraphs explain, on the basis of the results of investigations by the inventors, how wiring failures can be avoided using said two-layered conductive film to form, oversilicon oxide film 19, a 0.1-μm-or-narrower bit line BL. - In general, when a W film is deposited on a given foundation film, the W atoms will not be in an orderly alignment if there is a large difference between the lattice constants of the foundation material and W. As a result, segregations appear at the interface, and surface diffusion of W atoms is liable to occur because W atoms move along the segregations that are generated at the interface with the foundation film. Therefore, the surface diffusion distance of W atoms increases with the extent of the segregations. On the other hand, when there is little difference between the lattice constants of the foundation material and W, it is possible for the W atoms to be in an orderly alignment. As a result, the region of segregations at the interface between the two lattices is significantly narrower, and consequently, the surface diffusion distance of W atoms is shortened.
- Vacancies and dislocations inside crystal grains contribute to the diffusion paths for atoms, so atoms are more likely to travel within grains if the grains contain many vacancies or dislocations. Accordingly, when a film is formed under conditions that readily bring the arrangement of the W atoms into disorder, the number of W atoms at the grain boundaries decreases, since many of the W atoms tend to diffuse to fill up the vacancies and dislocations. This is the case when the difference between the lattice constants of the foundation material and W is great and the W film is then subjected to high-temperature thermal processing.
- There is a large difference between the lattice constants of silicon oxide and W. Accordingly, when
W film 25 is directly deposited onsilicon oxide film 19, large segregations grow at the interface between the two films, and many vacancies and dislocations are generated within the crystal grains ofW film 25. The inventors have found that there is a tensile stress insideW film 25 after a bit line has been formed by patterningW film 25 which has been directly deposited onsilicon oxide film 19. - In the DRAM fabrication process, when a thermal processing at a temperature higher than the temperature at which
W film 25 is formed is carried out after the bit lines have been formed, many W atoms are diffused across the interface betweenW film 25 that forms the bit lines andsilicon oxide film 19 formed under that, within the crystal grains, and at the grain boundary ofW film 25, and the number of W atoms at the grain boundaries is thus decreased. As a result, segregations appear at the grain boundaries because of the tensile stress generated insideW film 25. In this case, when the bit line is sufficiently wider than the grain size ofW film 25, wiring breaks do not occur immediately. However, when the wiring width is narrowed to approximately 0.1 μm, which is equal to the average grain size ofW film 25, wiring breaks occur. - By contrast, there is only a small difference between the lattice constants of WN and W. Accordingly, when
W film 25 is deposited onWN film 24, W atoms are in an orderly arrangement that accords with the arrangement of the WN atoms. In such cases, the segregations at the interface are significantly narrower, and a tightly-packed and finely-grained film, with few vacancies or dislocations inside its crystal grains, can thus be obtained. In addition, the inventors have found that a compressive stress is generated insideW film 25 even when bit line BL is formed by the patterning of a two-layered conductive film in whichW film 25 is deposited onWN film 24. - As described thus far, in bit line BL that is made of a two-layered conductive film in which
W film 25 is deposited onWN film 24, few W atoms are diffused across the interface betweenW film 25 andWN film 24 under that, within crystal grains and at the grain boundaries ofW film 25. In addition, no tensile stress is generated insideW film 25. Therefore, wiring breaks are not caused by high-temperature processing even when the wiring width is narrowed to 0.1 μm or less. - Materials with lattice constants that are close to that of W include Mo (molybdenum) and its compounds such as MoN (molybdenum nitride), MoB (molybdenum boride), and MoC (molybdenum carbide), as well as WN. By forming bit lines BL of two-layered conductive films in which a W film is deposited on an Mo film or Mo-compound film, wiring breaks can be prevented even when the width of bit line BL is narrowed to 0.1 μm or less. TiN is also used as a barrier material though the difference between its lattice constant and that of W is greater than the differences for WN, Mo, and its compounds. However, a w film has compressive stress when it is deposited on a TiN film. Therefore, by forming bit lines BL of two-layered conductive films in which a W film is deposited on a TiN film, the wiring-break rate can be reduced even when the width of bit line BL is narrowed to 0.1 μm or less.
- As shown in FIG. 3, first-
layer wires 30 to 33 are formed oversilicon oxide film 19 in the peripheral circuits.Wires 30 to 33 are made of two-layered conductive films in whichW film 25 is deposited onWN film 24, in a similar way to and at the same time as bit lines BL as is described later.Wires silicon oxide films Wires silicon oxide films - Interlayer-insulating
film 40 is formed over bit line BL and first-layer wires 30 to 33. Interlayer-insulatingfilm 40 is made of a spin-on-glass film and a two-layered silicon oxide film which is formed over the spin-on-glass film, in a similar way to the formation of lower interlayer-insulatingfilm 15.Film 40 is flattened so that the surface height is almost the same over the whole area ofsubstrate 1. - In the storage section, through
holes 43 are formed in interlayer-insulatingfilm 40 andsilicon oxide film 19 under interlayer-insulatingfilm 40. Through-holes 43 are located directly above contact holes 17, and plugs 44 that are made of low-resistance n-type polysilicon films which have been doped with P (phosphorus) are embedded in through-holes 43. -
Silicon nitride film 45 and thicksilicon oxide film 46 are formed over interlayer-insulatingfilm 40. In the storage section,deep grooves 47 are formed insilicon oxide film 46. Data-storage capacitors C, which are configured bylower electrode 48, capacitance-insulatingfilm 49, andupper electrode 50, are formed indeep grooves 47.Lower electrodes 48 of data-storage capacitors C are made of a low-resistance n-type polysilicon film which has been doped with P (phosphorus).Lower electrodes 48 are electrically connected to n-type semiconductor regions (source and drain) 9 of memory-cell-selecting MISFETs Qn via throughhole 43 andcontact hole 17 that have been formed underlower electrode 48. Capacitance-insulatingfilm 49 of data-storage capacitor C is a Ta2O5 (tantalum pentoxide) film, etc.Upper electrode 50 is made of a TiN film, etc. -
Silicon oxide film 51 is then formed over data-storage capacitor C, and two or so layers of Al are formed as wiring (not shown) oversilicon oxide film 51. - FIGS.4 to 27 are now used in describing an example of a method of fabricating a DRAM that is related to the embodiment as configured above.
- As shown in FIG. 4, the element-isolation region of
substrate 1 is etched to form element-isolation groove 2 with a depth of about 350 nm on the major surface of p-type single-crystalline silicon substrate 1. B (boron) ions are then implanted into parts ofsubstrate 1 to form p-type wells 3 and P (phosphorus) ions are implanted into other parts ofsubstrate 1 to form n-type wells 4.Silicon oxide film 5 is then deposited by chemical vapor deposition (CVD) in the grooves and oversubstrate 1, and the superfluous part ofsilicon oxide film 5 that protrudes beyond the groove is removed by chemical mechanical polishing (CMP). As shown in FIG. 5, active regions L, which are the long, narrow island patterns that are surrounded by element-isolation grooves 2, are formed insubstrate 1 in the storage section by the formation of element-isolation grooves 2. - Gate-insulating
film 6 is formed of silicon oxide over p-type well 3 and n-type well 4 by the thermal oxidation ofsubstrate 1. As shown in FIGS. 6 and 7,gate electrodes 7A (word lines WL) are then formed over gate-insulatingfilm 6 in the storage section, andgate electrodes film 6 in the peripheral circuits. A polysilicon film which has been doped with P (phosphorus) is deposited oversubstrate 1 by CVD to formgate electrodes silicon nitride film 8 is deposited over the W 'silicide film by CVD.Silicon nitride film 8 is patterned by using a photoresist film as a mask against dry etching, and the W silicide film and polysilicon film are then patterned by usingsilicon nitride film 8 as a mask against dry etching. As shown in FIG. 7,gate electrodes 7A (word lines WL) run perpendicularly across the longer sides of active regions L, and the gate length and the space betweenadjacent gate electrodes 7A (word lines WL) are both in the 0.13 to 1.4-μm range. - As shown in FIG. 8, As (arsenic) ions are implanted in p-type well3 on both sides of
gate electrodes type semiconductor regions 9 in p-type well 3. In addition, B (boron) ions are implanted in n-type well 4 on both sides ofgate electrode 7C to form p−-type semiconductor regions 10 in n-type well 4. -
Silicon nitride film 11 is deposited oversubstrate 1 by CVD. As shown in FIG. 9, the storage sections ofsubstrate 1 are then covered by a photoresist film (not shown), andsilicon nitride film 11 in the peripheral circuits is anisotropically etched. As a result, side-wall spacers 11 s are formed on both sidewalls ofgate electrodes - In the peripheral circuits, P ions are implanted into p-type well3 to form n+-type semiconductor regions (source and drain) 12 with a high concentration of impurities, and B ions are implanted into n-type well 4 to form p+-type semiconductor regions (source and drain) 13 with a high concentration of impurities. The above processes complete the formation of n-channel MISFET Qn and p-channel MISFET Qp in the peripheral circuits.
- As shown in FIG. 10, interlayer-insulating
film 15 made of a spin-on-glass film and a two-layered silicon oxide film is formed overgate electrodes film 15 is formed by spin-coating a spin-on-glass film overgate electrodes gate electrodes 7A (word lines WL) of the storage section are extremely narrow, the space can be filled perfectly by using the spin-on-glass film. After a silicon oxide film is deposited by CVD over the spin-on-glass film, the silicon oxide film is polished and flattened by CMP to make the heights of the storage section and peripheral circuits uniform. The second silicon oxide film is then deposited by CVD over the first silicon oxide film to cover the fine scratches on the surface of the lower (first) silicon oxide film that are caused by CMP. - As shown in FIGS. 11 and 12, interlayer-insulating
films 15 over n−-type semiconductor regions 9 in the storage section are removed by dry etching. A photoresist film (not shown) is used as a mask. The condition for this etching is that the rate of etching of interlayer-insulating films 15 (the spin-on-glass film and silicon oxide film) must be greater than that ofsilicon nitride films -
Silicon nitride film 11 is removed from n-type semiconductor regions 9 by dry etching, using a photoresist film as a mask, and the surface of n−-type semiconductor regions 9 is then exposed so that contact holes 16 and 17 are thus formed. The condition for the etching ofsilicon nitride film 11 is that the etching rate ofsilicon nitride film 11 is greater than that ofsilicon oxide film 5 embedded in element-isolation groove 2. This is so thatsilicon oxide film 5 in element-isolation groove 2 is not etched deeply.Silicon nitride film 11 is anisotropically etched andsilicon nitride film 11 thus remains on both sidewalls ofgate electrodes 7A (word lines WL). Therefore, contact holes 16 and 17 are formed with fine diameters by a self-alignment method with regard togate electrodes 7A (word lines WL). As earlier described, part of long-patternedcontact hole 16 extends up to the upper region of element-isolation groove 2, which is outside active region L. - As shown in FIG. 13, plugs18 are formed in contact holes 16 and 17. To form plugs 18, a low-resistance polysilicon film which has been doped with P is deposited by CVD in contact holes 16 and 17 and over interlayer-insulating
film 15, and the superfluous polysilicon film over interlayer-insulatingfilm 15 is removed by dry etching. -
Substrate 1 is thermal-processed in an atmosphere of nitrogen and the P in the polysilicon film which configuresplug 18 is diffused into n−-type semiconductor regions 9 to form low-resistance n-type semiconductor regions 9 (source and drain). The above processes complete the creation of memory-cell-selecting MISFET Qt in the storage section. - As shown in FIGS. 14 and 15, after
silicon oxide film 19 has been deposited by CVD over interlayer-insulatingfilm 15, a photoresist film (not shown) is used as a mask in the dry etching ofsilicon oxide film 19 and interlayer-insulatingfilm 15 in the peripheral circuits. As a result, contact holes 21 are formed above the source and drain of n-channel type MISFET Qn (n+-type semiconductor region 12), and contact holes 22 are formed above the source and drain of p-channel type MISFET Qp (p+-type semiconductor region 13). At the same time,silicon oxide film 19 in the storage section is etched to form throughhole 20 overcontact hole 16. - As shown in FIG. 16, plugs23 are formed in contact holes 21 and 22 that have been formed in the peripheral circuits and in through
hole 20 that has been formed in the storage section.Plugs 23 are formed of TiN and W films that are deposited, by sputtering and CVD, oversilicon oxide film 19, in contact holes 21 and 22, and in throughhole 20. The superfluous TiN and W films oversilicon oxide film 19 are then removed by CMP. - As shown in FIG. 17,
WN film 24 andW film 25 are deposited, by sputtering and in that order, oversilicon oxide film 19. As earlier described, the deposition ofW film 25 onWN film 24 leads to a more tightly-packed and finely-grained W film 25 with greatly-narrow interfacial segregations and with fewer vacancies and dislocations in the crystal grains, than would be obtained by the direct deposition ofW film 25 onsilicon oxide film 19. - As shown in FIG. 18, photoresist masks26 are formed over
W film 25. The width ofphotoresist mask 26 formed overW film 25 in the storage section is around 0.18 to 0.2 - As shown in FIG. 19, photoresist masks26 are narrowed using active oxygen radicals, which can be generated by the irradiation of ozone by ultraviolet rays, in the well-known ashing process. This process narrows the line widths of
photoresist masks 26s formed overW film 25 in the storage section to, for example, around 0.12 to 0.13 - As shown in FIGS. 20 and 21, narrowed
photoresist masks 26 s are used in patterningW film 25 andWN film 24 by dry etching to form bit lines BL oversilicon oxide film 19 in the storage section andwires 30 to 33 oversilicon oxide film 19 in the peripheral circuits. Etching ofW film 25 andWN film 24 is, to a certain degree, isotropic. Both sidewalls of bit lines BL (andwires 30 to 33) are thus etched, and bit lines BL with a width of 0.1 μm or less, which is narrower than the line widths ofphotoresist masks 26 s, can in this way be obtained. In addition, sinceW film 25 andWN film 24 are etched at almost the same rate, bit lines BL (andwires 30 to 33) can be formed with a high degree of accuracy in terms of size. Similarly, since the Mo film and Mo-compound film are etched at almost the same rate as theW film 25, bit lines BL (andwires 30 to 33) can still be formed with a high degree of accuracy in terms of size, even whenWN film 24 is replaced by an Mo film or an Mo-compound film. - After
photoresist masks 26s have been entirely removed by the ashing process, interlayer-insulatingfilm 40 is formed over bit lines BL andwires 30 to 33, as is shown in FIG. 22. Interlayer-insulatingfilm 40 is formed by the same process as was used to form interlayer-insulatingfilm 15. - As shown in FIGS. 22 and 23, through
holes 43 are formed above contact holes 17 by etching of interlayer-insulatingfilm 40 andsilicon oxide film 19 in the storage section.Polysilicon film 41 andsidewall spacers 42 made of a polysilicon film, which are formed over interlayer-insulatingfilm 40, are used as etching-resistant masks. As earlier described, since bit lines BL are narrowed to 0.1 μm or less, and the spaces between the bit lines are thus widened, a sufficient margin against short-circuit withplug 44, which has been embedded in throughhole 43 that was formed in the space between bit lines BL, can thus be ensured. - After
polysilicon film 41 andsidewall spacers 42 have been removed by dry etching, plug 44 is formed in throughhole 43, as is shown in FIG. 24. A low-resistance polysilicon film doped with P (phosphorus) is deposited in throughhole 43 and over interlayer-insulatingfilm 40 by CVD to formplug 44. Any superfluous polysilicon film over interlayer-insulatingfilm 40 is removed by dry etching (or CMP). -
Silicon nitride film 45 is deposited over interlayer-insulatingfilm 40 by CVD, andsilicon oxide film 46 is then deposited oversilicon nitride film 45 by CVD. To formdeep grooves 47 over throughholes 44,silicon oxide film 46 andsilicon nitride film 45 are then etched, in the storage section, with a photoresist film (not shown) as the mask. - As is shown in FIG. 25,
lower electrodes 48 of data-storage capacitors C are formed of polysilicon films on the sidewalls ingrooves 47. To formlower electrodes 48, an amorphous silicon film (not shown) which has been doped with P (phosphorus) is deposited by CVD ingrooves 47 and oversilicon oxide film 46. Any superfluous amorphous silicon film oversilicon oxide film 46 is removed by dry etching. - The surface of the amorphous silicon film that remains in
grooves 47 is wet-cleaned by using some kinds of hydrofluoric acid. The amorphous silicon film is then exposed to a low-pressure atmosphere that supplies monosilane (SiH4) to its surface.Substrate 1 is then thermally processed to crystallize the surface of the amorphous silicon film into grains of silicon. In this way,lower electrodes 48 are formed of grainy polysilicon film. Since a grainy polysilicon film has a large surface area, it is possible to increase the storage capacitance of the refined data-storage capacitor. - As shown in FIG. 26, a Ta2O5 (tantalum pentoxide) film is deposited, by CVD, over the surface of
lower electrodes 48 formed ingrooves 47 and over the surface ofsilicon oxide film 46outside grooves 47. This film forms the capacitance-insulatingfilm 49 of data-storage capacitor C. -
Substrate 1 is thermally processed in an atmosphere of oxygen to improve and crystallize the Ta2O5 film. This thermal processing produces a high-quality Ta2O5 film, with a dielectric constant of 20 to 25, and with better current-leakage characteristics. This thermal processing used to improve and crystallize the Ta2O5 film is carried out in an atmosphere of oxygen and at temperatures in the range from 750 to 800° C. Although bit lines BL below are exposed to high temperatures by this treatment, no wiring break occurs. This is because bit lines BL are made of two-layered conductive films, in whichW film 25 has been deposited overWN film 24, and fewer atoms of W thus diffused across the interface betweenW film 25 andWN film 24, within crystal grains, and at grain boundaries inW film 25, as earlier described, and no tensile stress exists inW film 25. - Capacitance-insulating
film 49 of data-storage capacitor C can also be made of a film which is mainly comprised of a substance with a high-dielectric constant or a ferroelectric substance with a perovskite or complex-perovskite crystal structure, such as PZT, PLT, PLZT, PbTiO3, SrTiO3, BaTiO3, BST, SBT, or Ta2O5. Even when a film of a substance with a high-dielectric constant or of a ferroelectric substance such as is listed above is used, high-temperature thermal processing is still required to improve and crystallize the film. In the same way as is described above, however, the high-temperature thermal processing will still not cause wiring breaks in bit lines BL. - As shown in FIG. 27, after the TiN film has been deposited in
grooves 47 and over capacitance-insulatingfilm 49 by a series of CVD and sputtering processes, the TiN and Ta2O5 films are patterned by dry etching with a photoresist film (not shown) as a mask. The above processes configure data-storage capacitor C withupper electrode 50 made of the TiN film, capacitance-insulatingfilm 49 made of the Ta2O5 film, andlower electrode 48 made of a polysilicon film. The DRAM memory cell is thus configured by memory-cell-selecting MISFET Qt and data-storage capacitor C that is connected, in series, to memory-cell-selecting MISFET Qt. -
Silicon oxide film 50 is then deposited over data-storage capacitor C by CVD, and two or so layers of Al are formed as wiring (not shown) oversilicon oxide film 50 to complete the DRAM that is this embodiment and is shown in FIGS. 2 and 3. - This invention was described in detail above on the basis of an embodiment. However, this invention is not restricted to this embodiment; various modifications are possible without deviating from the essential points of the invention.
- This embodiment was used to describe the situation in which wiring breaks in DRAM bit lines are to be prevented. Since the gate electrodes of the MISFET will be made yet finer, with gate lengths of 0.1 μm or less, as LSIs are miniaturized and more densely integrated, the wiring breaks of gate electrodes made of conductive films that is including a W film will still be a problem. Even in this case, the wiring breaks of the gate electrodes can still be effectively prevented by forming the gate electrode with a WN film with its lattice constant which is close to that of W, a two-layered conductive film in which the W film is deposited over an Mo film or an Mo-compound film, or a polymetal-structured conductive film in which a polysilicon film is formed under the two-layered conductive film.
- Typical advantages obtained from the invention disclosed in this application are briefly described in the following paragraph.
- This invention effectively prevents wiring breaks in bit lines of fine width, and DRAM-memory size can thus be reduced to implement larger-scale integrated memory.
Claims (39)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/208,771 US20020190295A1 (en) | 2000-03-01 | 2002-08-01 | Semiconductor integrated circuit device and the process of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000055621A JP2001244436A (en) | 2000-03-01 | 2000-03-01 | Semiconductor integrated circuit device and manufacturing method thereof |
JP2000-055621 | 2000-03-01 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/208,771 Continuation US20020190295A1 (en) | 2000-03-01 | 2002-08-01 | Semiconductor integrated circuit device and the process of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010050386A1 true US20010050386A1 (en) | 2001-12-13 |
US6429476B2 US6429476B2 (en) | 2002-08-06 |
Family
ID=18576712
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/795,190 Expired - Fee Related US6429476B2 (en) | 2000-03-01 | 2001-03-01 | Semiconductor integrated circuit device |
US10/208,771 Abandoned US20020190295A1 (en) | 2000-03-01 | 2002-08-01 | Semiconductor integrated circuit device and the process of manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/208,771 Abandoned US20020190295A1 (en) | 2000-03-01 | 2002-08-01 | Semiconductor integrated circuit device and the process of manufacturing the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US6429476B2 (en) |
JP (1) | JP2001244436A (en) |
KR (1) | KR20010087207A (en) |
TW (1) | TW495964B (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6465356B2 (en) * | 2000-06-28 | 2002-10-15 | Hyundai Electronics Industries Co., Ltd. | Method for forming fine patterns by thinning developed photoresist patterns using oxygen radicals |
US20100078729A1 (en) * | 2007-03-27 | 2010-04-01 | Fujitsu Microelectronics Limited | Semiconductor device and method of manufacturing the semiconductor device |
US20130119509A1 (en) * | 2011-11-16 | 2013-05-16 | International Business Machines Corporation | Forming beol line fuse structure |
US8975127B2 (en) | 2007-06-11 | 2015-03-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9653564B2 (en) | 2015-03-26 | 2017-05-16 | Toyoda Gosei Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20200212170A1 (en) * | 2018-12-28 | 2020-07-02 | Samsung Electronics Co., Ltd. | Semiconductor device including capacitor and method of forming the same |
CN112864098A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
KR20210123182A (en) * | 2020-04-01 | 2021-10-13 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor memory structure |
US11497879B2 (en) * | 2013-03-15 | 2022-11-15 | ResMed Pty Ltd | Humidifier reservoir |
US20230157029A1 (en) * | 2021-11-12 | 2023-05-18 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US20230180462A1 (en) * | 2021-12-06 | 2023-06-08 | Nanya Technology Corporation | Semiconductor device with air gap |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566148B2 (en) * | 2001-08-13 | 2003-05-20 | Sharp Laboratories Of America, Inc. | Method of making a ferroelectric memory transistor |
US6602749B2 (en) * | 2001-09-17 | 2003-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance |
US6720232B1 (en) * | 2003-04-10 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure |
US6921692B2 (en) * | 2003-07-07 | 2005-07-26 | Micron Technology, Inc. | Methods of forming memory circuitry |
JP4746357B2 (en) * | 2005-06-09 | 2011-08-10 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
KR100735753B1 (en) * | 2005-10-04 | 2007-07-06 | 삼성전자주식회사 | Flash memory device having a shared bit line and fabrication method thereof |
JP5280716B2 (en) * | 2007-06-11 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
KR100902106B1 (en) * | 2007-10-31 | 2009-06-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with tungsten contained pattern |
KR101006531B1 (en) * | 2009-05-11 | 2011-01-07 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
US8283713B2 (en) * | 2010-06-02 | 2012-10-09 | Lsi Corporation | Logic-based eDRAM using local interconnects to reduce impact of extension contact parasitics |
KR101007175B1 (en) * | 2010-06-18 | 2011-01-12 | 네스트리 주식회사 | Method for control a shutter glasses for 3-d display and 3-d display system |
KR101725446B1 (en) * | 2011-08-24 | 2017-04-12 | 삼성전자주식회사 | Semiconductor Devices and Methods of Fabricating the Same |
JP5863381B2 (en) * | 2011-10-17 | 2016-02-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
KR101902870B1 (en) * | 2012-04-10 | 2018-10-01 | 삼성전자주식회사 | Semiconductor Device Having a DC Structure |
US11164816B2 (en) | 2019-09-05 | 2021-11-02 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
JP7373667B2 (en) * | 2021-08-02 | 2023-11-02 | チャンシン メモリー テクノロジーズ インコーポレイテッド | Semiconductor structure and its manufacturing method |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2555103B2 (en) * | 1987-11-13 | 1996-11-20 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
SG54456A1 (en) * | 1996-01-12 | 1998-11-16 | Hitachi Ltd | Semconductor integrated circuit device and method for manufacturing the same |
JP3869089B2 (en) * | 1996-11-14 | 2007-01-17 | 株式会社日立製作所 | Manufacturing method of semiconductor integrated circuit device |
JPH11214650A (en) | 1998-01-23 | 1999-08-06 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
2000
- 2000-03-01 JP JP2000055621A patent/JP2001244436A/en active Pending
-
2001
- 2001-02-14 TW TW090103286A patent/TW495964B/en not_active IP Right Cessation
- 2001-02-27 KR KR1020010009885A patent/KR20010087207A/en not_active Application Discontinuation
- 2001-03-01 US US09/795,190 patent/US6429476B2/en not_active Expired - Fee Related
-
2002
- 2002-08-01 US US10/208,771 patent/US20020190295A1/en not_active Abandoned
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6465356B2 (en) * | 2000-06-28 | 2002-10-15 | Hyundai Electronics Industries Co., Ltd. | Method for forming fine patterns by thinning developed photoresist patterns using oxygen radicals |
US9786565B2 (en) * | 2007-03-27 | 2017-10-10 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the semiconductor device |
US20100078729A1 (en) * | 2007-03-27 | 2010-04-01 | Fujitsu Microelectronics Limited | Semiconductor device and method of manufacturing the semiconductor device |
US8975127B2 (en) | 2007-06-11 | 2015-03-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9184126B2 (en) | 2007-06-11 | 2015-11-10 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9601433B2 (en) | 2007-06-11 | 2017-03-21 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9812317B2 (en) | 2007-06-11 | 2017-11-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10096467B2 (en) | 2007-06-11 | 2018-10-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9059175B2 (en) * | 2011-11-16 | 2015-06-16 | International Business Machines Corporation | Forming BEOL line fuse structure |
US9263386B2 (en) | 2011-11-16 | 2016-02-16 | International Business Machines Corporation | Forming BEOL line fuse structure |
US20130119509A1 (en) * | 2011-11-16 | 2013-05-16 | International Business Machines Corporation | Forming beol line fuse structure |
US11497879B2 (en) * | 2013-03-15 | 2022-11-15 | ResMed Pty Ltd | Humidifier reservoir |
US9653564B2 (en) | 2015-03-26 | 2017-05-16 | Toyoda Gosei Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20200212170A1 (en) * | 2018-12-28 | 2020-07-02 | Samsung Electronics Co., Ltd. | Semiconductor device including capacitor and method of forming the same |
US10916623B2 (en) * | 2018-12-28 | 2021-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device including capacitor and method of forming the same |
CN111384054A (en) * | 2018-12-28 | 2020-07-07 | 三星电子株式会社 | Semiconductor device including capacitor |
CN111384054B (en) * | 2018-12-28 | 2024-01-09 | 三星电子株式会社 | Semiconductor device including capacitor |
KR20210123182A (en) * | 2020-04-01 | 2021-10-13 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor memory structure |
KR102403387B1 (en) | 2020-04-01 | 2022-06-02 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor memory structure |
US11462282B2 (en) * | 2020-04-01 | 2022-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory structure |
US11942169B2 (en) | 2020-04-01 | 2024-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory structure |
CN112864098A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
US20230157029A1 (en) * | 2021-11-12 | 2023-05-18 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US20230180462A1 (en) * | 2021-12-06 | 2023-06-08 | Nanya Technology Corporation | Semiconductor device with air gap |
US11985816B2 (en) * | 2021-12-06 | 2024-05-14 | Nanya Technology Corporation | Semiconductor device with air gap |
Also Published As
Publication number | Publication date |
---|---|
US20020190295A1 (en) | 2002-12-19 |
JP2001244436A (en) | 2001-09-07 |
TW495964B (en) | 2002-07-21 |
US6429476B2 (en) | 2002-08-06 |
KR20010087207A (en) | 2001-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6429476B2 (en) | Semiconductor integrated circuit device | |
US6794698B1 (en) | Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls | |
US5796133A (en) | Semiconductor device capacitor having lower electrodes separated by low dielectric spacer material | |
KR940009628B1 (en) | Capacitor and manufacturing method thereof | |
US6258649B1 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
US6770527B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
US6727542B2 (en) | Semiconductor memory device and method for manufacturing the same | |
US20050280154A1 (en) | Semiconductor memory device | |
US6664157B2 (en) | Semiconductor integrated circuit device and the method of producing the same | |
US6288446B2 (en) | Semiconductor device with pillar-shaped capacitor storage node | |
KR20000022801A (en) | Semiconductor device and manufacturing method thereof | |
US6072210A (en) | Integrate DRAM cell having a DRAM capacitor and a transistor | |
US6444405B1 (en) | Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate | |
US20040023465A1 (en) | Memory cell capacitors having an over/under configuration | |
KR100189963B1 (en) | Semiconductor memory device and its manufacture | |
US6054394A (en) | Method of fabricating a dynamic random access memory capacitor | |
US6392264B2 (en) | Semiconductor memory device and method of producing the same | |
US6791137B2 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
KR0161425B1 (en) | Formation method of wiring semiconductor device | |
US6482727B2 (en) | Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device | |
US6090663A (en) | Method for forming a high-density DRAM cell with a rugged polysilicon cup-shaped capacitor | |
US6329244B1 (en) | Method of manufacturing dynamic random access memory cell | |
JP3030812B2 (en) | Manufacturing method of DRAM capacitor using chemical mechanical polishing method | |
JP2001217406A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
US6114214A (en) | Method for forming a high-density dram cell with a double-crown rugged polysilicon capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HITACHI, LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, MASAYUKI;YAMADA, KENTARO;SAHARA, MASASHI;AND OTHERS;REEL/FRAME:011579/0212;SIGNING DATES FROM 20001226 TO 20010118 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:026109/0528 Effective date: 20110307 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140806 |