US20010045642A1 - Die-to-insert permanent connection and method of forming - Google Patents
Die-to-insert permanent connection and method of forming Download PDFInfo
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- US20010045642A1 US20010045642A1 US09/915,236 US91523601A US2001045642A1 US 20010045642 A1 US20010045642 A1 US 20010045642A1 US 91523601 A US91523601 A US 91523601A US 2001045642 A1 US2001045642 A1 US 2001045642A1
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- conductive bumps
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Definitions
- This invention relates generally to die-to-insert interconnections and, more specifically, to a method of forming a permanent die-to-insert electrical connection for a semiconductor die assembly by diffusing gold bumps on the insert into the bond pads of the die using relatively low elevated temperatures and low levels of constant force during the extended time of a burn-in process.
- WB wirebonding
- TAB Tape Automated Bonding
- C4 Controlled Collapse Chip Connection
- WB is the most common chip-bonding technology because the required number of chip connections in many products can be accomplished in addition to providing the lowest cost per connection.
- WB is generally employed to electrically connect chips to the inner ends of the leads of a lead frame, the assembly subsequently being packaged as by transfer molding of a plastic package.
- TAB may be used for chips requiring more than 257 but less than 600 connections.
- TAB employs lead frames of a finer pitch mounted on an insulative carrier tape which is integrated into the chip package.
- the C4 process is capable of creating up to 16,000 connections per chip (or partial wafer), potentially meeting the demand for any number of connections that the die or partial wafer design dictates.
- solder bumps are deposited on wettable metal terminals (bond pads) on the chip, and a matching footprint of solder-wettable terminals is located on the substrate. Both the bond pads and the terminals must be treated with solder flux. Moreover, the solder bumps must be constrained from completely collapsing (or flowing out onto the substrate bonding site) by using thick-film glass dams, or stops. The tendency for the solder to flow on the chip is contained by a special bonding pad metallurgy that consists of a circular pad of evaporated chromium, copper, and gold.
- the bond pad metallurgy is then coated by evaporation with, for example, 5Sn-95Pb or 2Sn-98Pb, to a thickness of 100 to 125 ⁇ m.
- the upside-down chip or die flip-chip is aligned to the substrate, and all chip-to-substrate conductive paths are made simultaneously by reflowing the solder.
- VLSI Very Large Scale Integration
- pressure contact interconnect methods are also known in the art.
- Pressure contacts are not actually bonded but rather form a continuous contact using a material deformation concept such as a metal spring or an elastic retainer.
- a material deformation concept such as a metal spring or an elastic retainer.
- two gold bumps on chip and substrate
- a conductive rubber contact embedded in a polyamide carrier may be joined by a conductive rubber contact embedded in a polyamide carrier.
- this is a mechanically created connection and is, therefore, not as desirable as metallurgical bonding techniques for economic-as well as reliability-associated reasons.
- chip-to-substrate interconnections are typically effected after a burn-in operation is performed on the chip to determine if the chip is defective.
- a chip is typically placed in a multi-chip carrier in resiliently biased or other temporary connection to a burn-in die or substrate (also called an insert) having circuit traces and contacts for electrical testing of the chip.
- the chips are generally subjected to electrical impulses and elevated temperatures (on the order of 125-150° C.) for extended periods of time, usually 24-48 hours, depending upon the chip and the characterization protocol.
- Low-temperature cycling to as low as ⁇ 50° C. may also be employed on occasion, particularly for chips being qualified to military specifications. However, this is not common for chips destined for use in commercial applications.
- the chip is removed from its test fixture after burn-in and is then permanently attached to a substrate by means known in the art, such as those previously mentioned.
- the chip may be wirebonded to a lead frame or TAB-bonded to a taped lead frame, as known in the art, depending upon the ultimate application for the chip and preferred packaging for that application.
- burn-in connections and permanent operational connections are effected in the prior art in two distinct and different operations. While it would be possible to form permanent die-to-insert connections before burn-in, this would increase processing time and cost.
- MCM multi-chip modules
- SIMM single in-line memory modules
- Temporary chip-to-burn-in die or insert connections are also known in the art and exemplified by the disclosures of U.S. Pat. Nos. 5,440,241; 5,397,997; and 5,249,450. None of the foregoing patents, however, discloses a methodology for forming suitably permanent die-to-substrate electrical connections during burn-in.
- a method for forming a permanent chip-to-insert interconnection is herein disclosed.
- Gold bumps are attached to ends of conductive circuit traces on one side or the other of a nonelectrically conductive substrate, or even the exposed ends of internal conductors, by which electrical testing of a chip during burn-in is effected.
- the term “gold” includes not only elemental gold, but gold with other trace metals and in various alloyed combinations with other metals as known in the semiconductor art.
- the die has bond pads on one surface (commonly termed the “front” or “active” surface) formed of aluminum or an aluminum alloy. The bond pads are arranged as a mirror image of the gold bumps located on the surface of the substrate. Thus, when the bond pads are placed on top of the gold bumps, they are in substantial alignment with each other.
- the substrate material is selected such that the coefficient of thermal expansion (CTE) is similar to that of the die or semiconductor chip. This assures that both the substrate and the die expand and contract in a similar manner when subjected to elevated temperatures during a burn-in process so that the bond pads on the die will stay in relatively precise alignment with the gold bumps on the substrate, producing little or no shear force between any bond pad and its corresponding bump.
- the substrate may be comprised of Mullite, a ceramic material such as 203 aluminum oxide, or any other material known in the art that has a CTE similar to that of the die.
- the bond pads and gold bumps are pressed together.
- the die/substrate assembly is then heated to effect a bond between the conductive paths of the two components of the assembly.
- the heat applied is not sufficient to melt the gold bumps or even to approach the eutectic or peritectic threshold of the gold, but only to the extent necessary to diffuse the gold to form a permanent aluminum/gold bond between the gold bump and the aluminum bond pad.
- the gold from the gold bump diffuses into the aluminum bond pads of the die.
- the method herein disclosed is preferably performed during the burn-in process.
- the temperature can be set or cycled to provide the necessary diffusion energy to form the aluminum/gold bond.
- the chips may be placed in chip carriers which utilize a spring or other biasing member to press the bond pads of the semiconductor die and the gold bumps of the substrate (burn-in die, insert) together.
- the assemblies are then subjected to selected temperatures for a selected period of time, the combination of temperature and time promoting diffusion of the gold into the aluminum bond pads of the die. Contrary to prior art diffusion bonding methods, the diffusion temperature of the present invention is markedly lower, and the diffusion time markedly longer. Of course, were this not the case, the semiconductor die circuitry, if not the die itself, would be damaged and its performance characteristics altered.
- An added advantage of the method of chip-to-substrate interconnection of the present invention is its capability of keeping up with the requirements for ever-increasing numbers of I/O connections, the reduction of process and preparation steps in comparison to C4 bonding and other flip-chip bonding systems known in the art, and the deletion of at least one major step from the fabrication, testing and packaging sequence.
- FIG. 1 is a side view of a semiconductor die contained against a gold-bumped substrate in a burn-in fixture in accordance with the method of the present invention
- FIG. 2 is a partial top perspective view of a gold-bumped substrate showing circuit traces thereon;
- FIG. 3 is a schematic view of the active surface of a high bond pad density semiconductor die suitable for use in accordance with the present invention
- FIG. 4 is a schematic top view of a gold-bumped burn-in substrate suitable for use in accordance with the present invention.
- FIG. 5 is an exploded side view of the semiconductor die, burn-in substrate and burn-in fixture of the embodiment shown in FIG. 1;
- FIG. 6 is an end view of the semiconductor device and burn-in fixture shown in FIG. 1.
- FIG. 1 a side view of a semiconductor die assembly 10 positioned in a burn-in fixture 12 is shown.
- the term “die” as used herein may denote a single die (chip) from a wafer or a plurality of dies, up to an entire wafer if wafer-scale integration is employed for the unit under test.
- the semiconductor die assembly is comprised of a nonelectrically conductive substrate 14 (also commonly termed an insert or burn-in die in the prior art) on which a plurality of gold bumps 16 is formed by means known in the art.
- the bumps 16 are located at the ends of circuit traces 17 extending to the periphery of the substrate 14 for electrical testing during burn-in (see FIG. 2).
- One suitable means of forming gold bumps on substrate 14 is through use of a thermosonic gold wire bonding apparatus as known in the art and commercially available from Kulicke and Soffa Industries of Willow Grove, Pa.
- the bumps may be coined to a desired configuration after deposition, as known in the art. (See U.S. Pat. Nos.
- the preferred compositions of the gold bumps employed in the present invention may comprise 99.99% pure gold (Au) bond wire, as well as Be- or Cu-doped Au, or other Au-based alloys as known in the art.
- Aluminum (Al) wire may also be used to form the bumps, using ultrasonic apparatus as known in the art.
- the substrate 14 is placed in the base 20 of the burn-in fixture 12 with the gold bumps 16 facing upwardly, away from the base 20 .
- the die 18 is aligned with the substrate 14 (the die and substrate planes being mutually parallel and die and substrate electrical contacts being coincident) and a lid or cover 22 is placed on top of the die 18 .
- the die 18 has a plurality of bond pads 13 in the same configuration as the gold bumps 16 on the substrate 14 .
- the bond pads 13 and the gold bumps 16 match.
- one gold bump 15 may be offset from the rest, leaving a space 19 on the substrate surface, and one bond pad 13 ′ offset from the rest of the bond pads 13 , leaving a space 21 corresponding to the space 19 .
- Spaces 19 and 21 may, of course, be eliminated and a bump 16 and bond pad 13 merely offset in alignment.
- other alignment methods known in the art such as marking the components for alignment or creating a die/substrate interconnect pattern which can only be mated in one orientation, may also be employed.
- the bridge clamp 24 of the burn-in fixture 12 comprises an upper plate 26 having a first end 28 and a second end 30 to which perpendicularly extending legs 32 and 34 are attached about their proximal ends 36 and 38 , respectively.
- the legs 32 and 34 have anchors 40 and 42 resiliently disposed at the distal ends 44 and 46 of the legs 32 and 34 , respectively.
- Spaced upwardly from the anchors 40 and 42 are stop members 48 and 50 extending outwardly from legs 32 and 34 .
- the biasing member 54 may be comprised of spring steel and configured as a leaf spring, coil spring or belleville spring, or be formed of some other resilient material known in the art and capable of withstanding the elevated burn-in temperatures, such as a silicone-based elastomers.
- the biasing member 54 should also be designed to apply a selected amount of force to the back side of die 18 when the burn-in fixture 12 is closed, within a broad range capable of providing sufficient force for bonding contact but not excessive, damaging force to the die 18 , the bumps 16 , or the substrate 14 .
- the biasing member 54 as shown is held in position by projections 51 and 53 extending from the underside 52 of the bridge clamp 24 .
- the projections 51 and 53 are angled inwardly toward one another and provide for an abutment of the biasing member 54 .
- Other connection means are possible and contemplated, including a tab or extension of biasing member 54 sliding into slots in bridge clamp 24 .
- the burn-in fixture 12 is designed to apply pressure to the interfaces 56 between the gold bumps 16 and the die 18 transversely to the planes of the die 18 and substrate 14 .
- the anchors 40 and 42 are deflected and inserted through slots 58 and 60 .
- the stop members 48 and 50 prevent the legs 32 and 34 from being inserted too far into the slots 58 and 60 and thus prevent excessive force from being applied by the biasing member 54 on the lid or cover 22 .
- the lid or cover 22 substantially covers the die 18 and is of sufficient strength to resist bending or other deflection (FIGS. 1 and 6), the lid or cover 22 provides uniform pressure across the surface 64 of the die 18 . Moreover, the pressure may be sufficient to ensure that all of the gold bumps 16 are held in contact with the bond pads 13 on the surface 64 of the die 18 .
- FIG. 6 shows the right side end view of the embodiment of FIG. 5.
- the biasing member 54 extends over a substantial portion of the lid or cover 22 so that pressure is evenly applied to the top 57 of the lid or cover 22 . Because of the even pressure applied to the lid or cover 22 and subsequently between the gold bumps 16 and the bond pads 13 , diffusion between all gold bumps 16 and all bond pads 13 under burn-in temperatures can occur substantially simultaneously.
- each gold bump 16 may not initially be in contact with the bond pads 13 of the substrate 14 . While solvable through a coining operation as previous mentioned, such an additional process step (if not performed during bump application) may desirably be omitted. Dimensional variation of the substrate-to-die electrical contacts presented substantial problems with the use of prior art burn-in substrates or inserts employing hard, electroplated contact bumps of nonporous nickel.
- the distance between the die 18 and the substrate 14 will decrease under the force applied by biasing member 54 until those gold bumps 16 not initially in contact with the bond pads 13 do, in fact, contact and diffuse into the bond pads 13 .
- the semiconductor die assembly 10 that is contained in the burn-in fixture 12 is subjected to heat during a burn-in process to elevate the assembly 10 to a predetermined temperature above ambient, typically 125-150° C. as previously noted.
- the burn-in temperature in combination with the relatively slight temperature elevation of the die due to electrical testing during burn-in, is sufficient to cause the gold of the gold bumps 16 to diffuse into the bond pads 13 of the die 18 , but is not high enough to cause the gold in the gold bumps 16 to liquify or to cause damage (beyond the normal purpose of a burn-in to identify defective DUT's) to the DUT.
- the elevated temperature is maintained for a selected period of time, until burn-in is completed and diffusion of the gold into the bond pads 13 has formed a permanent bond.
- certain semiconductor devices have recently been developed for operation at elevated temperatures, such as 180° C. or slightly higher in applications such as aerospace or oil and gas exploration. Burn-in for such chips would naturally be conducted at temperatures higher than 150° C., but still far short of the melting point of gold or most gold alloys. Thus, diffusion bonding according to the present invention would have equal utility for such chips.
- the time required for sufficient diffusion bonding of the gold bumps of elemental gold or a given alloy to the bond pads can readily be determined, both mathematically and empirically, based on the bump metal or alloy employed and the temperature selected during which the die is biased against the adjacent, parallel substrate. The higher the temperature, the faster the diffusion rate. Thus, for a higher temperature, less time is required for the desired diffusion to occur for any given bump metal.
- a plurality of dice may be simultaneously bonded to a like plurality of substrates in a carrier during burn-in; while the term gold “bumps” has been employed, that term may encompass gold balls, cylinders, cuboids, pyramids or cones (including truncated such structures); the term “bond pad” is intended to include and encompass all suitable terminal structures to which a diffusion bond may be made, including both elevated and recessed bond pads as well as flat, concave or convex bond pads and other terminal structures; and bond pads may be formed of gold-compatible materials other than aluminum.
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Abstract
The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached to the connecting surface of the substrate to aluminum-based bond pads on the die to form a permanent die-to-insert connection. The process for diffusing the gold bumps into the bond pads preferably occurs during a burn-in process wherein pressure and heat are applied to the die/substrate assembly without melting the gold bumps until a permanent die-to-insert substrate connection is properly made.
Description
- This application is a divisional of application Ser. No. 09/565,862, filed May 5, 2000, pending, which is a continuation of application Ser. No. 08/736,586, filed Oct. 24, 1996, now U.S. Pat. No. 6,133,638, issued Oct. 17, 2000, which is a divisional of application Ser. No. 08/578,493, filed Dec. 22, 1995, now U.S. Pat. No. 5,686,318, issued Nov. 11, 1997.
- 1. Field of the Invention
- This invention relates generally to die-to-insert interconnections and, more specifically, to a method of forming a permanent die-to-insert electrical connection for a semiconductor die assembly by diffusing gold bumps on the insert into the bond pads of the die using relatively low elevated temperatures and low levels of constant force during the extended time of a burn-in process.
- 2. State of the Art
- Currently, there are three primary chip-level interconnection technologies in practice. They include wirebonding (WB), Tape Automated Bonding (TAB), and Controlled Collapse Chip Connection (C4). The method used to bond the interconnections is dependent upon the number and spacing of input/output (I/O) connections on the chip and the insert (i.e., substrate) as well as permissible cost.
- WB is the most common chip-bonding technology because the required number of chip connections in many products can be accomplished in addition to providing the lowest cost per connection. WB is generally employed to electrically connect chips to the inner ends of the leads of a lead frame, the assembly subsequently being packaged as by transfer molding of a plastic package. For chips requiring more than 257 but less than 600 connections, TAB may be used. TAB employs lead frames of a finer pitch mounted on an insulative carrier tape which is integrated into the chip package. The C4 process, however, is capable of creating up to 16,000 connections per chip (or partial wafer), potentially meeting the demand for any number of connections that the die or partial wafer design dictates.
- When C4 bonding is employed, the entire surface of the chip is normally covered with bond pads for the highest possible I/O count. Solder bumps are deposited on wettable metal terminals (bond pads) on the chip, and a matching footprint of solder-wettable terminals is located on the substrate. Both the bond pads and the terminals must be treated with solder flux. Moreover, the solder bumps must be constrained from completely collapsing (or flowing out onto the substrate bonding site) by using thick-film glass dams, or stops. The tendency for the solder to flow on the chip is contained by a special bonding pad metallurgy that consists of a circular pad of evaporated chromium, copper, and gold. The bond pad metallurgy is then coated by evaporation with, for example, 5Sn-95Pb or 2Sn-98Pb, to a thickness of 100 to 125 μm. Finally, the upside-down chip or die (flip-chip) is aligned to the substrate, and all chip-to-substrate conductive paths are made simultaneously by reflowing the solder.
- The numerous process steps and extensive prebond preparation associated with C4 makes it an expensive bonding method. Moreover, because of the expense added by the C4 process, bumping the chip has been avoided. In the Very Large Scale Integration (VLSI) era, however, the expense has been necessary to obtain the required number of connections.
- As disclosed in U.S. Pat. No. 5,435,734 to Chow, pressure contact interconnect methods are also known in the art. Pressure contacts are not actually bonded but rather form a continuous contact using a material deformation concept such as a metal spring or an elastic retainer. For example, two gold bumps (on chip and substrate) may be joined by a conductive rubber contact embedded in a polyamide carrier. However, this is a mechanically created connection and is, therefore, not as desirable as metallurgical bonding techniques for economic-as well as reliability-associated reasons.
- Furthermore, all of the previously mentioned methods of forming chip-to-substrate interconnections are typically effected after a burn-in operation is performed on the chip to determine if the chip is defective. For burn-in, a chip is typically placed in a multi-chip carrier in resiliently biased or other temporary connection to a burn-in die or substrate (also called an insert) having circuit traces and contacts for electrical testing of the chip. During the burn-in process, the chips are generally subjected to electrical impulses and elevated temperatures (on the order of 125-150° C.) for extended periods of time, usually 24-48 hours, depending upon the chip and the characterization protocol. Low-temperature cycling to as low as −50° C. may also be employed on occasion, particularly for chips being qualified to military specifications. However, this is not common for chips destined for use in commercial applications.
- If not proven defective, the chip is removed from its test fixture after burn-in and is then permanently attached to a substrate by means known in the art, such as those previously mentioned. Alternatively, the chip may be wirebonded to a lead frame or TAB-bonded to a taped lead frame, as known in the art, depending upon the ultimate application for the chip and preferred packaging for that application. In any case, burn-in connections and permanent operational connections are effected in the prior art in two distinct and different operations. While it would be possible to form permanent die-to-insert connections before burn-in, this would increase processing time and cost. It is known to package single die before burn-in, such as with wire- or TAB-bonded lead frame-mounted, plastic-packaged dice (e.g., DIP, ZIP), but such arrangements are not suitable for multi-chip modules (MCM's) such as single in-line memory modules (SIMM's) where failure of a single die will result in scrapping of the module.
- Thus, it would be advantageous to provide an economical method of chip-to-substrate interconnection that is capable of keeping up with the ever-increasing requirements for more I/O connections per chip, does not require all of the preparation and process steps associated with C4 chip interconnections such as application of flux and the use of thick-film glass substrate dams, and removes at least one major step from the manufacturing process through use of a one-step chip-to-substrate electrical connection technique suitable for both burn-in and ultimate first-level packaging of a chip.
- Additional non-C4 ball- or bump-type chip-to-substrate electrical interconnect systems exist in the art, as disclosed in U.S. Pat. Nos. 5,451,274; 5,426,266; 5,369,545; 5,346,857; and 5,341,979. Such systems achieve electrical connections through use of relatively complex and sophisticated apparatus and process methodology, and thus are not suitable for use during chip burn-in in a carrier or other fixture.
- Temporary chip-to-burn-in die or insert connections are also known in the art and exemplified by the disclosures of U.S. Pat. Nos. 5,440,241; 5,397,997; and 5,249,450. None of the foregoing patents, however, discloses a methodology for forming suitably permanent die-to-substrate electrical connections during burn-in.
- It is known in the electronics art to employ diffusion bonding to effect electrical connections between two or more substrates or circuit boards; U.S. Pat. No. 5,276,955 discloses such a process. However, diffusion bonding as known in the art is generally effected at relatively high temperatures just below the eutectic or peritectic temperatures of the bonding alloy, and for relatively short periods of time, such as one or two hours. Thus, state-of-the-art diffusion bonding as known to the inventors has no legitimate application to making chip-to-insert connections.
- According to the invention, a method for forming a permanent chip-to-insert interconnection is herein disclosed. Gold bumps are attached to ends of conductive circuit traces on one side or the other of a nonelectrically conductive substrate, or even the exposed ends of internal conductors, by which electrical testing of a chip during burn-in is effected. As used herein, it should be understood that the term “gold” includes not only elemental gold, but gold with other trace metals and in various alloyed combinations with other metals as known in the semiconductor art. Typically, the die has bond pads on one surface (commonly termed the “front” or “active” surface) formed of aluminum or an aluminum alloy. The bond pads are arranged as a mirror image of the gold bumps located on the surface of the substrate. Thus, when the bond pads are placed on top of the gold bumps, they are in substantial alignment with each other.
- The substrate material is selected such that the coefficient of thermal expansion (CTE) is similar to that of the die or semiconductor chip. This assures that both the substrate and the die expand and contract in a similar manner when subjected to elevated temperatures during a burn-in process so that the bond pads on the die will stay in relatively precise alignment with the gold bumps on the substrate, producing little or no shear force between any bond pad and its corresponding bump. By way of example only, the substrate may be comprised of Mullite, a ceramic material such as 203 aluminum oxide, or any other material known in the art that has a CTE similar to that of the die.
- By applying a force to the die as it is located above and parallel to the plane of the substrate, the bond pads and gold bumps are pressed together. The die/substrate assembly is then heated to effect a bond between the conductive paths of the two components of the assembly. The heat applied, however, is not sufficient to melt the gold bumps or even to approach the eutectic or peritectic threshold of the gold, but only to the extent necessary to diffuse the gold to form a permanent aluminum/gold bond between the gold bump and the aluminum bond pad. Thus, the gold from the gold bump diffuses into the aluminum bond pads of the die.
- The method herein disclosed is preferably performed during the burn-in process. During the heating cycle, the temperature can be set or cycled to provide the necessary diffusion energy to form the aluminum/gold bond. Moreover, the chips may be placed in chip carriers which utilize a spring or other biasing member to press the bond pads of the semiconductor die and the gold bumps of the substrate (burn-in die, insert) together. The assemblies are then subjected to selected temperatures for a selected period of time, the combination of temperature and time promoting diffusion of the gold into the aluminum bond pads of the die. Contrary to prior art diffusion bonding methods, the diffusion temperature of the present invention is markedly lower, and the diffusion time markedly longer. Of course, were this not the case, the semiconductor die circuitry, if not the die itself, would be damaged and its performance characteristics altered.
- Since there is an initial biased electrical contact as soon as the die under test (DUT) is secured against the gold bumps of the substrate in the carrier, electrical testing with elevated potentials as well as thermal testing of the die may commence immediately and continue while the permanent, bump-to-pad diffusion bond is created. Each die that fails during the burn-in process may then simply be discarded at the termination of burn-in along with its attached substrate for recovery of the precious metals. Alternatively, the die may be mechanically removed and a new die attached to the die location on the substrate. It has been found to be, in terms of processing time versus ultimate yield, less expensive to form a permanent chip-to-substrate attachment during burn-in than to perform burn-in followed by a permanent chip attachment to a second substrate, even if some dice have to be pulled as defective or substandard and replaced.
- An added advantage of the method of chip-to-substrate interconnection of the present invention is its capability of keeping up with the requirements for ever-increasing numbers of I/O connections, the reduction of process and preparation steps in comparison to C4 bonding and other flip-chip bonding systems known in the art, and the deletion of at least one major step from the fabrication, testing and packaging sequence.
- The present invention will be more fully understood and appreciated by those of ordinary skill of the art by a review of this specification, taken in conjunction with the appended drawings, wherein:
- FIG. 1 is a side view of a semiconductor die contained against a gold-bumped substrate in a burn-in fixture in accordance with the method of the present invention;
- FIG. 2 is a partial top perspective view of a gold-bumped substrate showing circuit traces thereon;
- FIG. 3 is a schematic view of the active surface of a high bond pad density semiconductor die suitable for use in accordance with the present invention;
- FIG. 4 is a schematic top view of a gold-bumped burn-in substrate suitable for use in accordance with the present invention;
- FIG. 5 is an exploded side view of the semiconductor die, burn-in substrate and burn-in fixture of the embodiment shown in FIG. 1; and
- FIG. 6 is an end view of the semiconductor device and burn-in fixture shown in FIG. 1.
- Referring to FIG. 1, a side view of a
semiconductor die assembly 10 positioned in a burn-infixture 12 is shown. The term “die” as used herein may denote a single die (chip) from a wafer or a plurality of dies, up to an entire wafer if wafer-scale integration is employed for the unit under test. - The semiconductor die assembly is comprised of a nonelectrically conductive substrate14 (also commonly termed an insert or burn-in die in the prior art) on which a plurality of gold bumps 16 is formed by means known in the art. The
bumps 16 are located at the ends of circuit traces 17 extending to the periphery of thesubstrate 14 for electrical testing during burn-in (see FIG. 2). One suitable means of forming gold bumps onsubstrate 14 is through use of a thermosonic gold wire bonding apparatus as known in the art and commercially available from Kulicke and Soffa Industries of Willow Grove, Pa. The bumps may be coined to a desired configuration after deposition, as known in the art. (See U.S. Pat. Nos. 5,397,997 and 5,249,450 for a discussion of various bump-forming techniques.) The preferred compositions of the gold bumps employed in the present invention may comprise 99.99% pure gold (Au) bond wire, as well as Be- or Cu-doped Au, or other Au-based alloys as known in the art. Aluminum (Al) wire may also be used to form the bumps, using ultrasonic apparatus as known in the art. - A semiconductor die18 with active and optionally passive components, as well as circuit traces, vias and other conductive paths as known in the art, is positioned on top of the gold bumps 16. The
substrate 14 is placed in thebase 20 of the burn-infixture 12 with the gold bumps 16 facing upwardly, away from thebase 20. Thedie 18 is aligned with the substrate 14 (the die and substrate planes being mutually parallel and die and substrate electrical contacts being coincident) and a lid or cover 22 is placed on top of thedie 18. - As better seen in FIGS. 3 and 4, the
die 18 has a plurality ofbond pads 13 in the same configuration as the gold bumps 16 on thesubstrate 14. Thus, when thedie 18 is placed on thesubstrate 14, thebond pads 13 and the gold bumps 16 match. Moreover, for alignment purposes, onegold bump 15 may be offset from the rest, leaving aspace 19 on the substrate surface, and onebond pad 13′ offset from the rest of thebond pads 13, leaving aspace 21 corresponding to thespace 19. Thus, correct rotational orientation of the die 18 relative to thesubstrate 14 can be easily ascertained.Spaces bump 16 andbond pad 13 merely offset in alignment. Of course, other alignment methods known in the art, such as marking the components for alignment or creating a die/substrate interconnect pattern which can only be mated in one orientation, may also be employed. - The
bridge clamp 24 of the burn-infixture 12 comprises anupper plate 26 having afirst end 28 and asecond end 30 to which perpendicularly extendinglegs legs anchors legs anchors stop members legs - Attached to the
underside 52 of thebridge clamp 24 is a biasingmember 54. The biasingmember 54 may be comprised of spring steel and configured as a leaf spring, coil spring or belleville spring, or be formed of some other resilient material known in the art and capable of withstanding the elevated burn-in temperatures, such as a silicone-based elastomers. The biasingmember 54 should also be designed to apply a selected amount of force to the back side ofdie 18 when the burn-infixture 12 is closed, within a broad range capable of providing sufficient force for bonding contact but not excessive, damaging force to thedie 18, thebumps 16, or thesubstrate 14. The biasingmember 54 as shown is held in position byprojections underside 52 of thebridge clamp 24. Theprojections member 54. Other connection means are possible and contemplated, including a tab or extension of biasingmember 54 sliding into slots inbridge clamp 24. - The burn-in
fixture 12 is designed to apply pressure to theinterfaces 56 between the gold bumps 16 and the die 18 transversely to the planes of thedie 18 andsubstrate 14. As shown in FIG. 5, theanchors slots stop members legs slots member 54 on the lid orcover 22. - When the
anchors base 20, a predetermined amount of force is applied by the biasingmember 54 to the surface of the lid orcover 22. Because the lid or cover 22 substantially covers thedie 18 and is of sufficient strength to resist bending or other deflection (FIGS. 1 and 6), the lid or cover 22 provides uniform pressure across thesurface 64 of thedie 18. Moreover, the pressure may be sufficient to ensure that all of the gold bumps 16 are held in contact with thebond pads 13 on thesurface 64 of thedie 18. - FIG. 6 shows the right side end view of the embodiment of FIG. 5. As shown, the biasing
member 54 extends over a substantial portion of the lid or cover 22 so that pressure is evenly applied to the top 57 of the lid orcover 22. Because of the even pressure applied to the lid or cover 22 and subsequently between the gold bumps 16 and thebond pads 13, diffusion between allgold bumps 16 and allbond pads 13 under burn-in temperatures can occur substantially simultaneously. - Because of the potential for inherent variation in the height of each
gold bump 16, some gold bumps 16 may not initially be in contact with thebond pads 13 of thesubstrate 14. While solvable through a coining operation as previous mentioned, such an additional process step (if not performed during bump application) may desirably be omitted. Dimensional variation of the substrate-to-die electrical contacts presented substantial problems with the use of prior art burn-in substrates or inserts employing hard, electroplated contact bumps of nonporous nickel. However, as the gold bumps 16 that are in initial contact with thebond pads 13 relax in height slightly as they are compressed during assembly, the distance between the die 18 and thesubstrate 14 will decrease under the force applied by biasingmember 54 until those gold bumps 16 not initially in contact with thebond pads 13 do, in fact, contact and diffuse into thebond pads 13. - The semiconductor die
assembly 10 that is contained in the burn-infixture 12 is subjected to heat during a burn-in process to elevate theassembly 10 to a predetermined temperature above ambient, typically 125-150° C. as previously noted. The burn-in temperature, in combination with the relatively slight temperature elevation of the die due to electrical testing during burn-in, is sufficient to cause the gold of the gold bumps 16 to diffuse into thebond pads 13 of the die 18, but is not high enough to cause the gold in the gold bumps 16 to liquify or to cause damage (beyond the normal purpose of a burn-in to identify defective DUT's) to the DUT. The elevated temperature is maintained for a selected period of time, until burn-in is completed and diffusion of the gold into thebond pads 13 has formed a permanent bond. It should be noted that certain semiconductor devices have recently been developed for operation at elevated temperatures, such as 180° C. or slightly higher in applications such as aerospace or oil and gas exploration. Burn-in for such chips would naturally be conducted at temperatures higher than 150° C., but still far short of the melting point of gold or most gold alloys. Thus, diffusion bonding according to the present invention would have equal utility for such chips. - The time required for sufficient diffusion bonding of the gold bumps of elemental gold or a given alloy to the bond pads can readily be determined, both mathematically and empirically, based on the bump metal or alloy employed and the temperature selected during which the die is biased against the adjacent, parallel substrate. The higher the temperature, the faster the diffusion rate. Thus, for a higher temperature, less time is required for the desired diffusion to occur for any given bump metal.
- While the present invention has been described in terms of certain preferred embodiments, it is not so limited, and those of ordinary skill in the art will readily recognize and appreciate that many additions, deletions and modifications to the embodiments described herein may be made without departing from the scope of the invention as hereinafter claimed. For example, a plurality of dice may be simultaneously bonded to a like plurality of substrates in a carrier during burn-in; while the term gold “bumps” has been employed, that term may encompass gold balls, cylinders, cuboids, pyramids or cones (including truncated such structures); the term “bond pad” is intended to include and encompass all suitable terminal structures to which a diffusion bond may be made, including both elevated and recessed bond pads as well as flat, concave or convex bond pads and other terminal structures; and bond pads may be formed of gold-compatible materials other than aluminum.
Claims (10)
1. A semiconductor die assembly, comprising:
a substrate having a surface;
a plurality of conductive bumps attached to the surface of the substrate, each of the plurality of conductive bumps comprised of a first material; and
a plurality of semiconductor dies having a plurality of bond pads corresponding to the plurality of the conductive bumps, each of the plurality of bond pads comprised of a second material, each of the plurality of bond pads secured to a corresponding conductive bump of the plurality of conductive bumps by a noneutectic, nonalloy-forming, low-temperature diffusion bond, the noneutectic, nonalloy-forming, low-temperature diffusion bond formed at a temperature less than approximately 180° C.
2. The semiconductor die assembly of , wherein the substrate and the plurality of semiconductor dies have coefficients of thermal expansion to maintain the plurality of bond pads and corresponding conductive bumps in alignment.
claim 1
3. The semiconductor die assembly of , wherein the substrate comprises a ceramic material.
claim 1
4. The semiconductor die assembly of , wherein the noneutectic, nonalloy-forming, low-temperature diffusion bond is temperature-induced.
claim 1
5. The semiconductor die assembly of , wherein the noneutectic, nonalloy-forming, low-temperature diffusion bond securing each of the plurality of bond pads to a corresponding conductive bump of the plurality of conductive bumps is formed with the substrate and plurality of semiconductor dies in mutually convergently biased contact through the plurality of conductive bumps and the plurality of bond pads.
claim 4
6. The semiconductor die assembly of , wherein the plurality of semiconductor dies comprises at least a portion of a wafer.
claim 1
7. The semiconductor die assembly of , wherein:
claim 1
the first material of the plurality of conductive bumps comprises gold;
the second material of the plurality of bond pads comprises aluminum; and
the noneutectic, nonalloy-forming, low-temperature diffusion bond of the plurality of bond pads and plurality of conductive bumps comprises essentially diffused gold and diffused aluminum.
8. A semiconductor die assembly, comprising:
a nonconductive substrate including a plurality of circuit traces respectively extending to a plurality of corresponding conductive bumps having a melting temperature and located on a surface of the nonconductive substrate; and
a plurality of semiconductor dies having a plurality of bond pads having a melting temperature and located on a surface thereof in proximity to the nonconductive substrate surface, the plurality of bond pads respectively bonded to corresponding conductive bumps of the plurality of corresponding conductive bumps by a noneutectic, nonalloy-forming, low-temperature diffusion bond, the noneutectic, nonalloy-forming, low-temperature diffusion bond formed at a temperature less than the melting temperature of the plurality of conductive bumps and less than the melting temperature of the plurality of bond pads, and wherein the temperature of the noneutectic, nonalloy-forming, low-temperature diffusion bond is less than approximately 180° C.
9. The semiconductor die assembly of , wherein the plurality of conductive bumps comprises gold, the plurality of bond pads comprises aluminum, and the noneutectic, nonalloy-forming, low-temperature diffusion bond comprises diffused gold and diffused aluminum.
claim 8
10. The semiconductor die assembly of , wherein the plurality of semiconductor dies comprises at least a portion of a wafer.
claim 8
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US09/915,236 US6404063B2 (en) | 1995-12-22 | 2001-07-25 | Die-to-insert permanent connection and method of forming |
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US08/578,493 US5686318A (en) | 1995-12-22 | 1995-12-22 | Method of forming a die-to-insert permanent connection |
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US09/565,862 US6387714B1 (en) | 1995-12-22 | 2000-05-05 | Die-to-insert permanent connection and method of forming |
US09/915,236 US6404063B2 (en) | 1995-12-22 | 2001-07-25 | Die-to-insert permanent connection and method of forming |
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US09/565,862 Division US6387714B1 (en) | 1995-12-22 | 2000-05-05 | Die-to-insert permanent connection and method of forming |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060152111A1 (en) * | 2005-01-10 | 2006-07-13 | Allison Robert C | Micro-electrical-mechanical device and method of making same |
US20180204825A1 (en) * | 2014-07-29 | 2018-07-19 | Huawei Technologies Co., Ltd. | Chip integration module, chip package structure, and chip integration method |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19940564C2 (en) * | 1999-08-26 | 2002-03-21 | Infineon Technologies Ag | Chip card module and this comprehensive chip card, as well as methods for producing the chip card module |
US6767817B2 (en) * | 2002-07-11 | 2004-07-27 | Micron Technology, Inc. | Asymmetric plating |
US7040012B2 (en) * | 2003-03-07 | 2006-05-09 | Intel Corporation | Method of electrically and mechanically connecting electronic devices to one another |
US8723299B2 (en) * | 2010-06-01 | 2014-05-13 | Infineon Technologies Ag | Method and system for forming a thin semiconductor device |
DE102013216709B4 (en) * | 2013-08-22 | 2021-03-25 | Infineon Technologies Ag | SEMICONDUCTOR ARRANGEMENT, METHOD FOR MANUFACTURING A NUMBER OF CHIP ASSEMBLIES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRANGEMENT |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS557022B1 (en) | 1968-05-10 | 1980-02-21 | ||
US3753290A (en) | 1971-09-30 | 1973-08-21 | Tektronix Inc | Electrical connection members for electronic devices and method of making same |
US4293637A (en) | 1977-05-31 | 1981-10-06 | Matsushita Electric Industrial Co., Ltd. | Method of making metal electrode of semiconductor device |
JPS5850021B2 (en) | 1982-07-16 | 1983-11-08 | 富士通株式会社 | Manufacturing method for semiconductor devices |
JPS6086841A (en) | 1983-10-19 | 1985-05-16 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS629642A (en) | 1985-07-05 | 1987-01-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
US4899107A (en) | 1988-09-30 | 1990-02-06 | Micron Technology, Inc. | Discrete die burn-in for nonpackaged die |
US5408190A (en) | 1991-06-04 | 1995-04-18 | Micron Technology, Inc. | Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die |
US4930001A (en) | 1989-03-23 | 1990-05-29 | Hughes Aircraft Company | Alloy bonded indium bumps and methods of processing same |
US5077598A (en) | 1989-11-08 | 1991-12-31 | Hewlett-Packard Company | Strain relief flip-chip integrated circuit assembly with test fixturing |
JP2891432B2 (en) | 1989-12-27 | 1999-05-17 | 田中電子工業株式会社 | Connection method of semiconductor material, connection material used therefor, and semiconductor device |
WO1993004375A1 (en) | 1991-08-23 | 1993-03-04 | Nchip, Inc. | Burn-in technologies for unpackaged integrated circuits |
WO1993007659A1 (en) | 1991-10-09 | 1993-04-15 | Ifax Corporation | Direct integrated circuit interconnection system |
US5440241A (en) | 1992-03-06 | 1995-08-08 | Micron Technology, Inc. | Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby |
US5276955A (en) | 1992-04-14 | 1994-01-11 | Supercomputer Systems Limited Partnership | Multilayer interconnect system for an area array interconnection using solid state diffusion |
US5438224A (en) | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
US5180974A (en) | 1992-05-26 | 1993-01-19 | Micron Technology, Inc. | Semiconductor testing and shipping system |
US5249450A (en) | 1992-06-15 | 1993-10-05 | Micron Technology, Inc. | Probehead for ultrasonic forging |
US5346857A (en) | 1992-09-28 | 1994-09-13 | Motorola, Inc. | Method for forming a flip-chip bond from a gold-tin eutectic |
JP2795788B2 (en) | 1993-02-18 | 1998-09-10 | シャープ株式会社 | Semiconductor chip mounting method |
US5821627A (en) | 1993-03-11 | 1998-10-13 | Kabushiki Kaisha Toshiba | Electronic circuit device |
US5369545A (en) | 1993-06-30 | 1994-11-29 | Intel Corporation | De-coupling capacitor on the top of the silicon die by eutectic flip bonding |
US5341979A (en) | 1993-09-03 | 1994-08-30 | Motorola, Inc. | Method of bonding a semiconductor substrate to a support substrate and structure therefore |
JP2856647B2 (en) | 1993-09-20 | 1999-02-10 | 株式会社東芝 | Socket for semiconductor chip burn-in |
US5591941A (en) | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US5426266A (en) | 1993-11-08 | 1995-06-20 | Planar Systems, Inc. | Die bonding connector and method |
US5451274A (en) | 1994-01-31 | 1995-09-19 | Motorola, Inc. | Reflow of multi-layer metal bumps |
KR100194130B1 (en) | 1994-03-30 | 1999-06-15 | 니시무로 타이죠 | Semiconductor package |
US5468655A (en) | 1994-10-31 | 1995-11-21 | Motorola, Inc. | Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules |
JP3297254B2 (en) | 1995-07-05 | 2002-07-02 | 株式会社東芝 | Semiconductor package and manufacturing method thereof |
US5897341A (en) | 1998-07-02 | 1999-04-27 | Fujitsu Limited | Diffusion bonded interconnect |
-
2001
- 2001-07-25 US US09/915,236 patent/US6404063B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060152111A1 (en) * | 2005-01-10 | 2006-07-13 | Allison Robert C | Micro-electrical-mechanical device and method of making same |
US7098576B2 (en) * | 2005-01-10 | 2006-08-29 | Raytheon Company | Micro-electrical-mechanical device and method of making same |
US20180204825A1 (en) * | 2014-07-29 | 2018-07-19 | Huawei Technologies Co., Ltd. | Chip integration module, chip package structure, and chip integration method |
US11462520B2 (en) * | 2014-07-29 | 2022-10-04 | Huawei Technologies Co., Ltd. | Chip integration module, chip package structure, and chip integration method |
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