New! View global litigation for patent families

US20010043648A1 - Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method - Google Patents

Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method Download PDF

Info

Publication number
US20010043648A1
US20010043648A1 US08991715 US99171597A US2001043648A1 US 20010043648 A1 US20010043648 A1 US 20010043648A1 US 08991715 US08991715 US 08991715 US 99171597 A US99171597 A US 99171597A US 2001043648 A1 US2001043648 A1 US 2001043648A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
data
serial
parallel
test
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US08991715
Other versions
US6341142B2 (en )
Inventor
Francois Ducaroir
Karl S. Nakamura
Michael O. Jenkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies General IP (Singapore) Pte Ltd
Original Assignee
LSI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/46Monitoring; Testing

Abstract

A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    This invention relates to digital data communication circuits, and more particularly to the operational verification of serial data communication circuits.
  • [0003]
    2. Description of the Relevant Art
  • [0004]
    Electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). Simultaneous transmission of multiple signals is accommodated by several wires routed in parallel (i.e., buses). Most computer systems have a modular architecture centered around a bus which serves as a shared communication link between system components. The two major advantages of shared buses over direct communication links between system components are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.
  • [0005]
    Due to technological advances, the signal processing capabilities of more modern electronic devices (e.g., microprocessors) are outstripping the signal transfer capabilities of conventional parallel buses. To their detriment, parallel buses have physical limitations which place an upper limit on the rate at which information can be transferred over the bus. For example, the electrical characteristics and loading of each wire of a bus may vary, causing signals transmitted simultaneously upon the bus to be received at different times. Bus timing must take into consideration worst case delays, resulting in reduced data transfer rates of systems employing parallel buses.
  • [0006]
    A serial data path, on the other hand, is a direct communication link between a single transmitter and a single receiver. Such a serial data path typically includes a dedicated transmission medium connected between the transmitter and receiver. The transmission medium may be, for example, a differentially-driven pair of wires or a fiber-optic cable. In cases where the transmission medium is a pair of wires, the communication link (i.e., channel) has a defined electrical loading and is typically optimized for minimum signal delay. As a result, the rate at which electrical signals can be transferred over such a serial data path exceeds the data transfer rate of a common shared parallel bus.
  • [0007]
    Serial data transmitter/receiver devices (i.e., transceivers) offering digital signal transmission rates exceeding 1 gigabit per second are now commercially available. The testing of such transceivers at their normal operating speeds, however, presents many technical challenges. Consider a serial data transceiver including a transmitter and a receiver. The transmitter receives parallel data at an input port, converts the parallel data to a serial data stream, and provides the serial data stream at an output port. The receiver receives a serial data stream at an input port, converts the serial data stream to parallel data, and provides the parallel data at an output port. A conventional method of operationally testing such a transceiver is to connect the transmitter output port to the receiver input port in a “loopback” fashion, provide parallel input test data to the transmitter input port, receive parallel output test data from the output port of the receiver, and compare the parallel output test data to the parallel input test data. A match between the parallel output test data and the parallel input test data verifies proper operation of the transceiver.
  • [0008]
    When the transceiver is installed within, for example, a computer system, access to the parallel data transfer terminals (i.e., the transmitter input port and the receiver output port) is typically limited to other computer system components coupled to the transceiver data transfer terminals. In order to gain access to the parallel data transfer terminals for testing, it may be necessary to disassemble the system to access the transceiver, to remove the transceiver from the system, and to mount the transceiver within a special test fixture which connects the transmitter output port to the receiver input port. Following testing, the transceiver must be reinstalled within the system and the system reassembled.
  • [0009]
    In contrast, the serial data transfer terminals of the transceiver (i.e., the receiver input port and the transmitter output port) are by design easily accessible and available for testing without system disassembly. In addition, serial data testing requires fewer wires and physical connections than parallel data testing. Testing problems are often the result of faulty wires and physical connections.
  • [0010]
    It would be beneficial to have a serial data transceiver which includes elements which facilitate functional testing requiring access to only the serial data transfer terminals of the transceiver (i.e., only the receiver input port and the transmitter output port). Such a serial data transceiver and accompanying test method would eliminate the need to disassemble a computer system including the transceiver in order to test the transceiver. In addition, the fewer wires and physical connections involved in serial testing of the transceiver would reduce problems associated with faulty wires and physical connections. In addition to transceiver testing and characterization, such testing capability is also beneficial for system debugging. For example, assume several computers are connected to a shared communication medium forming a computer network having a loop topology. Each transceiver operating in “loopback” mode immediately retransmits incoming serial data, behaving like a wire. Such action allows testing of the network independent of the transceivers.
  • SUMMARY OF THE INVENTION
  • [0011]
    A serial data transceiver is presented having elements which facilitate functional testing using only the serial data transfer terminals of the transceiver. An associated test apparatus and method employs these elements. The present transceiver architecture solves a test access problem. Testing of the serial data transceiver mounted within a computer system does not require disassembly of the computer system and removal of the transceiver from the system. The serial data transfer terminals are typically easily accessible and available for testing. In addition, fewer wires and physical connections are required for serial data testing than for parallel data testing. The use of fewer wires and physical connections reduces problems associated with faulty wires and physical connections.
  • [0012]
    The serial data transceiver includes a transmitter and a receiver formed upon a monolithic semiconductor substrate. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. The transmitter and receiver are also coupled to receive a test signal. When the test signal is asserted, parallel data is routed from the output of the receiver to the input of the transmitter. Functional testing of the serial data transceiver may thus be accomplished with access to only the serial data ports of the transceiver.
  • [0013]
    In order to facilitate the routing the output of the receiver to the input of the transmitter, one embodiment of the serial data transceiver includes two routers. A first router within the transmitter routes parallel input data to the transmitter. A second router within the receiver routes parallel output data and the recovered clock signal produced by the receiver. The first router is coupled to the second router, and both routers are configured to receive a ‘test’ signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver during testing.
  • [0014]
    In one embodiment, the transceiver includes a ‘transmit data’ input port for receiving parallel input data to be transmitted, a serial data output port, a serial data input port, a ‘receive data’ output port for providing parallel output data produced by the receiver, and a recovered clock terminal. The transmitter is coupled between the transmit data input port and the serial data output port. The transmitter receives the parallel input data, converts the parallel input data to a serial data stream, and transmits the serial data stream at the serial data output port. The transmitter includes a serializer for converting the parallel input data to the serial data stream. The first router is coupled between the transmit data input port and the serializer, and routes parallel input data and a recovered clock signal to the serializer dependent upon the test signal. The receiver is coupled between the serial data input port and the receive data output port. The receiver receives a serial data stream from the serial data input port, converts the serial data stream to parallel output data, and provides the parallel output data.
  • [0015]
    The receiver includes a deserializer for converting the serial data stream into the parallel output data. The deserializer also recovers a clock signal (i.e., the recovered clock signal) from the serial data stream. The second router is coupled between the deserializer and the receive data output port. The second router provides the recovered clock signal to the recovered clock terminal. The second router also routes the parallel output data produced by the deserializer dependent upon the test signal. When the test signal is deasserted: (i) the first router routes parallel input data from the transmit data input port to the serializer, and (ii) the second router routes parallel output data from the deserializer to the receive data output port. The serializer uses the reference clock signal to serialize the parallel input data. When the test signal is asserted: (i) the second router routes parallel output data and the recovered clock signal produced by the deserializer to the first router, and (ii) the first router routes the parallel output data and the recovered clock signal received from the second router to the serializer. The serializer uses the recovered clock signal to serialize the parallel output data produced by the deserializer.
  • [0016]
    The present method for testing the serial data transceiver described above includes asserting the test signal, providing serial input test data to the serial data input port, receiving serial output test data from the serial data output port, and comparing the serial output test data to the serial input test data. A test unit including a serial test generator and a serial data comparator may be coupled to the transceiver during testing and used to generate the serial input test data and to perform the comparison operation. A match between the serial output test data and the serial input test data (i.e., a one-to-one correspondence between the logic values of the corresponding bit positions of the serial output test data and the serial input test data) verifies proper operation of the serial data transceiver.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0017]
    Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
  • [0018]
    [0018]FIG. 1 is a block diagram of one embodiment of a serial data transceiver of the present invention and a related test unit, wherein the serial data transceiver includes a transmitter for transmitting serial data, a receiver for receiving serial data, and a mechanism for routing the output of the receiver to the input of the transmitter during testing such that received serial data is retransmitted by the transmitter.
  • [0019]
    While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0020]
    Referring now to the drawings, FIG. 1 is a block diagram of one embodiment of a serial data transceiver 10 of the present invention. Transceiver 10 includes a transmitter 12 and a receiver 14 formed upon a single monolithic semiconductor substrate 14. Transceiver 10 also includes a transmit data input port, a pair of polarized transmitter output terminals, a pair of polarized receiver input terminals, a receive data output port, a ‘reference clock’ terminal, a test terminal, and a ‘recovered clock’ terminal. During normal operation, transmitter 12 receives parallel data from the transmit data input port, converts the parallel data to a serial data stream (i.e., serializes the parallel data), and transmits the serial data stream differentially between the pair of polarized transmitter output terminals. The operations of transmitter 12 are synchronized by a ‘reference clock’ signal coupled to the ‘reference clock’ terminal. During normal operation, receiver 14 receives a serial data stream from between the pair of polarized receiver input terminals, converts the serial data stream to parallel data (i.e., deserializes the serial data stream), and provides the parallel data at the receive data output port. The operations of receiver 14 are synchronized by a clock signal recovered from the serial data stream (i.e., a ‘recovered clock’ signal).
  • [0021]
    Transmitter 12 includes a router 16, a serializer 18, and an output buffer 20. Router 16 receives parallel data from the transmit data input port, parallel data produced by receiver 14, and a test signal coupled to the test terminal. Router 16 provides either the parallel data from the transmit data input port or the parallel data produced by receiver 14 to serializer 18 dependent upon the test signal. When the test signal is deasserted, router 16 provides the parallel data from the transmit data input port to serializer 18. Serializer 18 uses the reference clock signal to serialize the parallel data provided by router 16 and provides the resulting serial data stream to output buffer 20. Output buffer 20 differentially drives the pair of polarized transmitter output terminals with complementary voltage values representing the logic values of the serial data stream. When the test signal is asserted, router 16 provides the parallel data and the recovered clock signal produced by receiver 14 to serializer 18. Serializer 18 uses the recovered clock signal to serialize the parallel data provided by router 16 and provides the resulting serial data stream to output buffer 20.
  • [0022]
    Receiver 14 includes an input buffer 22, a deserializer 24, and a router 28. Input buffer 22 receives a differentially-driven serial data stream from between the pair of polarized receiver input terminals and provides the corresponding logic values of the serial data stream to deserializer 24. Deserializer 24 recovers a transmit clock signal used to transmit the serial data from the serial data stream (i.e., the recovered clock signal), samples the serial data stream using the transmit clock signal stream in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data and recovered clock signal to router 28. Router 28 receives the parallel data and recovered clock signal from deserializer 24 as well as the test signal. Router 28 provides the recovered clock signal to the recovered clock terminal. Router 28 also provides parallel data to either the receive data output port or to router 16 of transmitter 12 dependent upon the test signal. When the test signal is deasserted, router 28 provides the parallel data to the receive data output port. When the test signal is asserted, router 28 provides both the parallel data and the recovered clock signal to router 16 of transmitter 12.
  • [0023]
    Router 16 and router 28 may include, for example, arrays of switches operating in parallel. During normal operation, the test signal is deasserted, router 16 provides parallel data from the transmit data input port to serializer 18, and router 28 provides parallel data from deserializer 24 to the receive data output port. During testing, transmitter 12 uses the recovered clock signal produced by receiver 14 to serialize the parallel output data produced by receiver 14. Thus during testing, the operations of transmitter 12 and receiver 14 are synchronized by the recovered clock signal.
  • [0024]
    [0024]FIG. 1 also shows a test unit 30 coupled to transceiver 10 during testing to verify proper operation of transceiver 10. Test unit 30 includes a serial data generator 32 and a serial data comparator 34. During testing, the test signal is asserted. Serial data generator 32 generates a serial test data stream and differentially drives the polarized pair of receiver input terminals of transceiver 10 with complementary voltage values representing the logic values of the serial test data stream. Input buffer 22 of receiver 14 receives the voltage values and provides the corresponding logic values to deserializer 24. Deserializer 24 produces the recovered clock signal, uses the recovered clock signal to deserialize the serial test data stream, and provides both the recovered clock signal and the resulting parallel test data to router 28. Router 28 receives the recovered clock signal and the parallel test data from deserializer 24, provides the recovered clock signal to the recovered clock terminal, and also provides the recovered clock signal and the parallel test data to router 16 of transmitter 12. Router 16 provides the recovered clock signal and the parallel test data to serializer 18. Serializer 18 uses the recovered clock signal to serialize the parallel test data provided by router 16, and provides the resulting serial test data stream to output buffer 20. Output buffer 20 differentially drives the pair of polarized transmitter output terminals with complementary voltage values representing the logic values of the serial test data stream. Serial data comparator 34 receives the voltage values produced by transmitter 12 and converts the voltage values to the corresponding serial output test data. Serial data comparator 34 then compares the serial output test data to the serial input test data provided by serial data generator 32. A match between the serial output test data and the serial input test data (i.e., a one-to-one correspondence between the logic values of the corresponding bit positions of the serial output test data and the serial input test data) verifies proper operation of transceiver 10.
  • [0025]
    It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention is believed to be a serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test apparatus and method. Furthermore, it is also to be understood that the form of the invention shown and described is to be taken as exemplary, presently preferred embodiments. Various modifications and changes may be made without departing from the spirit and scope of the invention as set forth in the claims. It is intended that the following claims be interpreted to embrace all such modifications and changes.

Claims (13)

    What is claimed is:
  1. 1. A serial data transceiver formed upon a monolithic semiconductor substrate, comprising:
    a receiver adapted to operably receive a first serial data stream and convert the first serial data stream into parallel data; and
    a transmitter connected to receive the parallel data during a time in which a test signal is asserted into the transceiver, whereupon the parallel data is converted into a second serial data stream.
  2. 2. The serial data transceiver as recited in
    claim 1
    , wherein the first and second serial data streams are presented at separate first and second serial connectors, respectively, of the transceiver.
  3. 3. The serial data transceiver as recited in
    claim 2
    , wherein the first and second serial connector are each singular connectors.
  4. 4. The serial data transceiver as recited in
    claim 2
    , wherein the first serial connector is adapted to receive a first serial test signal within the first serial data stream, and wherein the second serial connector is adapted to receive a test comparator unit for comparing the second serial data stream to the first serial test signal.
  5. 5. The serial data transceiver as recited in
    claim 1
    , wherein the transmitter comprises a first router for routing parallel input data to the transmitter.
  6. 6. The serial data transceiver as recited in
    claim 5
    , wherein the receiver comprises a second router for routing parallel output data produced by the receiver.
  7. 7. The serial data transceiver as recited in
    claim 6
    , wherein the first router is coupled to the second router, and wherein the first and second routers are configured to receive the test signal, and wherein when the test signal is asserted: (i) the second router routes the parallel output data produced by the receiver to the first router, and (ii) the first router routes the parallel output data produced by the receiver to the transmitter.
  8. 8. A system for testing a transceiver, comprising:
    a test unit;
    a serial data input port adapted to receive a serialized input test signal from the test unit;
    a serial data output port adapted to present a serialized output test signal to the test unit;
    a mechanism embodied within the transceiver for converting and routing, in parallel fashion, the serialized input test signal to the serialized output test signal output; and
    a comparator within the test unit for comparing the serialized input test signal to the serialized output test signal to determine the accuracy by which the mechanism converts the serial input test signal to the serialized output test signal.
  9. 9. The system as recited in
    claim 8
    , wherein said mechanism comprises at least one router operably coupled between the serial data input port and the serial data output port.
  10. 10. The system as recited in
    claim 9
    , wherein the router couples parallel signals converted from respective said serialized input test signal and said serialized output test signal.
  11. 11. The system as recited in
    claim 8
    , wherein said mechanism comprises a serializer and a deserializer coupled in series between the serial data input port and the serial data output port.
  12. 12. A serial data transceiver formed upon a monolithic semiconductor substrate, comprising:
    a transmit data input port for receiving parallel input data;
    a serial data output port;
    a serial data input port;
    a receive data output port for providing parallel output data;
    a transmitter coupled between the transmit data input port and the serial data output port, wherein the transmitter is configured to receive parallel input data, to convert the parallel input data to a serial data stream, and to transmit the serial data stream at the serial data output port, wherein the transmitter comprises:
    a serializer for converting the parallel input data to the serial data stream; and
    a first router coupled between the transmit data input port and the serializer for routing parallel input data to the serializer;
    a receiver coupled between the serial data input port and the receive data output port, wherein the receiver is configured to receive a serial data stream from the serial data input port, to convert the serial data stream to parallel output data, and to provide the parallel output data, wherein the receiver comprises:
    a deserializer for converting the serial data stream to the parallel output data; and
    a second router coupled between the deserializer and the receive data output port for routing the parallel output data produced by the deserializer;
    wherein the first router is coupled to the second router, and wherein the first and second routers are coupled to receive a test signal, and wherein when the test signal is deasserted:
    the first router routes parallel input data from the transmit data input port to the serializer; and
    the second router routes parallel output data from the deserializer to the receive data output port;
    and wherein when the test signal is asserted:
    the second router routes parallel output data from the deserializer to the first router; and
    the first router routes the parallel output data from the second router to the serializer.
  13. 13. A method for testing a serial data transceiver, comprising:
    providing a serial data transceiver, comprising:
    a serial data output port;
    a serial data input port;
    a transmitter coupled to the serial data output port, wherein the transmitter is configured to receive parallel data, to convert the parallel data to a serial data stream, and to transmit the serial data stream at the serial data output port, wherein the transmitter comprises a first router for routing parallel data to the transmitter;
    a receiver coupled to the serial data input port, wherein the receiver is configured to receive a serial data stream, to convert the serial data stream to parallel data, and to provide the parallel data, wherein the receiver comprises a second router for routing the parallel data produced by the receiver;
    wherein the first router is coupled to the second router, and wherein the first and second routers are coupled to receive a test signal, and wherein when the test signal is asserted: (i) the second router routes parallel data produced by the receiver to the first router; and (ii) the first router routes the parallel data produced by the receiver to the transmitter;
    asserting the test signal;
    providing serial input test data to the serial data input port;
    receiving serial output test data from the serial data output port; and
    comparing the serial output test data to the serial input test data.
US08991715 1997-12-16 1997-12-16 Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method Expired - Lifetime US6341142B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08991715 US6341142B2 (en) 1997-12-16 1997-12-16 Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08991715 US6341142B2 (en) 1997-12-16 1997-12-16 Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

Publications (2)

Publication Number Publication Date
US20010043648A1 true true US20010043648A1 (en) 2001-11-22
US6341142B2 US6341142B2 (en) 2002-01-22

Family

ID=25537487

Family Applications (1)

Application Number Title Priority Date Filing Date
US08991715 Expired - Lifetime US6341142B2 (en) 1997-12-16 1997-12-16 Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

Country Status (1)

Country Link
US (1) US6341142B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020112099A1 (en) * 2001-02-13 2002-08-15 Collier Josh D. Method and apparatus for deskewing multiple incoming signals
US20030031133A1 (en) * 2001-08-10 2003-02-13 Momtaz Afshin D. Line loop back for very high speed application
US20030084385A1 (en) * 2001-02-02 2003-05-01 Jared Zerbe Method and apparatus for evaluating and optimizing a signaling system
EP1406408A1 (en) * 2002-10-02 2004-04-07 Broadcom Corporation On-chip standalone self-test system and method
US20070064510A1 (en) * 2001-02-02 2007-03-22 Rambus Inc. Method And Apparatus For Evaluating And Optimizing A Signaling System
US20090161740A1 (en) * 2007-12-20 2009-06-25 Holger Wenske Transceiver with switch circuit for routing data from receiver to transmitter
US20100261431A1 (en) * 2009-04-08 2010-10-14 Litepoint Corporation Method and apparatus for testing multiple data signal transceivers substantially simultaneously with common transceiver tester
US7885320B1 (en) * 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
US20130339789A1 (en) * 2012-06-18 2013-12-19 Sankaran M. Menon Method and apparatus for output of high-bandwidth debug data/traces in ics and socs using embedded high speed debug
US20140163769A1 (en) * 2012-12-11 2014-06-12 Electro-Motive Diesel, Inc. System and method for communicating data in a consist
US9632895B2 (en) 2012-06-18 2017-04-25 Intel Corporation Apparatus, system and method for a common unified debug architecture for integrated circuits and SoCs

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19857154C1 (en) * 1998-12-11 2000-03-16 Daimler Chrysler Ag Method for transferring inverted data over one or several data lines transmits original binary data to a unit like a register selected through a binary base address.
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7376767B1 (en) * 2002-01-04 2008-05-20 Xilinx, Inc. Distributed buffering system having programmable interconnecting logic and applications thereof
US7047457B1 (en) * 2003-09-11 2006-05-16 Xilinx, Inc. Testing of a multi-gigabit transceiver
US7203460B2 (en) * 2003-10-10 2007-04-10 Texas Instruments Incorporated Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
GB2413746B (en) * 2004-05-01 2007-02-14 Abb Offshore Systems Ltd Modem
US7656325B1 (en) * 2008-07-09 2010-02-02 Lsi Corporation Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1504897A (en) 1974-08-09 1978-03-22 Ericsson L M Pty Ltd Method for through connection check in digital data systems
US4308472A (en) 1979-12-03 1981-12-29 Gte Automatic Electric Labs Inc. Clock check circuit
FR2486335B1 (en) 1980-07-02 1988-03-11 Telecommunications Sa Installation remote locate step-by-step amplification circuits intermediate connection of a mic
US4419633A (en) 1980-12-29 1983-12-06 Rockwell International Corporation Phase lock loop
JPS6236413B2 (en) 1981-09-07 1987-08-06 Hitachi Ltd
EP0110933B1 (en) 1982-05-26 1986-07-16 Telefonaktiebolaget L M Ericsson Apparatus for through-connection testing in a digital telecommunication network
GB2127653B (en) 1982-09-15 1986-10-15 Standard Telephones Cables Ltd Supervision of digital transmission systems
US4575864A (en) 1983-03-07 1986-03-11 E-Systems, Inc. Digital programmable packet switch synchronizer
US4573017A (en) 1984-01-03 1986-02-25 Motorola, Inc. Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop
US4613979A (en) 1984-05-03 1986-09-23 Zenith Electronics Corporation Continuous, automatic reset of synchronous data receiver upon detection of loss of sync
GB8522998D0 (en) 1985-09-18 1985-10-23 Plessey Co Plc Phase comparator lock detect circuit
JP2718664B2 (en) 1986-05-23 1998-02-25 株式会社日立画像情報システム Phase synchronous detection circuit
US4988901A (en) 1988-04-15 1991-01-29 Sharp Kabushiki Kaisha Pulse detecting device for detecting and outputting a pulse signal related to the slower frequency input pulse
DE3815531C2 (en) 1988-05-06 1990-08-16 Heidelberger Druckmaschinen Ag, 6900 Heidelberg, De
FI82164C (en) 1988-06-30 1991-01-10 Nokia Data Systems Coupling unit.
FR2651396B1 (en) 1989-08-31 1991-12-20 Abiven Jacques loopback devices for optical transmission systems has PTT.
US5180993A (en) 1990-01-15 1993-01-19 Telefonaktiebolaget L M Ericsson Method and arrangement for frequency synthesis
JP2698685B2 (en) 1990-03-27 1998-01-19 株式会社東芝 Computer system remote control device
DE4010798C2 (en) * 1990-04-04 1993-03-25 Bodenseewerk Geraetetechnik Gmbh, 7770 Ueberlingen, De
FR2667748A1 (en) 1990-10-09 1992-04-10 Trt Telecom Radio Electr System for transmitting information according to a time division multiplex having a variable structure.
US5159279A (en) 1990-11-27 1992-10-27 Dsc Communications Corporation Apparatus and method for detecting out-of-lock condition in a phase lock loop
US5200979A (en) 1991-06-06 1993-04-06 Northern Telecom Limited High speed telecommunication system using a novel line code
US5126690A (en) 1991-08-08 1992-06-30 International Business Machines Corporation Phase locked loop lock detector including loss of lock and gain of lock detectors
US5343461A (en) * 1991-08-27 1994-08-30 Ameritech Services, Inc. Full duplex digital transmission facility loop-back test, diagnostics and maintenance system
FR2682237B1 (en) 1991-10-04 1993-11-19 Alcatel Cit Device for hooking a loop detection phase-locked.
KR950011302B1 (en) 1992-03-11 1995-09-30 김광호 Circuit for detecting data accord
US5301207A (en) 1992-04-03 1994-04-05 Integrated Network Corporation Test apparatus and process for digital data service system
GB2268645B (en) 1992-07-02 1996-08-21 Motorola Inc A lock detection circuit for a phase lock loop
US5550802A (en) 1992-11-02 1996-08-27 National Semiconductor Corporation Data communication network with management port for isochronous switch
JP3286418B2 (en) 1993-09-20 2002-05-27 富士通株式会社 Subscriber line test equipment
US5638518A (en) * 1994-10-24 1997-06-10 Lsi Logic Corporation Node loop core for implementing transmission protocol in fibre channel
US5787114A (en) 1996-01-17 1998-07-28 Lsi Logic Corporation Loop-back test system and method
US5956370A (en) * 1996-01-17 1999-09-21 Lsi Logic Corporation Wrap-back test system and method
US5790563A (en) * 1996-02-05 1998-08-04 Lsi Logic Corp. Self test of core with unpredictable latency

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137048B2 (en) * 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US8756469B2 (en) 2001-02-02 2014-06-17 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US20030084385A1 (en) * 2001-02-02 2003-05-01 Jared Zerbe Method and apparatus for evaluating and optimizing a signaling system
US20030208707A9 (en) * 2001-02-02 2003-11-06 Jared Zerbe Method and apparatus for evaluating and optimizing a signaling system
US9356743B2 (en) 2001-02-02 2016-05-31 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US8069378B2 (en) * 2001-02-02 2011-11-29 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7360127B2 (en) 2001-02-02 2008-04-15 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US20070064510A1 (en) * 2001-02-02 2007-03-22 Rambus Inc. Method And Apparatus For Evaluating And Optimizing A Signaling System
US20060236183A1 (en) * 2001-02-02 2006-10-19 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US8812918B2 (en) 2001-02-02 2014-08-19 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US8812919B2 (en) 2001-02-02 2014-08-19 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6766464B2 (en) * 2001-02-13 2004-07-20 Sun Microsystems, Inc. Method and apparatus for deskewing multiple incoming signals
US20020112099A1 (en) * 2001-02-13 2002-08-15 Collier Josh D. Method and apparatus for deskewing multiple incoming signals
US7099278B2 (en) * 2001-08-10 2006-08-29 Broadcom Corporation Line loop back for very high speed application
US20030031133A1 (en) * 2001-08-10 2003-02-13 Momtaz Afshin D. Line loop back for very high speed application
EP1406408A1 (en) * 2002-10-02 2004-04-07 Broadcom Corporation On-chip standalone self-test system and method
US20040068683A1 (en) * 2002-10-02 2004-04-08 Hoang Tuan M. On-chip standalone self-test system and method
US7111208B2 (en) 2002-10-02 2006-09-19 Broadcom Corporation On-chip standalone self-test system and method
US7885320B1 (en) * 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
US8098766B2 (en) * 2007-12-20 2012-01-17 Infineon Technologies Ag Transceiver with switch circuit for routing data from receiver to transmitter
DE102008062010B4 (en) * 2007-12-20 2014-10-16 Infineon Technologies Ag Transmitter-receiver coupling circuit for passing data from the receiver to the transmitter
US20090161740A1 (en) * 2007-12-20 2009-06-25 Holger Wenske Transceiver with switch circuit for routing data from receiver to transmitter
US8170490B2 (en) 2009-04-08 2012-05-01 Litepoint Corporation Method and apparatus for testing multiple data signal transceivers substantially simultaneously with common transceiver tester
US20100261431A1 (en) * 2009-04-08 2010-10-14 Litepoint Corporation Method and apparatus for testing multiple data signal transceivers substantially simultaneously with common transceiver tester
WO2010117698A3 (en) * 2009-04-08 2011-01-13 Litepoint Corporation Method and apparatus for testing multiple data signal transceivers substantially simultaneously with common transceiver tester
WO2010117698A2 (en) * 2009-04-08 2010-10-14 Litepoint Corporation Method and apparatus for testing multiple data signal transceivers substantially simultaneously with common transceiver tester
US9043649B2 (en) * 2012-06-18 2015-05-26 Intel Corporation Method and apparatus for output of high-bandwidth debug data/traces in ICS and SoCs using embedded high speed debug
US20130339789A1 (en) * 2012-06-18 2013-12-19 Sankaran M. Menon Method and apparatus for output of high-bandwidth debug data/traces in ics and socs using embedded high speed debug
US9632895B2 (en) 2012-06-18 2017-04-25 Intel Corporation Apparatus, system and method for a common unified debug architecture for integrated circuits and SoCs
US20140163769A1 (en) * 2012-12-11 2014-06-12 Electro-Motive Diesel, Inc. System and method for communicating data in a consist
US9043044B2 (en) * 2012-12-11 2015-05-26 Electro-Motive Diesel, Inc. System and method for communicating data in a consist

Also Published As

Publication number Publication date Type
US6341142B2 (en) 2002-01-22 grant

Similar Documents

Publication Publication Date Title
US5726991A (en) Integral bit error rate test system for serial data communication links
US5956370A (en) Wrap-back test system and method
US6185643B1 (en) Method and apparatus for extending the range between a computer and computer peripherals
US6108726A (en) Reducing the pin count within a switching element through the use of a multiplexer
US6625675B2 (en) Processor for determining physical lane skew order
US5513377A (en) Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
US6693901B1 (en) Backplane configuration without common switch fabric
US5422880A (en) Broadband switching fabric in a communication controller
US5268903A (en) Multichannel telephonic switching network with different signaling formats and cross connect/PBX treatment selectable for each channel
US5043976A (en) Loop-back device for half-duplex optical transmission system
US6215816B1 (en) Physical layer interface device
US4683563A (en) Data communication network
US5787114A (en) Loop-back test system and method
US5832047A (en) Self timed interface
US5062104A (en) Digital service unit for connecting data processing equipment to a telephone system based computer network
US5406147A (en) Propagation speedup by use of complementary resolver outputs in a system bus receiver
US20050141661A1 (en) Lane to lane deskewing via non-data symbol processing for a serial point to point link
US6418537B1 (en) Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL
US6331999B1 (en) Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream
US6208667B1 (en) Constant phase crossbar switch
US4481626A (en) Transceiver multiplexor
US20020138224A1 (en) Real-time channel calibration method and arrangement
US6920576B2 (en) Parallel data communication having multiple sync codes
US5909427A (en) Redundant switch system and method of operation
US5522088A (en) Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus

Legal Events

Date Code Title Description
AS Assignment

Owner name: LSI LOGIC CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DUCAROIR, FRANCOIS;NAKAMURA, KARL S.;JENKINS, MICHAEL O.;REEL/FRAME:008929/0700;SIGNING DATES FROM 19971209 TO 19971212

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG

Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031

Effective date: 20140506

AS Assignment

Owner name: LSI CORPORATION, CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270

Effective date: 20070406

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388

Effective date: 20140814

AS Assignment

Owner name: LSI CORPORATION, CALIFORNIA

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039

Effective date: 20160201

Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039

Effective date: 20160201

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001

Effective date: 20160201

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001

Effective date: 20170119