KR20000041921A - Lan interface apparatus of an internet matching apparatus - Google Patents

Abstract

PURPOSE: A LAN interface apparatus is provided to perform a service offer rapidly by making data accessed from a master board be transferred directly into a corresponding board. CONSTITUTION: A LAN interface apparatus comprises a first and second ports(111,112), a first and second transceiver parts(113,114), a first and second modulation/demodulation parts(115,116), a link control and switch part(117) and an ethernet controller(118). Each of the first and second transceiver parts(113,114) processes data received from a system management unit or a LAN matching unit into a predetermined state proper for a system, and processes data transmitted from an internet matching unit into a predetermined state proper to a LAN communication. The first and second transceiver parts(113,114) have obstacle detecting parts(113a,114a) each of which detects whether a link obstacle is generated between connected matching units and outputs a signal corresponding to the detection result. Each of the first and second modulation/demodulation parts(115,116) decodes data received from a corresponding transceiver part(113/114) to demodulate the decoded result into a format used in the internet matching unit. Each of the first and second modulation/demodulation parts(115,116) codes data transmitted from the internet matching unit to a system management unit and the LAN matching unit. The link control and switch part(117) controls a data link transmitted and received between the internet matching unit and the system management unit or the LAN matching unit. The link control and switch part(117) switches a link so that, when one of the links is hindered, data is transferred through the other link.

Description

LAN interface device of internet matching device

The present invention relates to a LAN (Local Area Network) interface device that is connected to the Ethernet link in the Internet matching device, more specifically, a plurality of Ethernet on the master board in the Internet matching device using the VME bus The present invention relates to a LAN interface device of an internet matching device having a link switch circuit having an interface port so that when a connected port fails, the service is automatically switched to another port to maintain stable service.

As shown in FIG. 1, at least one slave board 12a-12n is connected to the master board 11 by a VME bus, and the master board 11 is connected to the master board 11. One Ethernet interface device for connecting a workstation is provided and the system management device 20 is connected. One of the slave boards 12a-12n connects an external LNA network to a final slave board. LAN interface device is provided to the LAN network matching device 30 is connected.

As described above, the LAN interface device provided in any one of the master board 11 and the slave boards 12a-12n includes the Ethernet controller 13, the modulation / demodulation unit 14, and transmission / reception as shown in FIG. 2. It consists of a unit 15 and a connector 16, the Ethernet controller 13 is provided with a system management device 20 to be connected to the master board 11 in the Internet matching device 10, for example a LAN interface device To control transmission and reception of data between the LAN matching device 30 connected to the final slave board 12n to be processed, and to process the data received from the system management device 20 or the LAN matching device 30 in a predetermined state. Transmits the signal to the dual port RAM (DPRAM) of the master board 11 or the final slave board 12n, and processes the signal transmitted to the system management apparatus 20 or the LAN matching device 30 to perform a modulation / demodulation unit ( Output to side 14).

The modulator / demodulator 14 modulates and demodulates data transmitted and received between the connected external system management apparatus 20 or LAN matching apparatus 30 and the Internet matching apparatus 10.

The transceiver unit 15 processes data transmitted and received between the external system management device 20 or the LAN matching device 30 and the Internet matching device 10 connected to the connector 16 in a predetermined state to connect the connector 16 to the connector 16. Transmit to the modulator / demodulator 14.

Connector 16 is an RJ45 connector for 10BASE-T connection to connect an external system management device 20 or LAN matching device 30 to the Ethernet network.

The operation for data transmission and reception between the Internet matching device and the external matching device through the conventional LAN interface device configured as described above is as follows.

The system matching device 20 is connected to the RJ45 connector 16 for the 10BASE-T connection of the LAN interface device having a single port in the master board 11 of the Internet matching device 10, and consists of a plurality of devices. External LAN registration to RJ45 connector 16 for 10BASE-T connection of any of the slave boards 12a-12n, e.g., the last slave board 12 as shown in FIG. With the device 30 connected, the master board 11 of the internet matching device 10 may perform data access according to a data access request in the LAN matching device 30 connected to the connector 16, for example. Communication with the requested LAN matching device 30 is performed, and the data access request signal of the LAN matching device 30 is provided on the slave board 12n and is configured as shown in FIG. 2. Receiving port (Rx +, Rx-) It applied when transmitting and receiving unit 15 is a data access request signal to the side of a modulation / demodulation unit 14 through the next data transmission port (D1 +, D1-) processing in a predetermined state.

The demodulator / demodulator 14 demodulates the signals applied through the reception ports Rx + and Rx− into Manchester, demodulates the data, and then transmits the data reception enable signal RENA to the Ethernet controller 13. After transmission, the data access request signal received in synchronization with the reception clock RCLK is transmitted to the data reception port RxD side of the Ethernet controller 13.

At this time, the Ethernet controller 13 analyzes the received data access request signal of the LAN matching device 30 and writes it to the slave board 12n dual port RAM of the Internet matching device 10.

When the data access request signal of the external LAN matching device 30 is recorded in the slave board 12n dual port RAM of the internet matching device 10 as described above, the processor of the master board 11 transmits the slave board 12n via the VME bus. Reads the communication request signal recorded in the dual port RAM) and processes the requested data.

In addition, at the time of data transmission, the Ethernet controller 13 of the interface device accesses the data recorded in the dual port RAM, and then applies a data transmission enable signal (TENA) to the modulation / demodulation section 14 side. Then, the accessed data is transferred to the modulation / demodulation section 14 in synchronization with the transmission clock TCLK applied by the modulation / demodulation section 14.

The modulator / demodulator 14 modulates PCM data received from the Ethernet controller 13 by Manchester coding suitable for LAN communication, and then transmits the data to the transceiver 15 through the transmission ports Tx + and Tx-. The unit 15 processes the received data according to electrical characteristics and transmits the data to the LAN matching device 30 through the connector 16.

In the above, data communication between the external LAN matching device 30 and the Internet matching device 10 connected to the connector 16 of the LAN interface device has been described, but is connected to the master board 11 of the Internet matching device 10. Communication with the system management apparatus 20 is also performed as described above.

As described above, the conventional LAN interface device provided in the Internet matching device to maintain data communication by converting data having different coding formats in communication between the Internet matching device and an external LAN matching device or a system management device. Since only one Ethernet communication port is provided, there is a problem in that data communication cannot be performed when a link failure occurs due to a cable error, a component defect, or other causes.

In addition, the LAN interface boards of the master board and the slave board are separated so that in order to transmit data to the external Internet, the processor of the master board writes data to the dual port RAM of the slave board, and then uses the LAN interface device to communicate with the Internet. Since the Internet communication is performed by converting the data into a proper format, there is a delay in the time required for data transmission, thereby delaying the provision of the service and reducing the efficiency of using the bus.

The present invention has been made in view of the above-described general problems, and an object thereof is to provide a service having a LAN interface device including two Ethernet ports to connect a system management device and a LAN matching device to a master board in an Internet matching device. If an error is detected in one Ethernet port, link switching is used to select another port to maintain a stable data communication service.

In addition, the present invention is to transmit the data accessed from the master board directly to the corresponding board through the LAN interface device to communicate with the Internet matching device so that the service can be provided quickly.

1 is a schematic diagram showing a state in which a system management device and a LAN matching device are connected in a conventional Internet matching device.

Fig. 2 is a detailed block diagram showing a conventional LAN interface device configuration.

Figure 3 is a schematic diagram showing a state in which the system management device and the LAN matching device connected in the Internet matching device according to the present invention.

Figure 4 is a detailed block diagram showing the configuration of the LAN interface device of the Internet matching device according to the present invention.

Figure 5 is a detailed view showing the configuration of the link control and switch in Figure 4;

FIG. 6 is a detailed view showing the configuration of a link control unit in FIG. 5; FIG.

<Explanation of symbols for the main parts of the drawings>

100: internet matching device 110: master board

120a-120n: Slave board 111: First port

112: second port 113: first transmission and reception unit

114: second transmission and reception unit 115: first side / demodulation unit

116: second side / demodulator 117: link control and switch unit

118: Ethernet controller 200: system matching device

300: LAN matching device

According to the present invention for achieving the above object, the LAN interface converts data received by the LAN communication protocol from each of the external matching devices of the plurality of ports into a protocol suitable for Ethernet communication, and transmits the data to each of the external matching devices. First and second transmitting and receiving means for converting the Ethernet communication protocol into a LAN communication protocol, and TCP / IP format data of each of the external matching devices applied by the first and second transmitting and receiving means are modulated into PCM data, and the Ethernet matching device First and second modulation means for modulating the PCM data transmitted from the PC to the external matching device into TCP / IP type data, and connected to the processor of the master board to control data transmission and reception between the Ethernet matching device and the external matching device. Connect the Ethernet control means and the data communication link between the Ethernet matching device and the external matching device. And link control and switching means for switching the data communication link to a link in a standby state without performing communication when a link failure is detected.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As can be seen in Figure 3, the system management apparatus 200 that is a workstation on the master board 110 in the Internet matching device 100 consisting of a master board 110 and a plurality of slave boards (120a-120n) ) And the external LAN matching device 300.

As described above, a LAN interface device for connecting the system management device 200 and the LAN matching device 300 through an interface device having two matching ports to the master board 110 of the Internet matching device 100 is shown in FIG. 4. As can be seen, the first and second ports 111 and 112, the first and second transceivers 113 and 114, the first and second modulation / demodulation units 115 and 116, the link control and switch unit 117, and Ethernet controller 118, the first and second ports (111, 112) is composed of RJ45 connector for 10BASE-T connection, each of the port management system 200 and LAN matching device 300 Interconnect data sent and received by connecting.

The first and second transceivers 113 process data received from the system management apparatus 200 or the LAN matching apparatus 300 in a predetermined state suitable for the system, and process the data transmitted from the Internet matching apparatus 100. It is provided with a fault detection unit (113a, 114a) for processing in a predetermined state suitable for LAN communication, and detects whether there is a link failure between connected matching devices and outputs a signal corresponding thereto.

The first and second modulation / demodulators 115 demodulate data received through the first and second transmitter / receivers 115 and 116 to be used in the Internet matching device 100 to demodulate the data. Manchester-coded the data transmitted from the system management apparatus 200 and the LAN matching apparatus 300 from the apparatus 100.

The link control and switch unit 117 controls a link of data transmitted and received between the Internet matching device 100 and the system management device 200 or the LAN matching device 300, and a failure is detected in any one link transmitted and received. In this case, the link is switched so that data is transmitted to the other link which is in a normal state.

Each of the first and second modulation / demodulation units 115 and 116 may include a data transmission port TxD, a data transmission enable port TENA, a transmission clock port TCLK, a data reception port RxD, and a data reception enable port. It is connected to the link control and switch unit 117 through the RENA, the receive clock port RCLK, and the data collision detection port CLSN.

The Ethernet controller 111 is connected to the processor of the master board 110 to control data transmission and reception between the system management apparatus 200 or the LAN matching apparatus 300, and to the system management apparatus 200 or the LAN matching apparatus 300. Process the data received from the system in a predetermined state and write the data to the dual port RAM (DPRAM) of the corresponding slave boards 120a-120n, and transmit and access data transmitted from the processor of the master board 110 to the link control and switch. It transmits to the part 117 side.

The Ethernet controller 111 includes two data transmission ports (TxD), a data transmission enable port (TENA), a transmission clock port (TCLK), a data reception port (RxD), a data reception enable port (RENA), and a reception clock. It is connected to the link control and switch unit 117 through a port RCLK and a data collision detection port CLSN.

In the case where the fault detection unit 113a or 114a provided in the first and second transmitter / receivers 113 and 114 is connected to the Ethernet controller 118 and the link control and switch unit 117, an error occurs in a matched link. Send and receive signals for it.

In addition, the link control and switch 117, as shown in Figure 5, the two Ethernet communication ports provided in the Ethernet controller 118 and the first and second modulation / demodulation unit (115, 116) in parallel. Data transmission and reception is performed according to the first and second buffers 117a and 117B to be connected, the transmit enable signal TENA and the receive enable signal RENA, the link failure signal LNKST, and the transmit clock TCLK. The link control unit 117c for generating an output port selection signal for the data and the output signal of the link control unit 117c by inverting the data output enable signal to the second buffer 117b side. Inverter INV is applied.

The second buffer 117b determines that a failure has occurred in one of the links for performing data transmission and reception at the link control unit 117c, and performs link switching according to an applied signal.

Also, as shown in FIG. 6, the link control unit 117c includes an OR gate OR for performing a logical multiplication of the data transmission enable signal TENa and the reception enable signal RENA, and the ORA. A de-flip-flop (DF / F) for receiving an output signal of the gate OR as a data signal and outputting a predetermined signal according to a transmission clock signal TCLK input to a clock terminal; The AND gate AND is configured to perform a logical multiplication on the signal LNKST, which is output from the signal input to one terminal and the input signal to the other terminal.

In the technical configuration having the function as described above, the operation for data transmission and reception is as follows.

For example, the system management device 200 is connected to the first port 111 of the LAN interface device configured as shown in FIG. 4 on the master board 110 of the Internet matching device 100, and the LAN is connected to the second port 112. In the state in which the matching device 300 is connected, when the data access request or data signal for transmission is detected from the LAN matching device 300 connected to the second port 112, the second transmitting / receiving unit 114 detects the first. The second transmitter / receiver 114 processes the received data access request signal or transmitted data to suit the electrical characteristics and then applies it to the second modulator / demodulator 116 through the transmission ports D1 +, D1-.

The modulation / demodulation unit 116, which has received the data access request signal or the transmission data through the reception ports Rx + and Rx-, transmits the receive enable signal RENE, which is a Manchester decoded signal, to the Ethernet controller 13 side. The received signal Rx for the demodulated data access request or the transmitted data is transmitted to the Ethernet controller 13 in synchronization with the transmission clock RCLK.

At this time, the Ethernet controller 118 receiving the data access request signal or the transmission data requests the processor side of the master board 110 to access the data or to record the transmission data.

When the data access request from the LAN matching device 300 is requested as described above, the processor of the master board 110 has the corresponding data among the plurality of slave boards 120a-120n connected to the required data through the VME bus. It reads the required data by accessing the dual port RAM of any slave board, and stores the received data in the dual port RAM of any slave board to record the corresponding data when it is requested to write the transmission data.

Subsequently, the processor of the master board 110 processes data accessed from any slave board dual port RAM in a predetermined state on its board, and then applies the data to the Ethernet controller 118 in the interface matching device. 118 applies a data transmission enable signal (TENA) to the link control and switch unit 117, and then transmits the data accessed according to the transmission clock TCLK applied from the link control and switch unit 117. It transmits to the link control and switch unit 117 side via (TxD).

The link control and switch unit 117 applies the data received from the Ethernet controller 118 to the second modulation / demodulation unit 116 through the switched port. Manchester-coded data received through the reception port Rx is transmitted to the transmission / reception unit 114 through the transmission ports Tx + and Tx-.

The transceiver 114 converts the received data into an electrical signal suitable for LAN communication, and then transmits the data to the second port 112 through the transmission ports Tx + and Tx- to the connected LAN matching device 300. do.

Although the communication between the LAN matching device 300 connected to the second port 112 and the Internet matching device 100 has been described above, the system matching device 200 connected to the first port 111 is required. The data access signal or transmission data proceeds in the same process as described above to perform data communication with the Internet matching device 100.

When the link connected between the internet matching device 100, the system management device 200, and the LAM matching device 300 is normal, the signal output from the link control unit 117c and gate AND of FIG. As shown in FIG. 5, the first port and the second port are directly connected to each other through the first buffer 117a to transmit and receive data.

As described above, when a data communication between ports directly connected through the first buffer 117a is in progress, a failure occurs in a link in which communication is performed, and thus a failure detection unit 113a provided in the first and second transceivers 113 is provided. When the error is detected at 114a, the failure detection unit of the corresponding transceiver unit in which the failure is detected is output to the link control and switch unit 117 and the Ethernet controller 118 side by outputting a link failure signal LNKST.

At this time, the link control unit 117c receiving the signal for link failure LNKST applies a data output control signal corresponding thereto to the first buffer 117a and at the same time the second buffer 117b through the inverter INV. To apply.

Accordingly, the first buffer 117a which directly connects the first and second ports is disabled to output data, and the second modulation / demodulator 116 receives the first port connected to the Ethernet controller 118. The second buffer 1127 connecting to the second port connected to the Ethernet controller 118 to the first modulation / demodulation unit 115 is enabled to maintain transmission and reception of data.

As shown in FIG. 6, the operation of the link control unit 117c according to the link failure may include the operation of the data transmission enable signal TENA and the data reception enable signal RENA to which the OR gate OR is input. When a logic sum operation is applied to the de-flip-flop DF / F as a data signal, the de-flip-flop DF / F synchronizes the input data according to the transmission clock signal TCLK input to the clock terminal CLK. Input to one terminal of gate (AND).

At this time, when the transmit enable signal (TENA) and the receive enable signal (RENA) are generated at the same time or any one of the two enable signals are generated, the signal output from the de- flip-flop (DF / F) is " Is output in the high " state and input to one terminal of the AND gate AND.

Therefore, when a failure does not occur in the link for performing data transfer, a signal of "low" is input to the other terminal of the AND gate AND, so that the output terminal is in a "low" state, thereby directly connecting the first buffer 117a. Maintain data communication through

However, when a failure occurs in a link in which data is transmitted and a signal for link failure LNKST is input to the other input terminal of the AND gate AND as high, the output terminal of the AND gate AND receives a high signal. Will print.

Accordingly, the second buffer 117b is enabled by the inversion of the inverter INV so that data is output.

In addition, since the output of the OR gate is "low" in the state where the enable signals (TENA, RENA) for data transmission and reception are not generated, the signal output from the de- flip-flop (DF / F) is also in the "low" state. It is input to one terminal of the row and gate AND.

Therefore, even though the signal LNKST for the link failure is input to the other terminal of the AND gate AND, the output terminal of the AND gate AND remains “low” so that the first buffer 117a is enabled. Keep it.

As described above, the present invention performs data communication by connecting the system matching device and the LAN matching device to the LAN interface device provided in the master board in the Internet matching device using the VME bus, thereby recording or writing data to the dual port RAM. The access operation of the received data is performed at one time, thereby providing promptness in the processing of the data transmitted and received.

In addition, the present invention provides stability and reliability to data communication because the communication is maintained by switching to another link when a failure occurs in the link during data communication through any link.

Claims (5)

In an internet matching device in which a master board and at least one slave board are connected to a VME bus, the internet matching device includes a plurality of ports for simultaneously connecting a system matching device and a LAN matching device to the master board. And a LAN interface device for switching a service link by switching to another port not executing a service. The LAN interface apparatus of claim 1, further comprising: first and second transmission / reception means for processing electrical characteristics of data signals transmitted and received through the plurality of ports; First and second modulation means for coding / decoding the transmitted / received data; Ethernet control means connected to the processor of the master board for controlling data transmission and reception between the Internet matching device and the external matching device; And a link control and switching means for connecting a data communication link between the internet matching device and the external matching device, and for connecting a link in a waiting state when a failure of a link in service is in progress. . 3. The LAN interface device of an internet matching device according to claim 2, wherein the first and second transmission and reception means comprises a failure occurrence detection means for detecting whether a link has a failure and outputting a signal thereof. 3. The apparatus of claim 2, wherein the link control and switching means includes first and second communication ports connected to the Ethernet control means and first and second communication ports connected to the first and second modulation / demodulation means. A first buffer connected directly to the enable signal; The first and second communication ports connected to the Ethernet control means and the first and second communication ports connected to the first and second modulation / demodulation means are crossed by an enable signal applied according to the detection of a link failure. A second buffer connected to each other; Link control means for outputting a data transmission / reception port selection signal according to a transmit enable signal (TENA), a receive enable signal (RENA), a link failure signal (LNKST), and a transmit clock (TCLK); Data output enable signal to the second buffer side by inverting the output signal of the link control means LAN interface device of the Internet matching device, characterized in that consisting of an inverter applied to. 5. The apparatus of claim 4, wherein the link control means comprises: first computing means for performing a logical sum operation on a transmit enable signal (TENA) and a receive enable signal (RENA) of data; A de-flip-flop for outputting the output signal of the first calculating means according to the transmission clock signal TCLK; And a second calculating means for performing a logical multiplication on the signal (LNKST) for the link failure inputted from the de-flop and input to one terminal and outputting it as a control signal. LAN interface device of the device.