US20010041461A1 - Process for forming high voltage junction termination extension oxide - Google Patents

Process for forming high voltage junction termination extension oxide Download PDF

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US20010041461A1
US20010041461A1 US09/167,177 US16717798D US2001041461A1 US 20010041461 A1 US20010041461 A1 US 20010041461A1 US 16717798 D US16717798 D US 16717798D US 2001041461 A1 US2001041461 A1 US 2001041461A1
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oxide
jte
oxide layer
substrate
ambient
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Rodney S. Ridley
Jason R. Trost
Raymond J. Webb
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Fairchild Semiconductor Corp
Harris Corp
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

Definitions

  • the present invention relates in general to the manufacture of high-voltage semiconductor integrated circuits, and is particularly directed to a new and improved process for forming a junction termination extension (JTE) oxide that enjoys reduced total oxide charge (Qox) and SiO 2 —Si interface trap density (Dit) parameters, thereby offering improved high voltage edge stability.
  • JTE junction termination extension
  • JTE junction termination extension
  • the conventional process begins by exposing the top surface of a semiconductor (silicon) substrate 1 , shown in FIG. 2A, to a ‘wet’ or steam ambient, so as to rapidly grow a relatively thick ubiquitous oxide layer 2 , that is to serve as part of the bulk JTE oxide.
  • the oxide layer 2 is then patterned, etched and cleaned/rinsed to open a plurality of implant apertures 3 , which expose corresponding (JTE dopant-implant) surface portions 4 in the top surface of substrate 1 .
  • step 105 conductivity type determining impurities 5 are implanted through the implant apertures 3 of the oxide layer 2 , forming a plurality of JTE surface regions shown at 6 in FIG. 2C.
  • This implant step introduces unwanted near-surface pockets of crystalline damage 7 in the vicinity of the top surface of the silicon substrate.
  • a wet or stream screen oxide layer 8 is rapidly grown directly on the JTE surface regions 6 , as shown in FIG. 2D.
  • the oxide layer 8 is grown rapidly and directly upon the implanted surface of the silicon, it is of relatively poor quality, and can be expected to negatively impact the quality of any subsequently formed oxide.
  • the device is subjected to a dopant drive-in step 109 , which causes the dopant of the implanted regions 6 to diffuse into the surrounding substrate, and essentially define the JTE structure, as shown at 6 ′ in FIG. 2E. Although some additional dopant diffusion will occur during subsequent oxidation, the bulk of the dopant drive-in is completed in this step.
  • the JTE oxide process is completed by performing a further rapid steam or wet oxidation step 111 , which fills in the implant apertures 3 with oxide 9 and results in the JTE structure shown in FIG. 2F.
  • each of the oxide layers formed in the process of FIGS. 1 and 2, particularly those overlying the implanted regions, are grown rapidly in a wet or stream atmosphere, they are of relatively low density. As a result they facilitate segregation or out-diffusion of dopants into the oxide, and reduce the quality of any oxide grown thereon. This has the unwanted effect of allowing the total oxide charge (Qox) and SiO 2 —Si interface trap density (Dit) to increase, which degrades high voltage stability.
  • the above-referenced shortcomings of conventional JTE oxide formation are effectively obviated by employing precursor densified thin oxide layers to improve the quality of subsequently formed thicker oxide layers, and performing multiple anneals in a dry or non-oxidizing atmosphere to remove implant damage and to set finalized geometry parameters.
  • the use of such an atmosphere for post JTE oxidation annealing substantially lowers Qox and Dit.
  • a relatively thin and dense precursor oxide layer is ubiquitously grown on the surface of a silicon substrate in a dry oxygen ambient.
  • the thickness of the oxide layer is increased in a steam or wet oxygen atmosphere, causing the growth of a relatively thick silicon dioxide layer. Because the thin precursor oxide layer is highly densified, it increases the density and quality of the thick oxide layer.
  • a post-oxidation anneal is then performed in a dry ambient or non-oxidizing atmosphere, which substantially reduces Qox and Dit.
  • the oxide then masked and etched to form a plurality of dopant implant apertures in the oxide layer.
  • JTE dopants are then implanted through the implant apertures of the oxide layer, forming a plurality of conductivity-modifying semiconductor JTE regions that extend to a prescribed implant depth from the top surface of the silicon substrate.
  • the substrate is annealed in a non-oxidizing or inert gas ambient.
  • the non-oxidizing atmosphere of the annealing step prevents oxidation of the top surface of the substrate from which the JTE regions extend, and thereby avoids negatively impacting subsequent oxide formation.
  • a dry oxide ambient cannot be used to anneal out the crystalline damage during this step, since formation of a highly dense oxide layer may cause the formation of oxidation-induced stacking faults.
  • the JTE dopants are then partially driven away from the near-surface portions into adjoining material of the substrate, to prevent segregation of the dopant into the oxide that will be subsequently grown.
  • a relatively thin and highly densified bulk oxide precursor layer is then grown on the exposed JTE dopant-implanted surface portions of the substrate to ensure precise control of subsequent oxide formation.
  • the bulk of the JTE oxide is then formed in a steam or wet oxygen atmosphere.
  • the substrate is annealed in a non-oxidizing or inert gas ambient, to cause a further drive-in of the JTE dopants.
  • the dry or non-oxidizing atmosphere of the post JTE oxidation annealing step substantially lowers Qox and Dit.
  • the reduction in Qox and Dit may be determined by carrying out conventional capacitance-voltage and associated electrical parameter measurements, such as those commonly employed for MOS capacitor structures.
  • FIG. 1 shows the process steps of a conventional JTE oxide process
  • FIGS. 2 A- 2 F are diagrammatic sectional views of a JTE semiconductor structure at respective steps of the process of FIG. 1;
  • FIGS. 3 A- 3 I are diagrammatic sectional views of a JTE semiconductor structure at respective steps of the JTE oxide process of the present invention.
  • FIG. 4 shows the sequence of steps of the JTE oxide formation process of the invention.
  • FIGS. 3 A- 3 I show the state of the device at respective steps of the processing flow sequence of FIG. 4.
  • the oxidation formation process begins by forming a relatively thick oxide layer 10 (e.g., 800 Angstroms) on a top surface 21 of a clean or epitaxial semiconductor substrate 20 , such as a silicon substrate of a first conductivity type (e.g., N type as a non-limiting example).
  • oxide layer 10 is formed by first slowly growing a relatively thin and dense precursor oxide layer, such as silicon dioxide 12 (FIG. 3A) in a dry oxygen (O 2 ) ambient, for example, at a temperature of 900° C., for 120 minutes, to a first thickness (e.g., 300 Angstroms).
  • step 403 the thickness of the silicon dioxide layer 10 is increased, by introducing steam (e.g., at a temperature on the order of 1050° C.) or a wet O 2 atmosphere (at a temperature of 1050° C.), for 120 minutes, causing the growth of a relatively thick silicon dioxide layer 14 at the silicon surface and incorporating therein the thin dense oxide layer 12 , to a thickness on the order of 80000 Angstroms, as shown in FIG. 3B. Because the thin precursor oxide layer 12 is a highly compact oxide layer, it increases the density and quality of the thick oxide layer 14 , relative to the oxide layer rapidly formed by the prior art process described previously.
  • steam e.g., at a temperature on the order of 1050° C.
  • a wet O 2 atmosphere at a temperature of 1050° C.
  • a post-oxidation anneal is performed in a dry ambient or non-oxidizing atmosphere, which serves to substantially reduce Qox and Dit.
  • the anneal may be carried out at a temperature on the order of 50° C. greater than the steam oxidation temperature (or 1100° C. in the present example), for 30 minutes, in an N 2 ambient.
  • the oxide-coated wafer is then masked, etched and cleaned/rinsed in a conventional manner in step 407 , to provide at least one (e.g., a plurality of) implant apertures 18 in the oxide layer 10 , which thereby selectively expose corresponding (JTE dopant-implant) surface portions 23 in the top surface 21 of the substrate 20 , as shown in FIG. 3C.
  • step 409 using a conventional implant operation, such as that described previously, conductivity type determining impurities 19 (e.g., P-type in the present example) are introduced (implanted) through the implant apertures 18 of the oxide layer 10 , so as to form a plurality of (P-type) conductivity-modifying semiconductor (JTE) regions 25 that extend to a prescribed implant depth from the top surface 21 of the substrate 20 , as shown in FIG. 3D.
  • this implant step causes crystalline damage in those portions 26 of the JTE regions 25 adjacent to the surface 21 , which must be removed to prevent stack fault formation.
  • the substrate is annealed in a non-oxidizing or inert gas ambient, such as but not limited to Ar, H 2 /N 2 forming gas, N 2 , and the like, to repair the displaced lattice sites, resulting in the structure of FIG. 3E.
  • a non-oxidizing or inert gas ambient such as but not limited to Ar, H 2 /N 2 forming gas, N 2 , and the like.
  • this anneal may be carried out at a temperature on the order of 800° C., for a period of 20 minutes.
  • the non-oxidizing atmosphere of the annealing step prevents oxidation of the surface portions 23 of the top surface 21 of the substrate 20 from which the JTE regions extend, and thereby avoids impacting subsequent oxide formation.
  • a dry oxide ambient cannot be used to anneal out the crystalline damage during this step, since the formation of a highly dense oxide layer may cause the formation of oxidation-induced stacking faults.
  • step 413 a partial drive-in of the conductivity type determining JTE dopants in regions 25 away from the near-surface portions into adjoining (surrounding) material of the semiconductor substrate 20 is performed, resulting in the expanded region structure 25 ′ shown in FIG. 3F.
  • This partial drive-in serves to prevent segregation of the dopant into the oxide that will be subsequently grown.
  • the respective time and temperature parameters for this step may be on the order of 160 minutes at 1200° C. The less than total dopant drive-in during this step conserves thermal budget, providing for substantial annealing time after the thickness of JTE termination oxide is finalized.
  • a relatively thin and highly densified bulk precursor oxide layer 30 is grown on the exposed JTE dopant-implanted surface portions 23 of the top surface 21 of the substrate 20 , in a dry O 2 ambient, for example, at a temperature of 1050° C., for 45 minutes, to a thickness on the order of 600 Angstroms.
  • the densified bulk precursor oxide layer 30 ensures precise control of subsequent bulk oxide formation.
  • the bulk of the JTE oxide is formed by introducing steam (e.g., at a temperature on the order of 1050° C.) or a wet O 2 atmosphere (at a temperature of 1050° C.), for 170 minutes, causing the growth of a relatively thick silicon dioxide layer 32 on the surface of the silicon, and incorporating the thin dense oxide layer 30 , for example to a thickness on the order of one micron, as shown in FIG. 3H.
  • steam e.g., at a temperature on the order of 1050° C.
  • a wet O 2 atmosphere at a temperature of 1050° C.
  • the substrate is again annealed in a non-oxidizing or inert gas ambient, such as but not limited to Ar, H 2 /N 2 forming gas, N 2 , and the like, referenced above, to effect a further drive-in of the conductivity type determining JTE dopants—forming regions 25 ′′, shown in the structure of FIG. 3I.
  • a non-oxidizing or inert gas ambient such as but not limited to Ar, H 2 /N 2 forming gas, N 2 , and the like, referenced above.
  • this final, post-JTE oxidation anneal may be carried out at a temperature on the order of 1100° C., for a period of 30 minutes.
  • the ‘dry’ or non-oxidizing atmosphere of the post JTE oxidation annealing step substantially lowers Qox and Dit.
  • the extent to which high voltage edge stability is improved, as represented by a reduction in Qox and Dit may be determined by carrying out conventional capacitance-voltage and associated electrical parameter measurements,

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Abstract

A process for forming a junction termination extension (JTE) oxide having reduced total oxide charge and SiO2—Si interface trap density parameters uses precursor densified thin oxide layers, to improve the quality of subsequently formed thicker oxide layers, and multiple anneals to remove implant damage and set geometry parameters. After formation of a first dual oxide layer, and a post-oxidation anneal, the oxide is patterned and JTE regions are implanted. Implant-based near surface crystalline damage is annealed out in a non-oxidizing ambient, and JTE dopants are partially driven into adjoining material of the substrate. A thin dense bulk precursor oxide layer is grown on the exposed JTE dopant-implanted surface portions of the substrate, followed by forming the bulk of the JTE oxide in a steam or wet oxygen atmosphere. The substrate is then annealed in a non-oxidizing ambient, to cause a further drive-in of the JTE dopants. The associated reduction in Qox and Dit improves high voltage edge stability.

Description

    FIELD OF THE INVENTION
  • The present invention relates in general to the manufacture of high-voltage semiconductor integrated circuits, and is particularly directed to a new and improved process for forming a junction termination extension (JTE) oxide that enjoys reduced total oxide charge (Qox) and SiO[0001] 2—Si interface trap density (Dit) parameters, thereby offering improved high voltage edge stability.
    • BACKGROUND OF THE INVENTION
  • High-voltage discrete and integrated circuit devices, which are currently employed in a wide variety of electrical and electronic circuit architectures, are subject to excessive electric field intensity created in the vicinity of a reverse-biased PN junction. One particularly effective mechanism to deal with this problem has been to use a junction termination extension (JTE), as a barrier against the effects of the electric field. In a typical architecture, the JTE device is passivated by a relatively thick bulk oxide layer that is formed by the process sequence shown in FIG. 1, respective steps of which yield a device structure shown in the associated cross-sectional diagrams of FIGS. [0002] 2A-2F.
  • More particularly, as shown at step [0003] 101, the conventional process begins by exposing the top surface of a semiconductor (silicon) substrate 1, shown in FIG. 2A, to a ‘wet’ or steam ambient, so as to rapidly grow a relatively thick ubiquitous oxide layer 2, that is to serve as part of the bulk JTE oxide. As shown at step 103 and FIG. 2B, the oxide layer 2 is then patterned, etched and cleaned/rinsed to open a plurality of implant apertures 3, which expose corresponding (JTE dopant-implant) surface portions 4 in the top surface of substrate 1.
  • In [0004] step 105, conductivity type determining impurities 5 are implanted through the implant apertures 3 of the oxide layer 2, forming a plurality of JTE surface regions shown at 6 in FIG. 2C. This implant step introduces unwanted near-surface pockets of crystalline damage 7 in the vicinity of the top surface of the silicon substrate. In order to remove this crystalline damage and prevent stacking fault formation, at step 107, a wet or stream screen oxide layer 8 is rapidly grown directly on the JTE surface regions 6, as shown in FIG. 2D. Unfortunately, because the oxide layer 8 is grown rapidly and directly upon the implanted surface of the silicon, it is of relatively poor quality, and can be expected to negatively impact the quality of any subsequently formed oxide.
  • Following formation of the screen oxide layer [0005] 8, the device is subjected to a dopant drive-in step 109, which causes the dopant of the implanted regions 6 to diffuse into the surrounding substrate, and essentially define the JTE structure, as shown at 6′ in FIG. 2E. Although some additional dopant diffusion will occur during subsequent oxidation, the bulk of the dopant drive-in is completed in this step. The JTE oxide process is completed by performing a further rapid steam or wet oxidation step 111, which fills in the implant apertures 3 with oxide 9 and results in the JTE structure shown in FIG. 2F.
  • Because each of the oxide layers formed in the process of FIGS. 1 and 2, particularly those overlying the implanted regions, are grown rapidly in a wet or stream atmosphere, they are of relatively low density. As a result they facilitate segregation or out-diffusion of dopants into the oxide, and reduce the quality of any oxide grown thereon. This has the unwanted effect of allowing the total oxide charge (Qox) and SiO[0006] 2—Si interface trap density (Dit) to increase, which degrades high voltage stability.
    • SUMMARY OF THE INVENTION
  • In accordance with the present invention, the above-referenced shortcomings of conventional JTE oxide formation are effectively obviated by employing precursor densified thin oxide layers to improve the quality of subsequently formed thicker oxide layers, and performing multiple anneals in a dry or non-oxidizing atmosphere to remove implant damage and to set finalized geometry parameters. The use of such an atmosphere for post JTE oxidation annealing substantially lowers Qox and Dit. [0007]
  • In order to ensure precise control of subsequent oxide formation, a relatively thin and dense precursor oxide layer is ubiquitously grown on the surface of a silicon substrate in a dry oxygen ambient. The thickness of the oxide layer is increased in a steam or wet oxygen atmosphere, causing the growth of a relatively thick silicon dioxide layer. Because the thin precursor oxide layer is highly densified, it increases the density and quality of the thick oxide layer. [0008]
  • A post-oxidation anneal is then performed in a dry ambient or non-oxidizing atmosphere, which substantially reduces Qox and Dit. The oxide then masked and etched to form a plurality of dopant implant apertures in the oxide layer. JTE dopants are then implanted through the implant apertures of the oxide layer, forming a plurality of conductivity-modifying semiconductor JTE regions that extend to a prescribed implant depth from the top surface of the silicon substrate. [0009]
  • In order to remove near surface crystalline damage caused by the implant, the substrate is annealed in a non-oxidizing or inert gas ambient. The non-oxidizing atmosphere of the annealing step prevents oxidation of the top surface of the substrate from which the JTE regions extend, and thereby avoids negatively impacting subsequent oxide formation. A dry oxide ambient cannot be used to anneal out the crystalline damage during this step, since formation of a highly dense oxide layer may cause the formation of oxidation-induced stacking faults. The JTE dopants are then partially driven away from the near-surface portions into adjoining material of the substrate, to prevent segregation of the dopant into the oxide that will be subsequently grown. [0010]
  • A relatively thin and highly densified bulk oxide precursor layer is then grown on the exposed JTE dopant-implanted surface portions of the substrate to ensure precise control of subsequent oxide formation. The bulk of the JTE oxide is then formed in a steam or wet oxygen atmosphere. [0011]
  • After the bulk oxide has been grown to its desired thickness, the substrate is annealed in a non-oxidizing or inert gas ambient, to cause a further drive-in of the JTE dopants. The dry or non-oxidizing atmosphere of the post JTE oxidation annealing step substantially lowers Qox and Dit. The reduction in Qox and Dit (and thereby the extent to which high voltage edge stability is improved) may be determined by carrying out conventional capacitance-voltage and associated electrical parameter measurements, such as those commonly employed for MOS capacitor structures.[0012]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows the process steps of a conventional JTE oxide process; [0013]
  • FIGS. [0014] 2A-2F are diagrammatic sectional views of a JTE semiconductor structure at respective steps of the process of FIG. 1;
  • FIGS. [0015] 3A-3I are diagrammatic sectional views of a JTE semiconductor structure at respective steps of the JTE oxide process of the present invention; and
  • FIG. 4 shows the sequence of steps of the JTE oxide formation process of the invention.[0016]
    • DETAILED DESCRIPTION
  • The process through which a high voltage junction termination extension oxide is formed on a semiconductor substrate/wafer in accordance with a preferred embodiment of the present invention will now be described with reference to the cross-sectional diagrams of FIGS. [0017] 3A-3I, that show the state of the device at respective steps of the processing flow sequence of FIG. 4.
  • As shown in FIGS. 3A and 3B, the oxidation formation process begins by forming a relatively thick oxide layer [0018] 10 (e.g., 800 Angstroms) on a top surface 21 of a clean or epitaxial semiconductor substrate 20, such as a silicon substrate of a first conductivity type (e.g., N type as a non-limiting example). In order to ensure precise control of subsequent oxide formation, in step 401, oxide layer 10 is formed by first slowly growing a relatively thin and dense precursor oxide layer, such as silicon dioxide 12 (FIG. 3A) in a dry oxygen (O2) ambient, for example, at a temperature of 900° C., for 120 minutes, to a first thickness (e.g., 300 Angstroms).
  • Next, in [0019] step 403, the thickness of the silicon dioxide layer 10 is increased, by introducing steam (e.g., at a temperature on the order of 1050° C.) or a wet O2 atmosphere (at a temperature of 1050° C.), for 120 minutes, causing the growth of a relatively thick silicon dioxide layer 14 at the silicon surface and incorporating therein the thin dense oxide layer 12, to a thickness on the order of 80000 Angstroms, as shown in FIG. 3B. Because the thin precursor oxide layer 12 is a highly compact oxide layer, it increases the density and quality of the thick oxide layer 14, relative to the oxide layer rapidly formed by the prior art process described previously.
  • Next, as shown at [0020] step 405, a post-oxidation anneal is performed in a dry ambient or non-oxidizing atmosphere, which serves to substantially reduce Qox and Dit. For this purpose, the anneal may be carried out at a temperature on the order of 50° C. greater than the steam oxidation temperature (or 1100° C. in the present example), for 30 minutes, in an N2 ambient. The oxide-coated wafer is then masked, etched and cleaned/rinsed in a conventional manner in step 407, to provide at least one (e.g., a plurality of) implant apertures 18 in the oxide layer 10, which thereby selectively expose corresponding (JTE dopant-implant) surface portions 23 in the top surface 21 of the substrate 20, as shown in FIG. 3C.
  • In step [0021] 409, using a conventional implant operation, such as that described previously, conductivity type determining impurities 19 (e.g., P-type in the present example) are introduced (implanted) through the implant apertures 18 of the oxide layer 10, so as to form a plurality of (P-type) conductivity-modifying semiconductor (JTE) regions 25 that extend to a prescribed implant depth from the top surface 21 of the substrate 20, as shown in FIG. 3D. As described previously, this implant step causes crystalline damage in those portions 26 of the JTE regions 25 adjacent to the surface 21, which must be removed to prevent stack fault formation.
  • For this purpose, at [0022] step 411, the substrate is annealed in a non-oxidizing or inert gas ambient, such as but not limited to Ar, H2/N2 forming gas, N2, and the like, to repair the displaced lattice sites, resulting in the structure of FIG. 3E. As a non-limiting example, this anneal may be carried out at a temperature on the order of 800° C., for a period of 20 minutes. The non-oxidizing atmosphere of the annealing step prevents oxidation of the surface portions 23 of the top surface 21 of the substrate 20 from which the JTE regions extend, and thereby avoids impacting subsequent oxide formation. A dry oxide ambient cannot be used to anneal out the crystalline damage during this step, since the formation of a highly dense oxide layer may cause the formation of oxidation-induced stacking faults.
  • In step [0023] 413, a partial drive-in of the conductivity type determining JTE dopants in regions 25 away from the near-surface portions into adjoining (surrounding) material of the semiconductor substrate 20 is performed, resulting in the expanded region structure 25′ shown in FIG. 3F. This partial drive-in serves to prevent segregation of the dopant into the oxide that will be subsequently grown. The respective time and temperature parameters for this step may be on the order of 160 minutes at 1200° C. The less than total dopant drive-in during this step conserves thermal budget, providing for substantial annealing time after the thickness of JTE termination oxide is finalized.
  • Next, as shown in FIG. 3G, and at [0024] step 415, a relatively thin and highly densified bulk precursor oxide layer 30 is grown on the exposed JTE dopant-implanted surface portions 23 of the top surface 21 of the substrate 20, in a dry O2 ambient, for example, at a temperature of 1050° C., for 45 minutes, to a thickness on the order of 600 Angstroms. Like the thin precursor oxide layer 12 formed in step 401, the densified bulk precursor oxide layer 30 ensures precise control of subsequent bulk oxide formation.
  • Following the formation of the thin [0025] precursor oxide layer 30 within the implant apertures 18, at step 417 the bulk of the JTE oxide is formed by introducing steam (e.g., at a temperature on the order of 1050° C.) or a wet O2 atmosphere (at a temperature of 1050° C.), for 170 minutes, causing the growth of a relatively thick silicon dioxide layer 32 on the surface of the silicon, and incorporating the thin dense oxide layer 30, for example to a thickness on the order of one micron, as shown in FIG. 3H. Again since bulk precursor oxide layer 30 is highly compact and densified, it increases the density and quality of the thick JTE oxide layer 32. During step 417, the thickness of dense oxide layer 30 is not significantly altered, as its thickness and density make it a substantially diffusion-limited film.
  • Once the [0026] bulk oxide 32 has been grown to its desired thickness, the substrate is again annealed in a non-oxidizing or inert gas ambient, such as but not limited to Ar, H2/N2 forming gas, N2, and the like, referenced above, to effect a further drive-in of the conductivity type determining JTE dopants—forming regions 25″, shown in the structure of FIG. 3I. As a non-limiting example, this final, post-JTE oxidation anneal may be carried out at a temperature on the order of 1100° C., for a period of 30 minutes. The ‘dry’ or non-oxidizing atmosphere of the post JTE oxidation annealing step substantially lowers Qox and Dit. The extent to which high voltage edge stability is improved, as represented by a reduction in Qox and Dit, may be determined by carrying out conventional capacitance-voltage and associated electrical parameter measurements, such as those commonly employed for MOS capacitor structures.
  • As will be appreciated from the foregoing description, the above-referenced shortcomings of conventional JTE oxide formation are effectively obviated by employing precursor densified thin oxide layers to improve the quality of subsequently formed thicker oxide layers, and performing multiple anneals in a dry or non-oxidizing atmosphere to remove implant damage and to set finalized geometry parameters. The use of such an atmosphere for post JTE oxidation annealing substantially lowers Qox and Dit. [0027]
  • While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as are known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art. [0028]

Claims (9)

What is claimed:
1. A method of manufacturing a semiconductor device comprising the steps of:
(a) introducing conductivity type determining impurities into a selected surface portion of a semiconductor substrate, so as to form a region containing near-surface region crystalline damage;
(b) annealing the structure resulting from step (a) in a non-oxidizing atmosphere to reduce said near-surface region crystalline damage;
(c) performing partial drive-in of said conductivity type determining impurities away from said near-surface region to material of said semiconductor substrate adjoining said region;
(d) forming an insulator layer upon said region; and
(e) annealing the structure resulting from step (d) in a non-oxidizing atmosphere and effecting a further drive-in of said conductivity type determining impurities to material of said semiconductor substrate adjoining said region.
2. A method according to
claim 1
, wherein step (d) comprises forming said insulator layer to a first thickness upon said region in a first ambient, and thereafter increasing the thickness of said insulator in a second ambient.
3. A method according to
claim 2
, wherein step (d) comprises forming a first oxide layer to said first thickness upon said region in a first oxide ambient, and thereafter forming, in a second oxide ambient, a second oxide layer, that incorporates therein said first oxide layer, to a second thickness greater than said first thickness.
4. A method according to
claim 1
, wherein step (a) comprises implanting said conductivity type determining impurities into said selected surface portion of a semiconductor substrate, so as to form said region containing near-surface region crystalline damage.
5. A method according to
claim 4
, wherein step (a) includes the precursor steps of forming a relatively thin and dense precursor oxide layer on said substrate in a dry oxygen ambient, growing a relatively thick oxide layer that incorporates therein said precursor oxide layer, conducting a post-oxidation anneal in a non-oxidizing atmosphere, so as to substantially reduce total oxide charge (Qox) and SiO2—Si interface trap density (Dit), and patterning said oxide layers to form a plurality of JTE conductivity type determining impurity implant apertures therein.
6. A method according to
claim 3
, wherein step (d) comprises growing said first oxide layer as a relatively thin and highly densified bulk oxide precursor layer, and growing said second oxide layer as a bulk JTE oxide in a steam or wet oxygen atmosphere.
7. A method of manufacturing a junction termination extension (JTE) semiconductor device comprising the steps of:
(a) forming a first densified relatively thin and dense precursor oxide layer on a semiconductor substrate;
(b) growing on said semiconductor substrate a second relatively thick oxide layer that incorporates therein said first oxide layer;
(c) performing a post-oxidation anneal of the structure resulting from step (b), so as to reduce total oxide charge (Qox) and oxide-substrate interface trap density (Dit) parameters;
(d) patterning said first and said oxide layers and implanting JTE dopants through implant apertures of the patterned oxide layers, thereby forming a plurality of JTE regions that extend to a prescribed implant depth from the top surface of said substrate;
(e) annealing said substrate in a non-oxidizing atmosphere to remove near surface crystalline damage caused by implantation of JTE dopants, and effecting a partial drive-in of implanted JTE dopants;
(f) growing a third, relatively thin and highly densified bulk precursor oxide layer on exposed JTE-implanted surface portions of said substrate;
(g) growing a fourth, relatively thick bulk oxide layer on said third oxide layer; and
(h) annealing said substrate in a non-oxidizing gas ambient, so as to further drive-in said JTE dopants, and reduce said total oxide charge (Qox) and oxide-substrate interface trap density (Dit) parameters.
8. A method according to
claim 7
, wherein step (a) is carried out in a dry oxygen ambient, and step (b) is carried out in a wet or stream atmosphere.
9. A method according to
claim 7
, wherein step (c) is carried out in a dry ambient or non-oxidizing atmosphere.
US09/167,177 1998-10-06 1998-10-06 Process for forming high voltage junction termination extension oxide Granted US20010041461A1 (en)

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