US20010039088A1 - Self-aligned trench capacitor capping process for high density dram cells - Google Patents
Self-aligned trench capacitor capping process for high density dram cells Download PDFInfo
- Publication number
- US20010039088A1 US20010039088A1 US09/426,754 US42675499A US2001039088A1 US 20010039088 A1 US20010039088 A1 US 20010039088A1 US 42675499 A US42675499 A US 42675499A US 2001039088 A1 US2001039088 A1 US 2001039088A1
- Authority
- US
- United States
- Prior art keywords
- trench
- silicon nitride
- pad
- patterning
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
Definitions
- the invention generally relates to a process for manufacturing memory cells. More particularly, the invention relates to a self-aligned trench capacitor capping process for high density DRAM cells.
- FIG. 1 shows a trench capacitor for use in a 256 Mbit DRAM.
- the trench capacitor includes substrate 100 with trench 101 .
- Filling trench 101 is polycrystalline silicon 102 .
- Near the top of trench 101 is collar 103 .
- a side of collar 103 is open to diffusion region 114 , which is connected to diffusion region 113 forming the drain region of MOS transistor 114 .
- MOS transistor 114 also includes gate 115 , gate oxide 105 , and source diffusion region 112 .
- Word line 109 connects gate 115 a shallow trench isolation (STI) region 107 isolates trench 101 from other trenches.
- the top of polycrystalline silicon 102 is bounded by silicon nitride layer 106 to contain the shallow trench isolation 107 .
- STI shallow trench isolation
- the silicon nitride layer 106 is also referred to as an STI liner.
- Oxide 104 acts as a buffer between polycrystalline silicon 102 and silicon nitride layer 106 .
- word line 110 passes by word line 114 without affecting the operation of the capacitor formed in trench 102 .
- Total STI height may be almost 300 nm (250 nm under surface and 50 nm above the surface).
- FIG. 1B shows in greater detail the non-planar resultant structure.
- FIG. 1B is taken along line II of Figure IA. As shown in FIG. 1B, the beginning of the shallow trench isolation region is a recessed polycrystalline silicon trench 201 . Lining the sides of trench 201 is oxide 202 .
- Silicon nitride 203 (also referred to as a trench top capping film) is formed on top of oxide 202 . Shallow trench isolation fill 204 fills the remaining area bounded by trench liner 203 . As described above, processing the wafer after deposition results in a non-planar surface. At least one reason is that the different etching rates of the STI 204 , oxide 202 , and trench liner 203 result in an edge of trench liner 203 rising above the surrounding recessed material (oxide 202 and STI fill 204 ). The resulting non-planar surface of the wafer reduces yield as lithographic techniques cannot adequately focus on the surface of the wafer due to its non-planar features. Further, the oxidation layer 104 consumes the top surface of the polycrystalline silicon node 102 of the trench capacitor. It is difficult to control STI edge shape uniformly due to the rising edge of trench liner 203 . This shape impacts the threshold voltage of the transistor.
- the capping process of the invention includes deposition of a silicon nitride pad during the formation of the trench capacitor. After deposition of the pad, the pad is patterned to provide access to the underlying trench. The top service is etched to recess the top surface of the trench below the surface of the surrounding top surface of the wafer. Next, the recessed top surface of the trench is deposited with the trench-capping silicon nitride. The side of the trench to be overlaid with a passing word line is subjected to a deep etch to provide for shallow trench isolation.
- the exposed surface of the trench is subjected to oxidation to form a buffer and the remaining cavity is filled with STI fill.
- the surface of the wafer is etched back or subjected to chemical-mechanical polishing to planarize the surface of the wafer.
- the silicon nitride pad is then removed to expose the surface of the wafer.
- a gate oxide is grown or deposited and a gate electrode formed.
- the surface of the trench may be oxidized prior to deposition of the trench cap. This oxidation provides a buffer between the silicon nitride trench cap and the polycrystalline silicon of the trench.
- FIGS. 1A and 1B show conventional trench capping structures.
- FIGS. 2 A- 2 E illustrate a process for forming a trench capacitor for use with embodiments of the invention.
- FIGS. 3 - 9 and 11 show process views of the capping technique according to embodiments of the present invention.
- FIG. 10 is a view of the trench capping structure of FIG. 9 from line XII according to embodiments of the present invention.
- FIG. 12 shows a completed trench capacitor memory cell according to embodiments of the present invention.
- FIG. 13 shows a top down view of a memory cell in accordance with the present invention.
- FIGS. 14 and 15 show additional process steps in accordance with alternative embodiments of the present invention.
- the term substrate is intended to cover the body of the semiconductor wafer and/or any epitaxial growth of silicon, silicon oxide, or deposition of other material thereon.
- a MOS transistor may be formed in a substrate wherein the substrate may include an epitaxial growth of silicon on top of an original silicon wafer.
- the term is being used to commonly refer to the wafer and formed structures thereon.
- DRAM cell 500 includes a trench capacitor 255 and a transfer gate 260 .
- Trench capacitor 255 includes a first N + -type polycrystalline silicon fill 302 A, a second polycrystalline silicon fill 302 B, and a collar oxide 303 .
- Transfer gate 260 includes N-type source/drain and drain/source regions 502 formed in P-type well 275 and a WSi x /polycrystalline silicon gate 313 insulatively spaced from the channel region between source/drain region 502 and drain/source region 502 .
- a shallow trench isolation structure electrically isolates DRAM cell 250 from an adjacent DRAM cell and passing word line 314 . Passing word line 314 has a WSi x /polycrystalline silicon structure.
- a diffusion region 503 electrically connects third polycrystalline silicon fill 302 C and drain/source region 502 of MOS transfer gate 260 .
- This diffusion region is formed by out diffusing dopants from the highly doped polycrystalline silicon fill in the storage trench into P-well 275 .
- Diffusion region 503 and third polycrystalline silicon fill 302 C constitute a buried strap for connecting trench capacitor 255 to transfer gate 260 .
- buried N-type well 248 is formed in a P-type semiconductor substrate 300 by implanting phosphorous below the intended P-well for a memory cell array.
- a buried N-type well may also be formed by other methods, e.g., P-well implantation into an N-type semiconductor substrate or by epitaxy.
- a silicon nitride layer 320 having a thickness of about 0.2 micrometers is formed by chemical vapor deposition, for example, on the surface of athin oxide layer 304 having a thickness of about 10 nanometers that is thermally grown on semiconductor substrate 300 .
- Oxide layer 304 and silicon nitride layer 320 are patterned and etched to provide a mask for etching a trench 301 .
- Trench 301 is etched using an anisotropic etching process to a depth of about 7 micrometers as shown in FIG. 2B.
- an N-type capacitor plate 501 is formed by outdiffusing arsenic from the lower portion of trench 301 . This may be accomplished, for example, by depositing an arsenic doped glass layer, etching the arsenic doped glass layer to remain only at the lower portion of trench 301 , and performing an annealing process to outdiffuse the arsenic.
- a storage node dielectric layer such as an oxide-nitride (ON) layer or a nitride-oxide (NO) layer is then formed in trench 301 .
- a first conductive region is formed by filling trench 301 with an impurity-doped first conductive material such as N + -type polycrystalline silicon.
- the filling step may be carried out using chemical vapor deposition of silane or disilane, for example.
- the N + -type polycrystalline silicon is then etched back to a first level within trench 301 using an isotropic etch process to form fist trench fill 302 A.
- the level of first trench fill 302 A is, for example, about 1.0 micrometer below the surface of semiconductor substrate 300 .
- Collar oxide 303 is then formed on the sidewall of the portion of trench 301 opened by the etching back of the N + -type polycrystalline silicon using low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) TEOS as shown in FIG. 2C.
- LPCVD low pressure chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- a second conductive region is formed by filling in the remainder of trench 301 with a second conductive material.
- the second conductive material may be, for example, N + -type polycrystalline silicon or undoped polycrystalline silicon and may be formed by chemical vapor deposition (CVD).
- the second conductive material and the oxide collar 303 are then etched back to a second level within trench 303 to form second trench fill 302 B which is insulated from the semiconductor substrate by collar oxide 303 as shown in FIG. 2D.
- the depth of the buried strap to be formed in a subsequent process step is defined by this controlled etch-back of the second conductive material and collar oxide 303 .
- Second trench fill 302 B is etched back to about 0.1 micrometer below the surface of semiconductor substrate 300 .
- An in-situ removal of a native oxide in trench 301 is then performed.
- the native oxide on the upper surface of second trench fill 302 B and on the sidewall of trench 301 through which impurities for the buried strap will subsequently be outdiffused are removed.
- This removal of native oxide may be carried out by an in-situ prebake in a hydrogen ambient at a temperature greater than 850° C., for example.
- the portion of trench 301 opened by the etching back of collar oxide 303 and the second conductive material is then filled by a third conductive material 302 C.
- the third conductive material may be, for example, undoped polycrystalline silicon deposited by chemical vapor deposition (CVD).
- FIG. 3 shows a semiconductor substrate 300 with trench 301 formed therein.
- the trench 301 is filled with polycrystalline silicon 302 A, B, and C (collectively shown as polycrystalline silicon 302 ).
- poly Si 302 C is recessed about 50 nm below the Si surface. This process results in the formation of cavity 307 of FIG. 5.
- any type of etchant may be used.
- an isotropic etchant provides smooth rounded corners and which aids in the deposition of the uniform trench capping layer as shown in FIG. 4 below.
- An anisotropic etch has some advantages in that it prevents a lateral etch into recess of 302 C.
- trench capping nitride 308 is deposited on pad 320 , on the walls of aperture 306 , and on the surface of cavity 307 .
- An example silicon nitride deposition technique as is LPCVD at about 700 degrees C or PECVD at about 50 degrees C at a thickness of 5 to 50 nm.
- a cavity for the STI fill is formed.
- a resist is deposited, exposed, and unwanted portions removed.
- the wafer is subjected to an etchant to form cavity 309 as shown in FIG. 5.
- An example etch time and materials includes NF 3 gas for 3 minutes.
- the STI trench cavity isolates the polycrystalline silicon 302 by the STI fill 311 .
- the exposed trench is oxidized to form protective oxide layer 310 as shown in FIG. 6.
- An example oxidation time is 5 minutes to create a 10 nm layer.
- the cavity is filled with STI fill 311 .
- Chemical-mechanical polishing of the surface of the wafer may be used.
- the chemical-mechanical polishing planarizes the top surface of the wafer as shown in FIG. 10B.
- a hot phosphoric acid solution applied for 120 seconds may alternatively be used to remove the pad.
- oxide layer 304 is damaged. Accordingly, it is removed and regrown through techniques known in the art.
- the STI fill 311 has not been etched down to be planar with the oxide 304 . This provides a greater separation of passing word lines ( 313 of FIG. 13 below) and the polycrystalline silicon 302 as the STI fill 311 remains relatively thick.
- FIG. 10 shows the planarized result as shown from line XII of FIG. 9. As shown by the circled area highlighted by arrow A, the corner shape of STI edge is smooth without the intruding nitride layer.
- FIG. 11 shows subsequent formation of gate oxide 312 and the deposition of gate electrodes 313 A and 314 A.
- the end portion of the silicon nitride trench liner 308 has been planarized. This planarized structure eliminates the detrimental non-planar portion as found in FIG. 1A and 1B.
- Gate oxide 304 is damaged in the process described above and is, therefore, removed and regrown through known techniques.
- FIG. 13 shows a top view of trenches 701 and 702 .
- Active word line 706 attaches through buried strap 703 to the storage node of the capacitor in trench 702 .
- Trench top capping film is shown by hatched portion 704 .
- Passing word line 705 resides on top of trench 702 .
- FIG. 14 shows an alternative embodiment of the invention.
- oxide 601 is grown after the etching step of FIG. 3 to protect the top surface of polycrystalline silicon 302 from degradation.
- the thickness of oxide 601 may range between 50 to 200 ⁇ .
- FIG. 15 shows the deposition of silicon nitride capping layer 602 on oxide 601 .
- the thickness of capping layer 602 may range between 50 and 200 ⁇ .
- the thickness of the capping layer 602 (as well as 308 ) may be increased to upwards of 500 ⁇ .
- this increase in thickness is beneficial because it further isolates the STI fill from the underlying polycrystalline silicon.
- the opening to the trench will be smaller due to the thicker nitride layer. The smaller opening contributes to good lithography performance in active area patterning because the photo resist coating processing is relatively easier.
- the nitride capping layer may be an oxi-nitride layer. This may be deposited via PCVD at 780 ° C. The use of the oxi-nitride layer leads to greater stress reduction.
- One advantage of the present invention is that the capping nitride film only exists on the top of the trench, not in the peripheral circuit area.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
Description
- A. Technical Field
- The invention generally relates to a process for manufacturing memory cells. More particularly, the invention relates to a self-aligned trench capacitor capping process for high density DRAM cells.
- B. Background of the Invention
- FIG. 1 shows a trench capacitor for use in a 256 Mbit DRAM. The trench capacitor includes
substrate 100 withtrench 101. Fillingtrench 101, ispolycrystalline silicon 102. Near the top oftrench 101 iscollar 103. A side ofcollar 103 is open todiffusion region 114, which is connected todiffusion region 113 forming the drain region ofMOS transistor 114.MOS transistor 114 also includesgate 115, gate oxide 105, and source diffusion region 112. Word line 109 connects gate 115 a shallow trench isolation (STI)region 107 isolatestrench 101 from other trenches. The top ofpolycrystalline silicon 102 is bounded bysilicon nitride layer 106 to contain theshallow trench isolation 107. Thesilicon nitride layer 106 is also referred to as an STI liner.Oxide 104 acts as a buffer betweenpolycrystalline silicon 102 andsilicon nitride layer 106. On top ofshallow trench isolation 107,word line 110 passes byword line 114 without affecting the operation of the capacitor formed intrench 102. - Total STI height may be almost 300 nm (250 nm under surface and 50 nm above the surface).
- To create
silicon nitride layer 106, the layer is deposited then etched back using conventional process steps (not shown for simplicity). However, when etching back, the difference between the etching rates ofsilicon 100, oxide 104-105, silicon nitride (STI liner layer) 106, and shallow trench fill 107 result in a non-planar surface for the device during processing. FIG. 1B shows in greater detail the non-planar resultant structure. FIG. 1B is taken along line II of Figure IA. As shown in FIG. 1B, the beginning of the shallow trench isolation region is a recessedpolycrystalline silicon trench 201. Lining the sides oftrench 201 is oxide 202. Silicon nitride 203 (also referred to as a trench top capping film) is formed on top of oxide 202. Shallow trench isolation fill 204 fills the remaining area bounded bytrench liner 203. As described above, processing the wafer after deposition results in a non-planar surface. At least one reason is that the different etching rates of theSTI 204, oxide 202, andtrench liner 203 result in an edge oftrench liner 203 rising above the surrounding recessed material (oxide 202 and STI fill 204). The resulting non-planar surface of the wafer reduces yield as lithographic techniques cannot adequately focus on the surface of the wafer due to its non-planar features. Further, theoxidation layer 104 consumes the top surface of thepolycrystalline silicon node 102 of the trench capacitor. It is difficult to control STI edge shape uniformly due to the rising edge oftrench liner 203. This shape impacts the threshold voltage of the transistor. - In response to the problems stemming from the conventional capping process described above, an improved process for capping a trench capacitor is disclosed. The capping process of the invention includes deposition of a silicon nitride pad during the formation of the trench capacitor. After deposition of the pad, the pad is patterned to provide access to the underlying trench. The top service is etched to recess the top surface of the trench below the surface of the surrounding top surface of the wafer. Next, the recessed top surface of the trench is deposited with the trench-capping silicon nitride. The side of the trench to be overlaid with a passing word line is subjected to a deep etch to provide for shallow trench isolation. The exposed surface of the trench is subjected to oxidation to form a buffer and the remaining cavity is filled with STI fill. The surface of the wafer is etched back or subjected to chemical-mechanical polishing to planarize the surface of the wafer. The silicon nitride pad is then removed to expose the surface of the wafer. Finally, a gate oxide is grown or deposited and a gate electrode formed.
- In an alternative embodiment of the invention, the surface of the trench may be oxidized prior to deposition of the trench cap. This oxidation provides a buffer between the silicon nitride trench cap and the polycrystalline silicon of the trench.
- These and other novel advantages, details, embodiments, features and objects of the present invention will be apparent to those skilled in the art from following the detailed description of the invention, the attached claims and accompanying drawings, listed herein, which are useful in explaining the invention.
- In the following text and drawings, wherein similar reference numerals denote similar elements throughout the several views thereof, the present invention is explained with reference to illustrative embodiments, in which:
- FIGS. 1A and 1B show conventional trench capping structures.
- FIGS.2A-2E illustrate a process for forming a trench capacitor for use with embodiments of the invention.
- FIGS.3-9 and 11 show process views of the capping technique according to embodiments of the present invention.
- FIG. 10 is a view of the trench capping structure of FIG. 9 from line XII according to embodiments of the present invention.
- FIG. 12 shows a completed trench capacitor memory cell according to embodiments of the present invention.
- FIG. 13 shows a top down view of a memory cell in accordance with the present invention.
- FIGS. 14 and 15 show additional process steps in accordance with alternative embodiments of the present invention.
- The following detailed description of the invention refers to the substrate of a wafer and performing processing steps in the substrate. As used herein, the term substrate is intended to cover the body of the semiconductor wafer and/or any epitaxial growth of silicon, silicon oxide, or deposition of other material thereon. For example, a MOS transistor may be formed in a substrate wherein the substrate may include an epitaxial growth of silicon on top of an original silicon wafer. In general, the term is being used to commonly refer to the wafer and formed structures thereon.
- As shown in FIG. 12,
DRAM cell 500 includes atrench capacitor 255 and atransfer gate 260.Trench capacitor 255 includes a first N+-type polycrystalline silicon fill 302A, a secondpolycrystalline silicon fill 302B, and acollar oxide 303.Transfer gate 260 includes N-type source/drain and drain/source regions 502 formed in P-type well 275 and a WSix/polycrystalline silicon gate 313 insulatively spaced from the channel region between source/drain region 502 and drain/source region 502. A shallow trench isolation structure electrically isolatesDRAM cell 250 from an adjacent DRAM cell and passingword line 314. Passingword line 314 has a WSix/polycrystalline silicon structure. Adiffusion region 503 electrically connects thirdpolycrystalline silicon fill 302C and drain/source region 502 ofMOS transfer gate 260. This diffusion region is formed by out diffusing dopants from the highly doped polycrystalline silicon fill in the storage trench into P-well 275.Diffusion region 503 and thirdpolycrystalline silicon fill 302C constitute a buried strap for connectingtrench capacitor 255 to transfergate 260. - A method of manufacturing the
DRAM cell 500 will be described below with reference to FIGS. 2A-2E. As shown in FIG. 2A, buried N-type well 248 is formed in a P-type semiconductor substrate 300 by implanting phosphorous below the intended P-well for a memory cell array. A buried N-type well may also be formed by other methods, e.g., P-well implantation into an N-type semiconductor substrate or by epitaxy. Asilicon nitride layer 320 having a thickness of about 0.2 micrometers is formed by chemical vapor deposition, for example, on the surface ofathin oxide layer 304 having a thickness of about 10 nanometers that is thermally grown onsemiconductor substrate 300.Oxide layer 304 andsilicon nitride layer 320 are patterned and etched to provide a mask for etching atrench 301.Trench 301 is etched using an anisotropic etching process to a depth of about 7 micrometers as shown in FIG. 2B. Afterstorage node trench 301 is etched, an N-type capacitor plate 501 is formed by outdiffusing arsenic from the lower portion oftrench 301. This may be accomplished, for example, by depositing an arsenic doped glass layer, etching the arsenic doped glass layer to remain only at the lower portion oftrench 301, and performing an annealing process to outdiffuse the arsenic. A storage node dielectric layer (not shown) such as an oxide-nitride (ON) layer or a nitride-oxide (NO) layer is then formed intrench 301. After the dielectric is formed, a first conductive region is formed by fillingtrench 301 with an impurity-doped first conductive material such as N+-type polycrystalline silicon. The filling step may be carried out using chemical vapor deposition of silane or disilane, for example. The N+-type polycrystalline silicon is then etched back to a first level withintrench 301 using an isotropic etch process to form fist trench fill 302A. The level of first trench fill 302A is, for example, about 1.0 micrometer below the surface ofsemiconductor substrate 300.Collar oxide 303 is then formed on the sidewall of the portion oftrench 301 opened by the etching back of the N+-type polycrystalline silicon using low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) TEOS as shown in FIG. 2C. - A second conductive region is formed by filling in the remainder of
trench 301 with a second conductive material. The second conductive material may be, for example, N+-type polycrystalline silicon or undoped polycrystalline silicon and may be formed by chemical vapor deposition (CVD). The second conductive material and theoxide collar 303 are then etched back to a second level withintrench 303 to formsecond trench fill 302B which is insulated from the semiconductor substrate bycollar oxide 303 as shown in FIG. 2D. The depth of the buried strap to be formed in a subsequent process step is defined by this controlled etch-back of the second conductive material andcollar oxide 303.Second trench fill 302B is etched back to about 0.1 micrometer below the surface ofsemiconductor substrate 300. An in-situ removal of a native oxide intrench 301 is then performed. In particular, the native oxide on the upper surface of second trench fill 302B and on the sidewall oftrench 301 through which impurities for the buried strap will subsequently be outdiffused are removed. This removal of native oxide may be carried out by an in-situ prebake in a hydrogen ambient at a temperature greater than 850° C., for example. - The portion of
trench 301 opened by the etching back ofcollar oxide 303 and the second conductive material is then filled by a thirdconductive material 302C. The third conductive material may be, for example, undoped polycrystalline silicon deposited by chemical vapor deposition (CVD). - FIG. 3 shows a
semiconductor substrate 300 withtrench 301 formed therein. Thetrench 301 is filled withpolycrystalline silicon 302 A, B, and C (collectively shown as polycrystalline silicon 302). Thenpoly Si 302C is recessed about 50 nm below the Si surface. This process results in the formation ofcavity 307 of FIG. 5. It is noted that any type of etchant may be used. However, an isotropic etchant provides smooth rounded corners and which aids in the deposition of the uniform trench capping layer as shown in FIG. 4 below. An anisotropic etch has some advantages in that it prevents a lateral etch into recess of 302C. - As shown in FIG. 4,
trench capping nitride 308 is deposited onpad 320, on the walls ofaperture 306, and on the surface ofcavity 307. An example silicon nitride deposition technique as is LPCVD at about 700 degrees C or PECVD at about 50 degrees C at a thickness of 5 to 50 nm. - Next, a cavity for the STI fill is formed. Through known lithographic techniques, a resist is deposited, exposed, and unwanted portions removed. Next, the wafer is subjected to an etchant to form
cavity 309 as shown in FIG. 5. An example etch time and materials includes NF3 gas for 3 minutes. - The STI trench cavity isolates the
polycrystalline silicon 302 by the STI fill 311. In order to improve isolation, the exposed trench is oxidized to formprotective oxide layer 310 as shown in FIG. 6. An example oxidation time is 5 minutes to create a 10 nm layer. - As shown in FIG. 7, the cavity is filled with STI fill311. Chemical-mechanical polishing of the surface of the wafer may be used. Here the chemical-mechanical polishing planarizes the top surface of the wafer as shown in FIG. 10B. A hot phosphoric acid solution applied for 120 seconds may alternatively be used to remove the pad. At this point,
oxide layer 304 is damaged. Accordingly, it is removed and regrown through techniques known in the art. - The STI fill311 has not been etched down to be planar with the
oxide 304. This provides a greater separation of passing word lines (313 of FIG. 13 below) and thepolycrystalline silicon 302 as the STI fill 311 remains relatively thick. - FIG. 10 shows the planarized result as shown from line XII of FIG. 9. As shown by the circled area highlighted by arrow A, the corner shape of STI edge is smooth without the intruding nitride layer.
- FIG. 11 shows subsequent formation of
gate oxide 312 and the deposition of gate electrodes 313A and 314A. Here, the end portion of the siliconnitride trench liner 308 has been planarized. This planarized structure eliminates the detrimental non-planar portion as found in FIG. 1A and 1B.Gate oxide 304 is damaged in the process described above and is, therefore, removed and regrown through known techniques. - FIG. 13 shows a top view of
trenches 701 and 702. Active word line 706 attaches through buried strap 703 to the storage node of the capacitor in trench 702. Trench top capping film is shown by hatched portion 704. Passingword line 705 resides on top of trench 702. - FIG. 14 shows an alternative embodiment of the invention. In FIG. 14,
oxide 601 is grown after the etching step of FIG. 3 to protect the top surface ofpolycrystalline silicon 302 from degradation. The thickness ofoxide 601 may range between 50 to 200Å. - FIG. 15 shows the deposition of silicon nitride capping layer602 on
oxide 601. Here, the thickness of capping layer 602 may range between 50 and 200 Å. Also, the thickness of the capping layer 602 (as well as 308) may be increased to upwards of 500 Å. Here, this increase in thickness is beneficial because it further isolates the STI fill from the underlying polycrystalline silicon. Also, the opening to the trench will be smaller due to the thicker nitride layer. The smaller opening contributes to good lithography performance in active area patterning because the photo resist coating processing is relatively easier. - Further, the nitride capping layer may be an oxi-nitride layer. This may be deposited via PCVD at 780 ° C. The use of the oxi-nitride layer leads to greater stress reduction. One advantage of the present invention is that the capping nitride film only exists on the top of the trench, not in the peripheral circuit area.
- In the foregoing specification, the present invention has been described with reference to specific exemplary embodiments thereof. Although the invention has been described in terms of a preferred embodiment, those skilled in the art will recognize that various modifications, embodiments or variations of the invention can be practiced within the spirit and scope of the invention as set forth in the appended claims. All are considered within the sphere, spirit, and scope of the invention. The specification and drawings are, therefore, to be regarded in an illustrated rather than restrictive sense. Accordingly, it is not intended that the invention be limited except as may be necessary in view of the appended claims.
Claims (6)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/426,754 US6372573B2 (en) | 1999-10-26 | 1999-10-26 | Self-aligned trench capacitor capping process for high density DRAM cells |
JP2000327184A JP4197576B2 (en) | 1999-10-26 | 2000-10-26 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/426,754 US6372573B2 (en) | 1999-10-26 | 1999-10-26 | Self-aligned trench capacitor capping process for high density DRAM cells |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010039088A1 true US20010039088A1 (en) | 2001-11-08 |
US6372573B2 US6372573B2 (en) | 2002-04-16 |
Family
ID=23692072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/426,754 Expired - Lifetime US6372573B2 (en) | 1999-10-26 | 1999-10-26 | Self-aligned trench capacitor capping process for high density DRAM cells |
Country Status (2)
Country | Link |
---|---|
US (1) | US6372573B2 (en) |
JP (1) | JP4197576B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050093066A1 (en) * | 2001-12-27 | 2005-05-05 | Hajime Nagano | Semiconductor device using partial SOI substrate and manufacturing method thereof |
US7291541B1 (en) * | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US20140131802A1 (en) * | 2011-10-03 | 2014-05-15 | International Business Machines Corporation | Structure and Method to Form Passive Devices in ETSOI Process Flow |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW522507B (en) * | 2001-10-29 | 2003-03-01 | Winbond Electronics Corp | Manufacturing method of semiconductor having trenched capacitor |
JP2004039734A (en) * | 2002-07-01 | 2004-02-05 | Fujitsu Ltd | Method of forming element separating film |
US6700154B1 (en) | 2002-09-20 | 2004-03-02 | Lattice Semiconductor Corporation | EEPROM cell with trench coupling capacitor |
DE10334547B4 (en) * | 2003-07-29 | 2006-07-27 | Infineon Technologies Ag | A manufacturing method for a trench capacitor with an insulation collar, which is electrically connected on one side to a substrate via a buried contact |
US11276767B2 (en) | 2017-03-15 | 2022-03-15 | International Business Machines Corporation | Additive core subtractive liner for metal cut etch processes |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916524A (en) | 1987-03-16 | 1990-04-10 | Texas Instruments Incorporated | Dram cell and method |
US5014099A (en) | 1988-05-26 | 1991-05-07 | Texas Instruments Incorporated | Dynamic RAM cell with trench capacitor and trench transistor |
US4927779A (en) | 1988-08-10 | 1990-05-22 | International Business Machines Corporation | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor |
US5466636A (en) * | 1992-09-17 | 1995-11-14 | International Business Machines Corporation | Method of forming borderless contacts using a removable mandrel |
JP2791260B2 (en) | 1993-03-01 | 1998-08-27 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5360758A (en) * | 1993-12-03 | 1994-11-01 | International Business Machines Corporation | Self-aligned buried strap for trench type DRAM cells |
JPH07245343A (en) | 1994-03-03 | 1995-09-19 | Toshiba Corp | Semiconductor device and its manufacture |
US5543348A (en) | 1995-03-29 | 1996-08-06 | Kabushiki Kaisha Toshiba | Controlled recrystallization of buried strap in a semiconductor memory device |
US5643823A (en) | 1995-09-21 | 1997-07-01 | Siemens Aktiengesellschaft | Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures |
US6008104A (en) * | 1998-04-06 | 1999-12-28 | Siemens Aktiengesellschaft | Method of fabricating a trench capacitor with a deposited isolation collar |
US6074909A (en) * | 1998-07-31 | 2000-06-13 | Siemens Aktiengesellschaft | Apparatus and method for forming controlled deep trench top isolation layers |
US6143599A (en) * | 1998-09-29 | 2000-11-07 | Infineon Technologies North America Corp. | Method for manufacturing memory cell with trench capacitor |
-
1999
- 1999-10-26 US US09/426,754 patent/US6372573B2/en not_active Expired - Lifetime
-
2000
- 2000-10-26 JP JP2000327184A patent/JP4197576B2/en not_active Expired - Lifetime
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050093066A1 (en) * | 2001-12-27 | 2005-05-05 | Hajime Nagano | Semiconductor device using partial SOI substrate and manufacturing method thereof |
US7112822B2 (en) * | 2001-12-27 | 2006-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device using partial SOI substrate and manufacturing method thereof |
US20060273330A1 (en) * | 2001-12-27 | 2006-12-07 | Hajime Nagano | Semiconductor device using partial SOI substrate and manufacturing method thereof |
US7439112B2 (en) | 2001-12-27 | 2008-10-21 | Kabushiki Kaisha Toshiba | Semiconductor device using partial SOI substrate and manufacturing method thereof |
US7291541B1 (en) * | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US7745902B1 (en) | 2004-03-18 | 2010-06-29 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US20140131802A1 (en) * | 2011-10-03 | 2014-05-15 | International Business Machines Corporation | Structure and Method to Form Passive Devices in ETSOI Process Flow |
US9570466B2 (en) * | 2011-10-03 | 2017-02-14 | Globalfoundries Inc. | Structure and method to form passive devices in ETSOI process flow |
Also Published As
Publication number | Publication date |
---|---|
JP4197576B2 (en) | 2008-12-17 |
JP2001127148A (en) | 2001-05-11 |
US6372573B2 (en) | 2002-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5960297A (en) | Shallow trench isolation structure and method of forming the same | |
US6319794B1 (en) | Structure and method for producing low leakage isolation devices | |
US5945704A (en) | Trench capacitor with epi buried layer | |
US5933748A (en) | Shallow trench isolation process | |
US6018174A (en) | Bottle-shaped trench capacitor with epi buried layer | |
US6204112B1 (en) | Process for forming a high density semiconductor device | |
JP3466938B2 (en) | Semiconductor memory device and method of manufacturing the same | |
US6204140B1 (en) | Dynamic random access memory | |
US6309924B1 (en) | Method of forming self-limiting polysilicon LOCOS for DRAM cell | |
EP0644591B1 (en) | Trench capacitor cell structure of dram | |
US6265741B1 (en) | Trench capacitor with epi buried layer | |
US20060228864A1 (en) | Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using Epi-Si growth process | |
EP0656656A2 (en) | Integrated interconnect for very high density DRAMS | |
US6358812B1 (en) | Methods of forming storage capacitors | |
US20050158961A1 (en) | Trench capacitor with buried strap | |
US5792685A (en) | Three-dimensional device layout having a trench capacitor | |
US5753551A (en) | Memory cell array with a self-aligned, buried bit line | |
US20030020110A1 (en) | Method of preparing buried locos collar in trench drams | |
US6872629B2 (en) | Method of forming a memory cell with a single sided buried strap | |
US6300172B1 (en) | Method of field isolation in silicon-on-insulator technology | |
US7118956B2 (en) | Trench capacitor and a method for manufacturing the same | |
US6372573B2 (en) | Self-aligned trench capacitor capping process for high density DRAM cells | |
US6677197B2 (en) | High aspect ratio PBL SiN barrier formation | |
US6404000B1 (en) | Pedestal collar structure for higher charge retention time in trench-type DRAM cells | |
US6964898B1 (en) | Method for fabricating deep trench capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AOKI, MASAMI;INOUE, HIROFUMI;REEL/FRAME:010563/0248;SIGNING DATES FROM 20000131 TO 20000204 Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PORTH, BRUCE W.;LEVY, MAX G.;NASTASI, VICTOR R.;AND OTHERS;REEL/FRAME:010563/0273;SIGNING DATES FROM 20000106 TO 20000107 |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
FEPP | Fee payment procedure |
Free format text: PETITION RELATED TO MAINTENANCE FEES FILED (ORIGINAL EVENT CODE: PMFP); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PETITION RELATED TO MAINTENANCE FEES GRANTED (ORIGINAL EVENT CODE: PMFG); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees | ||
REIN | Reinstatement after maintenance fee payment confirmed | ||
PRDP | Patent reinstated due to the acceptance of a late maintenance fee |
Effective date: 20140604 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140416 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
SULP | Surcharge for late payment | ||
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |