US20010038362A1 - Auxiliary deflection winding driver disabling arrangement - Google Patents
Auxiliary deflection winding driver disabling arrangement Download PDFInfo
- Publication number
- US20010038362A1 US20010038362A1 US09/409,492 US40949299A US2001038362A1 US 20010038362 A1 US20010038362 A1 US 20010038362A1 US 40949299 A US40949299 A US 40949299A US 2001038362 A1 US2001038362 A1 US 2001038362A1
- Authority
- US
- United States
- Prior art keywords
- correction data
- memory
- data
- beam landing
- deflection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/16—Picture reproducers using cathode ray tubes
- H04N9/28—Arrangements for convergence or focusing
Definitions
- the displayed image in, for example, a direct view video display or in a projection video display having a cathode ray tube (CRT), may suffer from beam landing location errors such as geometrical and misconvergence errors. It is known to correct such errors for a CRT using a digital dynamic convergence arrangement. Correction data stored in a memory are applied via a digital-to-analog (D/A) converter and a power amplifier to, for example, an auxiliary convergence winding. The amount of correction may vary dynamically in a given deflection cycle, in accordance with the location of the beam on the display screen.
- D/A digital-to-analog
- correction data are stored in a non-volatile memory that retains the correction data even when it is not energized.
- the correction data stored in the non-volatile memory are read out and stored in a volatile memory.
- the data stored in the volatile memory are successively read out and applied via a D/A converter to an auxiliary convergence winding.
- Non-transient alteration of the correction data may occur in the non-volatile memory, as well as in the volatile memory, because of energy released in the event of a CRT arc discharge.
- the non-transient data alteration might occur when the arc discharge occurred simultaneously with the reading out of the correction data from the non-volatile memory.
- each convergence data word includes a parity bit derived by check summing the data in the word that is read out of the volatile memory.
- the parity bit is used to sense data bit error in the read out data.
- a parity checking detector is used to calculate the parity bit using the present read out data bits from the volatile memory.
- a video display deflection apparatus includes an arrangement for generating a deflection field in a cathode ray tube to vary a beam landing location of an electron beam of the cathode ray tube.
- a source of beam landing error correction data that are applied to the deflection field generating arrangement is provided for varying the deflection field by a variable amount that varies in accordance with the varying beam landing location.
- a disabling arrangement is coupled in a signal path of the beam landing error correction data for decoupling the beam landing error correction data from the deflection field generating arrangement to prevent the beam landing error correction data from varying said deflection field when abnormal operation conditions occur.
- FIGURE illustrates, in a block diagram form, a deflection system of a projection television receiver, embodying an inventive feature.
- FIG. 1 illustrates, in block diagram form, a deflection system 100 of a projection television receiver capable of multi-scan frequency operation.
- Deflection system 100 provides digital dynamic convergence, in accordance with an inventive feature.
- Three cathode ray tubes (CRT's), R, G and B form a combined image 800 on a screen 700 .
- the deflection field in each CRT is controlled in a similar way.
- CRT G is equipped with a horizontal deflection coil driven by a horizontal deflection output stage 600 and with a vertical deflection coil driven by a vertical deflection amplifier 650 , conventionally constructed.
- CRT G is also depicted with an auxiliary horizontal convergence coil 615 driven by a horizontal convergence amplifier 610 and with an auxiliary vertical convergence coil 665 driven by a vertical convergence amplifier 660 , conventionally constructed.
- An digital-to-analog (D/A) converter 311 produces a differential output on a conductor 311 b and on a conductor 311 c .
- D/A converter 311 generates a current I 1 on conductor 311 b.
- Current I 1 is equal to a reference value REF plus an analog current derived from a digital beam landing error correction data word 311 a.
- D/A converter 311 generates a current 12 on conductor 311 c .
- Current 12 is equal to reference value REF minus an analog current derived from digital beam landing error correction data word 311 a.
- Conductors 311 b and 311 c are coupled to inverting and to non-inverting input terminals, respectively, of a differential preamplifier 900 .
- An output terminal 901 of amplifier 900 is coupled via a resistor 902 to a collector of a protection transistor 903 and to amplifier 610 and drives it with an analog signal derived from a digital beam landing error correction data word 311 a.
- a D/A converter 312 is coupled to amplifier 660 and drives it with an analog signal derived from a digital beam landing error correction data word 312 a.
- Words 311 a and words 312 a are read out of a memory 305 via a controller or control logic circuit 301 , in a conventional manner.
- Memory 305 forming a volatile memory space has a sufficiently fast access time for fetching successive words as the beam landing location varies on screen 700 to provide for dynamic convergence.
- An electrically erasable programmable memory (EEPROM) 550 forming a first non-volatile memory space and containing digital beam landing error correction data words 550 a is coupled to control logic circuit 301 via a bus 550 b.
- Memory 550 includes, for example, four 2K byte memory spaces, not shown, for providing words 311 a and 312 a. The four 2K byte memory spaces are used, when stage 600 operates in a selectable horizontal scan frequency, 1 H, 2H, 2.14H or 2.4H, respectively, where H is equal to 15,734 Hz.
- data words 550 a are read out of memory 550 , and transferred via logic circuit 301 to memory 305 .
- the duplicates of data words 550 a are stored in memory 305 .
- memory 305 contains the required values of digital beam landing error correction data words 311 a and 312 a for providing dynamic convergence, as explained before.
- a convergence microprocessor 900 is coupled via an I 2 C bus 900 b isolated from bus 550 b and mastered by microprocessor 900 .
- Microprocessor 900 controls logic circuit 301 for providing required control and data transfer functions associated with control logic circuit 301 .
- a back-up, non-volatile EEPROM 250 forming a second non-volatile memory space and containing factory adjusted digital beam landing error correction data words 250 a is coupled to convergence microprocessor 900 via a bus 250 b that is, advantageously, isolated from each of bus 550 b and bus 900 b .
- Data words 250 a can be read out of EEPROM 250 , transferred via microprocessor 900 and logic circuit 301 to memory 305 and, their duplicates stored in memory 550 .
- Convergence microprocessor 900 is controlled by a main chassis microprocessor 950 via an I 2 C bus 951 that additionally serves various receiver sub systems.
- correction data words 550 a might occur in memory 550 because of the energy released in the arc discharge. Alteration of the correction data words might occur also in memory 305 .
- the data alteration in memory 550 seemed to happen intermittently when the arc discharge and the read out of the correction data words 550 a from memory 550 occur simultaneously. Whereas, no data alteration has occurred when, during the occurrence of the arc discharge, data words are not simultaneously read out from memory 550 .
- a data error correction procedure embodying an inventive feature, is employed for substituting the error containing data in memory 550 with data free of errors.
- Each convergence data word 311 a and 312 a read out of memory 305 has a parity bit, not shown, derived by check summing the data in the word that are read out from memory 305 , during, for example, factory set up. These parity bits are used to sense a data error in each of read out data words 311 a and 312 a.
- a parity checking detector 200 is used to calculate the parity bits using the present read out data words 311 a and 312 a from memory 305 .
- a parity flag bit 701 is set in logic circuit 301 .
- Flag bit 701 is monitored by convergence microprocessor 900 . Chassis microprocessor 950 checks the status of flag bit 701 via microprocessor 900 , for example, every 5 seconds.
- control logic circuit 301 If flag bit 701 has been set and also during an interval, when power is first applied to deflection system 100 , control logic circuit 301 generates a control signal 904 that disables currents I 1 and I 2 to make each equal to zero regardless of the value of word 311 a. Additionally, control logic circuit 301 generates a control signal 906 that turns on transistor 903 to decouple data words 311 a from amplifier 610 . Thereby, any excessive transient condition at an output of amplifier 610 is, advantageously, prevented. On the other hand, during normal operation, transistor 903 is turned off and currents I 1 and I 2 vary in accordance with words 311 a. Similar protection arrangement is provided with respect to amplifier 660 .
- data words 250 a stored in memory 250 are automatically read out and transferred to memory 305 .
- Data words 250 a in memory 250 are parity error free because, during the aforementioned arc discharge, no read out process occurs simultaneously in memory 250 .
- updated data words 311 a and 312 a in memory 305 are identical to those obtained, during factory set up.
- a more acceptable image quality on screen 700 is obtained.
- duplicate data words to those stored in memory 250 are transferred to memory 550 .
- data words 550 a in memory 550 also become parity error free.
- Re-adjustment of correction data words 550 a in memory 550 may be required, for example, after the set has been relocated to a geographical location having a different value of the earth magnetic field from which existed, during factory set up.
- An alignment procedure may be employed when the set is serviced, during field service, or under user control for re-adjusting the data stored in memory 550 .
- the words stored in memory 250 are used both for running the alignment procedure and for producing error free correction data words 550 a in memory 550 , as explained before.
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Video Image Reproduction Devices For Color Tv Systems (AREA)
Abstract
Description
- The displayed image in, for example, a direct view video display or in a projection video display having a cathode ray tube (CRT), may suffer from beam landing location errors such as geometrical and misconvergence errors. It is known to correct such errors for a CRT using a digital dynamic convergence arrangement. Correction data stored in a memory are applied via a digital-to-analog (D/A) converter and a power amplifier to, for example, an auxiliary convergence winding. The amount of correction may vary dynamically in a given deflection cycle, in accordance with the location of the beam on the display screen.
- In a video display, embodying an inventive feature, correction data are stored in a non-volatile memory that retains the correction data even when it is not energized. Upon power turn on, for example, the correction data stored in the non-volatile memory are read out and stored in a volatile memory. During each deflection cycle, the data stored in the volatile memory are successively read out and applied via a D/A converter to an auxiliary convergence winding.
- Non-transient alteration of the correction data may occur in the non-volatile memory, as well as in the volatile memory, because of energy released in the event of a CRT arc discharge. The non-transient data alteration might occur when the arc discharge occurred simultaneously with the reading out of the correction data from the non-volatile memory.
- In carrying out an inventive feature, each convergence data word includes a parity bit derived by check summing the data in the word that is read out of the volatile memory. The parity bit is used to sense data bit error in the read out data. A parity checking detector is used to calculate the parity bit using the present read out data bits from the volatile memory. When a parity error is detected, an output and/or an input of a convergence amplifier is actively disabled to prevent a disturbance of a screen of the CRT.
- A video display deflection apparatus, embodying an inventive feature, includes an arrangement for generating a deflection field in a cathode ray tube to vary a beam landing location of an electron beam of the cathode ray tube. A source of beam landing error correction data that are applied to the deflection field generating arrangement is provided for varying the deflection field by a variable amount that varies in accordance with the varying beam landing location. A disabling arrangement is coupled in a signal path of the beam landing error correction data for decoupling the beam landing error correction data from the deflection field generating arrangement to prevent the beam landing error correction data from varying said deflection field when abnormal operation conditions occur.
- The sole FIGURE illustrates, in a block diagram form, a deflection system of a projection television receiver, embodying an inventive feature.
- The sole FIGURE illustrates, in block diagram form, a
deflection system 100 of a projection television receiver capable of multi-scan frequency operation.Deflection system 100 provides digital dynamic convergence, in accordance with an inventive feature. Three cathode ray tubes (CRT's), R, G and B form a combinedimage 800 on ascreen 700. The deflection field in each CRT is controlled in a similar way. For example, CRT G is equipped with a horizontal deflection coil driven by a horizontaldeflection output stage 600 and with a vertical deflection coil driven by avertical deflection amplifier 650, conventionally constructed. CRT G is also depicted with an auxiliaryhorizontal convergence coil 615 driven by ahorizontal convergence amplifier 610 and with an auxiliaryvertical convergence coil 665 driven by avertical convergence amplifier 660, conventionally constructed. - An digital-to-analog (D/A)
converter 311 produces a differential output on a conductor 311 b and on a conductor 311 c. D/A converter 311 generates a current I1 on conductor 311 b. Current I1 is equal to a reference value REF plus an analog current derived from a digital beam landing errorcorrection data word 311 a. Similarly, D/A converter 311 generates a current 12 on conductor 311 c. Current 12 is equal to reference value REF minus an analog current derived from digital beam landing errorcorrection data word 311 a. - Conductors311 b and 311 c are coupled to inverting and to non-inverting input terminals, respectively, of a
differential preamplifier 900. Anoutput terminal 901 ofamplifier 900 is coupled via a resistor 902 to a collector of a protection transistor 903 and to amplifier 610 and drives it with an analog signal derived from a digital beam landing errorcorrection data word 311 a. Similarly, a D/A converter 312 is coupled toamplifier 660 and drives it with an analog signal derived from a digital beam landing errorcorrection data word 312 a. - During the deflection cycle,
Words 311 a andwords 312 a are read out of amemory 305 via a controller orcontrol logic circuit 301, in a conventional manner.Memory 305 forming a volatile memory space has a sufficiently fast access time for fetching successive words as the beam landing location varies onscreen 700 to provide for dynamic convergence. - An electrically erasable programmable memory (EEPROM)550 forming a first non-volatile memory space and containing digital beam landing error
correction data words 550 a is coupled tocontrol logic circuit 301 via abus 550 b.Memory 550 includes, for example, four 2K byte memory spaces, not shown, for providingwords stage 600 operates in a selectable horizontal scan frequency, 1 H, 2H, 2.14H or 2.4H, respectively, where H is equal to 15,734 Hz. - During a mode set up occurring as part of a power up procedure or when a change of, for example, a horizontal scan frequency in horizontal
deflection output stage 600 is required,data words 550 a are read out ofmemory 550, and transferred vialogic circuit 301 tomemory 305. Thus, the duplicates ofdata words 550 a are stored inmemory 305. Thereafter,memory 305 contains the required values of digital beam landing errorcorrection data words - A
convergence microprocessor 900 is coupled via an I2C bus 900 b isolated frombus 550 b and mastered bymicroprocessor 900.Microprocessor 900controls logic circuit 301 for providing required control and data transfer functions associated withcontrol logic circuit 301. - A back-up, non-volatile EEPROM250 forming a second non-volatile memory space and containing factory adjusted digital beam landing error
correction data words 250 a is coupled toconvergence microprocessor 900 via abus 250 b that is, advantageously, isolated from each ofbus 550b andbus 900 b.Data words 250 a can be read out of EEPROM 250, transferred viamicroprocessor 900 andlogic circuit 301 tomemory 305 and, their duplicates stored inmemory 550.Convergence microprocessor 900 is controlled by amain chassis microprocessor 950 via an I2C bus 951 that additionally serves various receiver sub systems. - In a factory set up procedure,
screen 700 is viewed by a camera, not shown. Convergence error correction data words are stored inmemory 305 and are adjusted until the displayed image meets tight screen position specifications. Duplicates of the data inmemory 305 are then written to each of EEPROMs 550 and 250. - During CRT G arc discharge, non-transient alteration of
correction data words 550 a might occur inmemory 550 because of the energy released in the arc discharge. Alteration of the correction data words might occur also inmemory 305. The data alteration inmemory 550 seemed to happen intermittently when the arc discharge and the read out of thecorrection data words 550 a frommemory 550 occur simultaneously. Whereas, no data alteration has occurred when, during the occurrence of the arc discharge, data words are not simultaneously read out frommemory 550. A data error correction procedure, embodying an inventive feature, is employed for substituting the error containing data inmemory 550 with data free of errors. - Each
convergence data word memory 305 has a parity bit, not shown, derived by check summing the data in the word that are read out frommemory 305, during, for example, factory set up. These parity bits are used to sense a data error in each of read outdata words parity checking detector 200 is used to calculate the parity bits using the present read outdata words memory 305. When a parity error is detected, aparity flag bit 701 is set inlogic circuit 301.Flag bit 701 is monitored byconvergence microprocessor 900.Chassis microprocessor 950 checks the status offlag bit 701 viamicroprocessor 900, for example, every 5 seconds. - In carrying out an inventive feature, If
flag bit 701 has been set and also during an interval, when power is first applied todeflection system 100,control logic circuit 301 generates a control signal 904 that disables currents I1 and I2 to make each equal to zero regardless of the value ofword 311 a. Additionally,control logic circuit 301 generates a control signal 906 that turns on transistor 903 to decoupledata words 311 a fromamplifier 610. Thereby, any excessive transient condition at an output ofamplifier 610 is, advantageously, prevented. On the other hand, during normal operation, transistor 903 is turned off and currents I1 and I2 vary in accordance withwords 311 a. Similar protection arrangement is provided with respect toamplifier 660. - Additionally, if
flag bit 701 has been set, because of detected parity bit error,data words 250 a stored inmemory 250 are automatically read out and transferred tomemory 305.Data words 250 a inmemory 250 are parity error free because, during the aforementioned arc discharge, no read out process occurs simultaneously inmemory 250. Thus, updateddata words memory 305 are identical to those obtained, during factory set up. As a result, advantageously, a more acceptable image quality onscreen 700 is obtained. Thereafter, duplicate data words to those stored inmemory 250 are transferred tomemory 550. As a result,data words 550 a inmemory 550 also become parity error free. - Re-adjustment of
correction data words 550 a inmemory 550 may be required, for example, after the set has been relocated to a geographical location having a different value of the earth magnetic field from which existed, during factory set up. An alignment procedure may be employed when the set is serviced, during field service, or under user control for re-adjusting the data stored inmemory 550. Advantageously, the words stored inmemory 250 are used both for running the alignment procedure and for producing error freecorrection data words 550 a inmemory 550, as explained before.
Claims (2)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/409,492 US6369780B2 (en) | 1999-09-30 | 1999-09-30 | Auxiliary deflection winding driver disabling arrangement |
DE60006565T DE60006565T2 (en) | 1999-09-30 | 2000-09-29 | DRIVER LOCKING ARRANGEMENT FOR ADDITIONAL DEFLECTION |
JP2001527571A JP2003529970A (en) | 1999-09-30 | 2000-09-29 | Apparatus for disabling auxiliary deflection winding exciter |
PCT/EP2000/009578 WO2001024534A1 (en) | 1999-09-30 | 2000-09-29 | Auxiliary deflection winding driver disabling arrangement |
AU75241/00A AU7524100A (en) | 1999-09-30 | 2000-09-29 | Auxiliary deflection winding driver disabling arrangement |
CNB00813653XA CN1171463C (en) | 1999-09-30 | 2000-09-29 | Auxiliary deflection winding driver disabling arrangement |
EP00964257A EP1216577B1 (en) | 1999-09-30 | 2000-09-29 | Auxiliary deflection winding driver disabling arrangement |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/409,492 US6369780B2 (en) | 1999-09-30 | 1999-09-30 | Auxiliary deflection winding driver disabling arrangement |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010038362A1 true US20010038362A1 (en) | 2001-11-08 |
US6369780B2 US6369780B2 (en) | 2002-04-09 |
Family
ID=23620722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/409,492 Expired - Fee Related US6369780B2 (en) | 1999-09-30 | 1999-09-30 | Auxiliary deflection winding driver disabling arrangement |
Country Status (7)
Country | Link |
---|---|
US (1) | US6369780B2 (en) |
EP (1) | EP1216577B1 (en) |
JP (1) | JP2003529970A (en) |
CN (1) | CN1171463C (en) |
AU (1) | AU7524100A (en) |
DE (1) | DE60006565T2 (en) |
WO (1) | WO2001024534A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6743273B2 (en) | 2000-09-05 | 2004-06-01 | Donaldson Company, Inc. | Polymer, polymer microfiber, polymer nanofiber and applications including filter structures |
KR100766970B1 (en) * | 2001-05-11 | 2007-10-15 | 삼성전자주식회사 | Data setting up system for displayer and control methode the same |
WO2004054236A1 (en) * | 2002-12-06 | 2004-06-24 | Koninklijke Philips Electronics N.V. | Drive apparatus for frame deflection and method |
US9993992B2 (en) | 2015-04-17 | 2018-06-12 | Fyfe Co. Llc | Structural fabric useful for lining pipe |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4365305A (en) * | 1981-01-05 | 1982-12-21 | Western Electric Company, Inc. | Vector generator for computer graphics |
US4388619A (en) * | 1981-06-30 | 1983-06-14 | International Business Machines Corporation | Corrector for bundle deflection distortion in multibeam cathode ray tubes |
US4422019A (en) | 1982-07-12 | 1983-12-20 | Tektronix, Inc. | Apparatus for providing vertical as well as horizontal smoothing of convergence correction signals in a digital convergence system |
FR2546016B1 (en) | 1983-05-11 | 1986-12-05 | Thomson Csf | LEVEL CORRECTION METHOD AND DEVICE FOR A TELEVISION IMAGE |
US4670772A (en) * | 1984-12-28 | 1987-06-02 | Rca Corporation | Raster distortion correction for progressive scan television system |
JP3035912B2 (en) | 1988-10-14 | 2000-04-24 | ソニー株式会社 | Image display correction waveform data generator |
US5194783A (en) | 1991-01-25 | 1993-03-16 | Hitachi, Ltd. | Display apparatus based on a digital convergence scheme |
DE4137131C2 (en) | 1991-11-12 | 2003-06-26 | Thomson Brandt Gmbh | Method and device for raster correction |
JP3050986B2 (en) | 1992-02-26 | 2000-06-12 | 株式会社日立製作所 | Digital convergence correction apparatus, image display apparatus using the same, and method and apparatus for creating convergence correction data |
DE4214317A1 (en) | 1992-05-04 | 1993-11-11 | Thomson Brandt Gmbh | Control method and device |
JPH05344514A (en) | 1992-06-08 | 1993-12-24 | Sanyo Electric Co Ltd | Image display device |
CA2107156C (en) | 1993-09-28 | 1999-05-11 | Matsushita Electric Industrial Co. Ltd. | Dynamic focusing device for cathode ray tube |
KR0130871B1 (en) | 1994-03-21 | 1998-04-21 | 김광호 | Digital conversions adjust method and equipment |
DE69618564T2 (en) * | 1995-08-29 | 2002-09-05 | Koninkl Philips Electronics Nv | COLOR DISPLAY DEVICE WITH ARRANGEMENT FOR CORRECTING LANDING ERRORS |
KR0176783B1 (en) | 1995-12-19 | 1999-05-01 | 구자홍 | Convergence compensation method of projection tv |
DE19611059A1 (en) | 1996-03-21 | 1997-09-25 | Thomson Brandt Gmbh | Process for signal acquisition in electronic devices by means of interpolation between interpolation point values |
US6014168A (en) | 1996-04-26 | 2000-01-11 | Display Laboratories, Inc. | Screen mapping of a cathode ray tube |
JP3393029B2 (en) | 1997-01-20 | 2003-04-07 | 富士通株式会社 | Display image distortion correction method for display device, distortion detection device, distortion correction device, and display device provided with the distortion correction device |
KR100242841B1 (en) | 1997-05-27 | 2000-02-01 | 윤종용 | Circuit for correcting north-south distortion of display apparatus |
KR100267729B1 (en) | 1998-04-30 | 2000-10-16 | 윤종용 | Horizontal deflection interpolation apparatus of video signal |
-
1999
- 1999-09-30 US US09/409,492 patent/US6369780B2/en not_active Expired - Fee Related
-
2000
- 2000-09-29 AU AU75241/00A patent/AU7524100A/en not_active Abandoned
- 2000-09-29 WO PCT/EP2000/009578 patent/WO2001024534A1/en active IP Right Grant
- 2000-09-29 EP EP00964257A patent/EP1216577B1/en not_active Expired - Lifetime
- 2000-09-29 CN CNB00813653XA patent/CN1171463C/en not_active Expired - Fee Related
- 2000-09-29 DE DE60006565T patent/DE60006565T2/en not_active Expired - Fee Related
- 2000-09-29 JP JP2001527571A patent/JP2003529970A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP1216577B1 (en) | 2003-11-12 |
CN1171463C (en) | 2004-10-13 |
CN1377558A (en) | 2002-10-30 |
DE60006565D1 (en) | 2003-12-18 |
US6369780B2 (en) | 2002-04-09 |
WO2001024534A1 (en) | 2001-04-05 |
JP2003529970A (en) | 2003-10-07 |
DE60006565T2 (en) | 2004-09-16 |
EP1216577A1 (en) | 2002-06-26 |
AU7524100A (en) | 2001-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5216497A (en) | Digital convergence apparatus including an extrapolating circuit | |
JP2617409B2 (en) | Error detection device for digital television equipment | |
US4320414A (en) | Adjusting device for color television camera apparatus | |
US6369780B2 (en) | Auxiliary deflection winding driver disabling arrangement | |
US6437829B1 (en) | Alignment of cathode ray tube displays using a video graphics controller | |
US6473139B1 (en) | Data error recovery for digital beam landing error correction arrangement | |
US4766355A (en) | Automatic vertical size control | |
KR0176783B1 (en) | Convergence compensation method of projection tv | |
US5847511A (en) | Automatic image rotation compensation circuit and method | |
EP1250815B1 (en) | Projection television set with parity error checking | |
MXPA00009606A (en) | Data error recovery for digital beam landing error correction device | |
US4501996A (en) | Deflection distortion correcting circuit | |
US5422847A (en) | Non-volatile memory controlling apparatus | |
US7239493B2 (en) | Method for preventing the generation of excessive high voltage | |
US6069673A (en) | CRT focus correcting method, CRT focus correcting circuit and display unit | |
JP3834990B2 (en) | Cathode ray tube display | |
US3876826A (en) | Data transmission system | |
CN101072315A (en) | Power sensor circuit | |
KR20000033083A (en) | Convergence control device and method | |
JP2002101314A (en) | Crt display device | |
JPH08307889A (en) | Automatic earth magnetism correction device | |
JP2001358964A (en) | Video output device, video output method and television receiver | |
JPH0759018A (en) | Television receiver | |
JPH0548922A (en) | Deflection distortion correcting circuit | |
JP2001309199A (en) | Video output device, video output method and television receiver |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: THOMSONCONSUMER ELECTRONICS, INC., INDIANA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLEIM, GUNTER;HEIZMANN, FRIEDRICH;RUNTZE, ALBERT;REEL/FRAME:011228/0216 Effective date: 19991220 |
|
AS | Assignment |
Owner name: THOMSON LICENSING S.A., FRANCE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:THOMSON CONSUMER ELECTRONICS INC.;REEL/FRAME:012560/0696 Effective date: 20011108 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Expired due to failure to pay maintenance fee |
Effective date: 20100409 |