MXPA00009606A - Data error recovery for digital beam landing error correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED:To recover a data error in a digital beam landing error correction device. SOLUTION:A 1st nonvolatile memory (550) stores correction data for a digital concentration device. During the processing to activate a power supply, the correction data are read from the 1st nonvolatile memory and stored in a volatile memory (305). The data stored in the volatile memory are continuously read during each deflection cycle and given to an auxiliary concentration windings (665, 615). When any parity error is detected (701) in the read data, data stored in a 2nd nonvolatile memory (250) are automatically read and transferred to the volatile memory and the 1st nonvolatile memory. The 2nd nonvolatile memory includes copies of the correction data stored in the 1st nonvolatile memory during setup in a factory and maintains the copies without any parity error.

Description

DATA ERROR RECOVERY FOR CONFIGURATION OF DIGITAL BEAM LANDING ERROR CORRECTION The invention relates to a beam landing correction configuration in a video display apparatus. BACKGROUND OF THE INVENTION The image displayed in, for example, a direct view video display or in a projection video display having a cathode ray tube may suffer beam landing location errors such as geometric and convergence errors. wrong It is known to correct such errors for a cathode ray tube using a digital dynamic convergence configuration, the correction data stored in a memory is applied via a digital-to-analog converter (D / A) and a power amplifier a, for example. , an auxiliary convergence winding. The correction amount can vary dynamically in a given cycle of deviation, in accordance with the location of the beam in the display screen. In a video display, which includes an aspect of the invention, the correction data is stored in a first non-volatile memory which retains the correction data even when it is not turned on. When turned on, for example, the correction data stored in the non-volatile memory is read and stored in a volatile memory. During each cycle of deviation, the data stored in the volatile memory is read successively and applied via a digital-to-analog converter to a winding * - '' • ". of auxiliary convergence; while the data of the non-volatile memory do not need to be read during the deviation cycle. As the data is retained in the non-volatile memory, the volatile memory does not have to retain the data when the video display is turned off. By using said memory hierarchy, the correction data can be accessed via the fastest volatile memory and are retained, when the display is off, using the slower non-volatile memory. For example, at the factory, the correction data set at the factory is stored in the non-volatile memory. The correction data set at the factory is unique for each device of the same model to compensate for production tolerances. The readjustment of the correction data may be required after the device has been relocated to a geographic location that has a different value from the Earth's magnetic field than it did during the factory installation. The readjustment of the correction data can be obtained with an automatic alignment system using photosensors. The non-transient alteration of the correction data can occur in the non-volatile memory, as well as in the volatile memory, due to the energy released in case of an arc discharge from the cathode ray tube. Non-transient data disturbance could occur when the arc discharge occurs simultaneously with the reading of the non-volatile memory correction data. While, there has not been an alteration of data of this type when the data reading process and the arc discharge do not occur simultaneously. It may be desirable to replace data containing error with valid data free of data errors in each memory. In carrying out an aspect of the invention, each convergence data word includes a parity bit derived by checksuming the data in the word that is read from the volatile memory. The parity bit is used to detect data bit error in the read data. A parity check detector is used to calculate the parity bit using the read data bits present from the volatile memory. When a parity error is detected, the data stored in a second non-volatile memory is read automatically and transferred to the volatile memory and the first non-volatile memory. The second non-volatile memory may contain a duplicate of the correction data stored in the first non-volatile memory, during factory installation. Unlike the correction data in the first non-volatile memory, the data in the second non-volatile memory is free of parity error. This is so because the data is not read from the second non-volatile memory during the activation procedure, then the reading and the release of the arc discharge energy do not coincide. Therefore, conveniently, the data containing parity error stored in the first non-volatile memory are replaced with the data provided by the second non-volatile memory that are free of parity error.

BRIEF DESCRIPTION OF THE INVENTION A video display deflection apparatus, including an aspect of the invention that generates a deflection field in a cathode ray tube to vary a beam landing location of an electron beam of the cathode ray tube . A first memory space is provided which contains beam landing error correction data. The correction data is read from the first memory space, during a given deviation cycle. The correction data is applied to a configuration that generates a deviation field to vary the deviation field in a variable amount that varies according to the location of the variable beam landing. A second memory space containing beam landing error correction data is provided. The correction data is read from the second memory space and stored in the first memory space, during a mode installation procedure. A third memory space containing beam landing error correction is provided. A bit error detector detects data bit error in the data stored in one of the first and second memory spaces. A controller is used to read beam landing error correction data of the third memory space and to store the read data of the third memory space in one of the first and second memory spaces. Data containing data bit error is replaced after the data bit error has been detected.

BRIEF DESCRIPTION OF THE DRAWINGS The only Figure illustrates in block diagram form a deflection system of a projection television receiver, which includes an aspect of the invention. DETAILED DESCRIPTION The single Figure illustrates in block diagram form a deflection system 100 of a projection television receiver capable of multi-scan frequency operation. The deflection system 100 provides digital dynamic convergence, in accordance with an aspect of the invention. Three cathode ray tubes R, G and B form a combined image 800 on a screen 700. The deflection field in each cathode ray tube is controlled in a similar manner. For example, the cathode ray tube G is equipped with a horizontal deflection coil activated by a horizontal deflection output stage 600 and with a vertical deflection coil activated by a vertical deflection amplifier 650, constructed in a conventional manner. The cathode ray tube G is also shown with an auxiliary horizontal convergence coil 615 activated by a horizontal convergence amplifier 610 and with an auxiliary vertical convergence coil 665 activated by a vertical convergence amplifier 660, constructed in a conventional manner. A digital-to-analog converter (D / A) 311 is coupled to the amplifier 610 and activates it with an analog signal derived from a digital beam landing error correction data word 311a. Similarly, a digital-to-analog converter 312 is coupled to the amplifier 660 and activates it with an analog signal derived from a digital beam landing error correction data word 312a. During the deflection cycle, the words 311a and the words 312a are read from a memory 305 via a controller or logic control circuit 301, in a conventional manner. The memory 305 forming a volatile memory space has sufficient quick access time to extract successive words as The location of the beam landing varies on the 700 screen to provide dynamic convergence. An electronically erasable programmable read-only memory (EEPROM) 550 that forms a first non-volatile memory space and contains error correction data words of digital beam landing 550a is coupled to logic control circuit 301 via a bus 550b. The memory 550 includes, for example, four memory spaces of 2k bytes, not shown, to provide the words 311a and 312a. The four memory spaces of 2k bytes are used when the step 600 operates in a selectable horizontal scanning frequency, 1H, 2H, 2.14H or 2.4H, respectively, where H equals 15.734 Hz. During an installation so that it occurs as part of an energy activation procedure or when a change is required , for example, a horizontal scan frequency in the horizontal deviation output stage 600, the data words 550a are read from the memory 550, and are transferred via the logic control circuit 301 to the memory 305. Therefore, the duplicates of the data words 550a are stored in the memory 305. Subsequently, the memory 305 contains the values required for digital beam landing error correction data words 311a and 312a to provide dynamic convergence, as explained above. A convergence microprocessor 900 is coupled via a bus l2C 900b isolated from the bus 550b and driven by the convergence microprocessor 900. The convergence microprocessor 900 controls the logic control circuit 301 to provide the required control and the associated data transfer functions with logic control circuit 301. As a backup, electronically non-volatile programmable and erasable read-only memory 250 forming a second non-volatile memory space and containing the words of digital beam landing error correction data Factory set 250a is coupled to the convergence microprocessor 900 via a bus 250b which is conveniently isolated from each bus 550b and bus 900b. The data words 250a can be read out of the electronically erasable programmable read-only memory 250, transferred via the convergence microprocessor 900 and the logic control circuit 301 to the memory 305 and their duplicates stored in the memory 550. The convergence microprocessor 900 is controlled by a 950 main chassis microprocessor via a • iMtÉd bus l2C 951 that additionally serves several sub systems of the receiver. In a factory installation procedure, the display 700 is viewed by a camera, not shown. The convergence error correction data words are stored in the memory 305 and are adjusted until the displayed image meets strict screen position specifications. Then, duplicates of the data are written into the memory 305 in each of the electronically erasable programmable read-only memories 550 and 250. During the arc discharge of the cathode ray tube G, a non-transient the correction data words 550a in the memory 550 due to the energy released in the arc discharge. The alteration of the correction data words could also occur in the memory 305. The alteration of data in the memory 500 seemed to occur intermittently when the arc discharge and the reading of the correction data words 550a of the memory 550 It happens simultaneously. While no data alteration has occurred when, during the occurrence of the arc discharge, the data words are not read simultaneously from the memory 550. A data error correction procedure, which includes an aspect of The invention is used to replace the error-containing data in the memory 550 with error-free data. Each paging of convergence data 31 1 a and 312 a read from memory 305, has a parity bit, not shown, derived by checksum of the data in the word that is read from memory 305, during, for example, the installation in the factory. These parity bits are used to detect a data error in each of the read data words 311a and 312a. A parity check detector 200 is used to calculate the parity bits used by the present read data words 311 a and 312 a of the memory 305. When a parity error is detected, a parity indicator bit 701 is set in the logic control circuit 301. The parity indicator bit 701 is monitored by the convergence microprocessor 900. The main chassis microprocessor 950 checks the state of the indicator bit 701 via the convergence microprocessor 900, for example, every 5 seconds. If a parity indicator bit 701 has been set, due to a detected parity bit error, the data words 250a, stored in the memory 250 are read automatically and transferred to the memory 305. The data words 250a in the memory 250 are free of parity error because, during the aforementioned arc discharge, a reading process does not occur simultaneously in the memory 250. Therefore, the updated data words 311a and 312a in the memory 305 are identical to those obtained during factory installation. As a result, conveniently, a more acceptable image quality is obtained on the screen 700.

Subsequently, the duplicate data words to those stored in the memory 250 are transferred to the memory 550. As a result, the data words 550a in the memory 550 are also free of parity error. The readjustment of the data words 550a in the memory 550 may be required, for example after the installation has been relocated to a geographical location having a different value from the Earth's magnetic field than it existed during the factory installation. . An alignment procedure can be employed when servicing the apparatus, during field service, or under user control to readjust the data stored in memory 550. Conveniently, words stored in memory 250 are used to perform the alignment procedure and to produce error-free correction data words 550a in memory 550, as explained above.

Claims (5)

1. CLAIMS 1. A video display deflection apparatus comprising: means (615, 665) for generating a deflection field in a cathode ray tube to vary a beam landing location of an electron beam of said ray tube cathode a first memory space (305) containing beam landing error correction data (305a) that are read from said first memory space, during a given drift cycle, and which apply to said field generation means deviation to vary such deflection field by a variable amount that varies in accordance with said beam landing location; a second memory space (550) containing beam landing error correction data (550b) that is read from said second memory space and stored in said first memory space, during a mode installation procedure; characterized by a third memory space (250) containing beam landing error correction data (250a); a bit error detector (200) for detecting data bit error in the data stored in one of said first and second memory spaces; and a controller (900) for reading said beam landing error correction data from said third memory space and for
2. saving such read data from said third memory space in one of said first and second memory spaces to replace said data containing data bit error, after said data bit error has been detected. A video display diverting apparatus according to claim 1, wherein after said data bit error (at 200) has been detected, the data in such third memory space (250) is read from said third memory space and stored in said second memory space (550) to replace said data containing data bit error in said second memory space with data that is free of data bit error.
3. 3. A video display diversion apparatus according to claim 1, wherein said data bit error is produced in the data (550a, 550b) stored in said second memory space (550) during said procedure. of mode installation, when said data is read from said second memory space and stored in said first memory space (305).
4. A video display diversion apparatus according to claim 1, wherein each of said second (550) and third (250) memory spaces is contained in a non-volatile memory.
5. 5. A video display diversion apparatus according to claim 1, wherein the stored data

   ,: ...............,. > , j > * > t,, ... ^ «^ ü6 * a.», - &? ma * MáßáaíMí¡ ~ ** m *** in said first memory space (305) are used to correct convergence errors .