US20010036700A1 - Method of fabricating cup-shape cylindrical capacitor of high density DRAMS - Google Patents
Method of fabricating cup-shape cylindrical capacitor of high density DRAMS Download PDFInfo
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- US20010036700A1 US20010036700A1 US09/551,535 US55153500A US2001036700A1 US 20010036700 A1 US20010036700 A1 US 20010036700A1 US 55153500 A US55153500 A US 55153500A US 2001036700 A1 US2001036700 A1 US 2001036700A1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000003860 storage Methods 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract 3
- 239000000463 material Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 239000005360 phosphosilicate glass Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 229910004205 SiNX Inorganic materials 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 238000001459 lithography Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 239000000376 reactant Substances 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- WRECIMRULFAWHA-UHFFFAOYSA-N trimethyl borate Chemical compound COB(OC)OC WRECIMRULFAWHA-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Definitions
- the present invention relates to a method of fabricating the capacitors of dynamic random access memory (DRAM) cells, and more particularly to the cup-shape cylindrical capacitor structure of high density DRAMs.
- DRAM dynamic random access memory
- a DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and capacitors which are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
- MOSFET metal-oxide-semiconductor field effect transistor
- bitlines and MOSFET regions which include gate oxides, gate electrodes and source/drain regions are formed on the semiconductor silicon substrate.
- a first dielectric and a second dielectric layers are sequentially deposited.
- the first dielectric layer is planarized and the first and second dielectric layers are then etched by plasma-etching to expose the source regions of the MOSFET in order to form cell contact windows of the DRAMs.
- the first polysilicon layer which is overlaying the second dielectric layer and filling into the cell contacts is formed.
- a third dielectric layer is formed overlaying the first polysilicon layer, and defined into third dielectric crowns by the conventional lithography and etching techniques.
- a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer.
- the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors. Therefore, the third dielectric crowns are removed by hydrofluoric acid (HF).
- HF hydrofluoric acid
- the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed by standard integrated circuit technologies. Therefore, the cup shape cylindrical capacitor for high density DRAM applications is accomplished.
- FIGS. 1 through 7 schematically illustrate the cross sectional view of a DRAM cell fabrication according to the present invention.
- FIG. 1 is a cross sectional representation of the DRAM cell after the second dielectric layer is formed.
- FIG. 2 is a cross sectional representation of the DRAM cell of FIG. 1 after the sidewall spacers are formed in the contact window.
- FIG. 3 is a cross sectional representation of the DRAM cell of FIG. 2 after the third dielectric layer is formed.
- FIG. 4 is a cross sectional representation of the DRAM cell of FIG. 3 after the third dielectric crown and second polysilicon layer are formed.
- FIG. 5 is a cross sectional representation of the DRAM cell of FIG. 4 after the cup-shape capacitor storage node is formed.
- FIG. 6 is a cross sectional representation of the DRAM cell of FIG. 5 after the third dielectric crown is removed.
- FIG. 7 is a cross sectional representation of the DRAM cell after the final capacitor structure is completed.
- the invention disclosed herein is directed to a method of fabricating the cup-shape cylindrical capacitor of high density DRAMs.
- the drawing figures are illustrated a partially completed integrated circuit device.
- numerous details are set forth in order to provide a thorough understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are while still achieving the results of the present invention. In other instance, well-known processing steps are not described in detail in order not unnecessarily to obscure the present invention.
- MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
- filed oxide regions 12 served for isolation are formed on a single crystalline semiconductor silicon substrates 10 to a thickness of about 3000 to 6000 Angstroms by the conventional localized oxidation of silicon (LOCOS) or shallow trench isolation (STI) techniques.
- LOC localized oxidation of silicon
- STI shallow trench isolation
- Bitlines and MOSFET regions which are usually consist of gate oxides, gates 14 , pad oxides 16 , lightly doped regions, spacers, and source/drain regions 18 are then formed.
- the gate 14 of the MOSFET is usually composed of polysilicon or polycide formed by low pressure chemical vapor deposition (LPCVD) to a thickness of about 2000 to 3500 Angstroms.
- the source/drain region 18 of the MOSFET which is formed by ion implantation technique, is preferably doped with arsenic (As 75 ) or phosphorus (p 31 ) ions, with an implantation dose of 2 E 15 to 5 E 16 cm ⁇ 2 , and an implantation energy of 30 to 80 keV.
- the first dielectric 20 and second dielectric 22 layers are continuously deposited on the silicon substrate 10 .
- the first dielectric layer 20 is usually using boronphosphosilicate glass (BPSG) which is formed by atmosphere CVD (APCVD) technique under the following conditions: a temperature is about 400° C., and a pressure is about 1.0 torr, with reactant gases of Si(C 2 H 5 O) 4 , N 2 and TMB (Tri-Methyl-Borate).
- BPSG boronphosphosilicate glass
- APCVD atmosphere CVD
- the thickness of the first dielectric layer 20 is about 3000 to 8000 Angstroms.
- the first dielectric layer 20 is planarized by thermal reflow, etchback or chemical mechanical polishing (CMP) techniques.
- CMP chemical mechanical polishing
- the first dielectric layer 20 can be natural silicate glass (NSG) formed by LPCVD under a temperature about 720° C., a pressure about 0.25 torr, with reactant gases of Si(C 2 H 5 O) 4 , N 2 O and O 2 . Even Tetra-Ethyl-Ortho Silicate (TEOS) or BPSG/NSG multilayers can also work.
- NSG natural silicate glass
- TEOS Tetra-Ethyl-Ortho Silicate
- BPSG/NSG multilayers can also work.
- the second dielectric layer 22 which serves as polysilicon etch stopper is usually using nitride (SiN x ) formed by LPCVD technique under the following conditions: a pressure is between 200 to 400 mTorr, with a temperature of about 720° C., and reactant gases SiH 2 Cl 2 and NH 3 flowing to a thickness of 200 to 1000 Angstroms.
- nitride SiN x
- reactant gases SiH 2 Cl 2 and NH 3 flowing to a thickness of 200 to 1000 Angstroms.
- the materials with high etch selectivity respect to polysilicon can also be used such as oxynitride (SiON).
- the first dielectric and second dielectric layers are partially etched to open cell contact windows 25 for the sources/drains 18 of the MOSFET by the conventional lithography and plasma-etching techniques.
- sidewall spacers 28 may be formed inside the cell contact windows.
- the plasma etching process can use magnetic enhanced reactive ion etching (MERIE), electron cyclotron etching (ECR) or reactive ion etching (RIE) methods with reactant gases such as CF 4 , CHF 3 and Ar.
- MERIE magnetic enhanced reactive ion etching
- ECR electron cyclotron etching
- RIE reactive ion etching
- the sidewall spacers 28 are usually composed of silicon dioxide such as TEOS by the LPCVD technique, followed by vertically anisotropically etching to complete the spacer formation.
- the first polysilicon layer 30 which is overlaying the second dielectric layer 22 and filling into the cell contact window 25 is deposited.
- a third dielectric layer 32 is formed overlaying the first polysilicon layer 30 as shown in FIG. 3.
- the first polysilicon layer 30 is usually formed by in-situ phosphorus doped LPCVD method under a mixture of 15% PH 3 +85% SiH 4 and 5% PH 3 +95% N 2 , at a temperature about 550° C. to obtain a thickness of between 500 to 1500 Angstroms.
- the third dielectric layer 32 is usually using BPSG which is formed by APCVD technique as described above. The thickness of the third dielectric layer 32 is about 4000 to 10000 Angstroms. Thereafter, the third dielectric layer 32 is subjected to planarize.
- the third dielectric layer 32 can be NSG, phosphosilicate glass PSG), spin on glass (SOG) or the like.
- the third dielectric layer 32 is vertically etched to form third dielectric crowns 32 A by the conventional lithography and plasma-etching techniques.
- a second polysilicon layer 34 is deposited overlaying the third dielectric crowns 32 A and first polysilicon layer 30 as shown in FIG. 4.
- the third dielectric layer 32 plasma-etching process can still use MERIE, ECR or RIE methods with reactant gases such as CF 4 , CHF 3 and Ar as described before.
- the second polysilicon layer 34 is also formed by in-situ phosphorus doped LPCVD method to a thickness of between 1000 to 2000 Angstroms. Alternatively, the second polysilicon 34 may be doped by ion implant technique.
- the first polysilicon 30 and second polysilicon 34 layers are vertically anisotropically etchback to define storage nodes of the cylindrical capacitors.
- the etchback process which is automatically stopped at the second dielectric layer 22 without damaging underlayers is usually employed MERIE method with reactant gases of Cl 2 , SF 6 and HBr.
- the third dielectric crowns 32 A are removed by wet etching such as the mixture of hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) or buffer oxide etch (BOE).
- HF hydrofluoric acid
- NH 4 F ammonium fluoride
- BOE buffer oxide etch
- a capacitor dielectric layer 36 and a third polysilicon layer 38 as top plate of the capacitor are sequentially formed by standard integrated circuit processing procedure.
- the cup shape cylindrical capacitor for high density DRAM applications is finally accomplished.
- the capacitor dielectric layer 36 is usually using nitride/oxide (NO) doublelayer or oxide/nitride/oxide (ONO) triplelayer or even tantalum oxide (Ta 2 O 5 ) material.
- the thickness of the capacitor dielectric layer 36 is about 20 to 150 Angstroms.
- the third polysilicon layer is deposited by the same method of the first polysilicon as described before.
- the thickness of the third polysilicon layer 38 is about 1000 to 2000 Angstroms.
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Abstract
A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.
Description
- (1) Field of the Invention
- The present invention relates to a method of fabricating the capacitors of dynamic random access memory (DRAM) cells, and more particularly to the cup-shape cylindrical capacitor structure of high density DRAMs.
- (2) Description of the Related Art
- A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and capacitors which are built in a semiconductor silicon substrate. There is an electrical contact between the source of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
- In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these DRAM devices have increased considerable. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 16 M bit or even 64 M bit DRAMs.
- As the sizes of the capacitors become smaller, so that the capacitance values of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing the performance problem. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
- When the capacitor is used to fabricate 16 Mbit DRAMs and beyond, increasing the capacitor surface area becomes a top priority. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. These capacitor structures can effectively increase the capacitance values of the capacitors, however, these processes are too complicated and highly fastidious. They are difficult to be practically employed for DRAM mass-production.
- Accordingly, it is a primary object of the present invention to provide a method for fabricating a DRAM cell fabrication with greater capacitance per unit area.
- It is another object of the present invention to provide a method of fabricating the stack capacitor structure of the high density DRAMs.
- It is a further object of the present invention to provide an easy and manufacturable process for high density DRAMs that can reduce the processing steps and fabrication cost.
- These objects are accomplished by the fabrication process described below.
- First, a field oxide layer for isolation is grown on the semiconductor silicon substrate by standard integrated circuit fabrication process. Then, bitlines and MOSFET regions which include gate oxides, gate electrodes and source/drain regions are formed on the semiconductor silicon substrate.
- Next, a first dielectric and a second dielectric layers are sequentially deposited. The first dielectric layer is planarized and the first and second dielectric layers are then etched by plasma-etching to expose the source regions of the MOSFET in order to form cell contact windows of the DRAMs.
- Then, the first polysilicon layer which is overlaying the second dielectric layer and filling into the cell contacts is formed. The next step is the key point of the present invention, a third dielectric layer is formed overlaying the first polysilicon layer, and defined into third dielectric crowns by the conventional lithography and etching techniques.
- Next, a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer. The first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors. Therefore, the third dielectric crowns are removed by hydrofluoric acid (HF).
- Finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed by standard integrated circuit technologies. Therefore, the cup shape cylindrical capacitor for high density DRAM applications is accomplished.
- The accompanying drawings forming a material part of this description, in which:
- FIGS. 1 through 7 schematically illustrate the cross sectional view of a DRAM cell fabrication according to the present invention.
- FIG. 1 is a cross sectional representation of the DRAM cell after the second dielectric layer is formed.
- FIG. 2 is a cross sectional representation of the DRAM cell of FIG. 1 after the sidewall spacers are formed in the contact window.
- FIG. 3 is a cross sectional representation of the DRAM cell of FIG. 2 after the third dielectric layer is formed.
- FIG. 4 is a cross sectional representation of the DRAM cell of FIG. 3 after the third dielectric crown and second polysilicon layer are formed.
- FIG. 5 is a cross sectional representation of the DRAM cell of FIG. 4 after the cup-shape capacitor storage node is formed.
- FIG. 6 is a cross sectional representation of the DRAM cell of FIG. 5 after the third dielectric crown is removed.
- FIG. 7 is a cross sectional representation of the DRAM cell after the final capacitor structure is completed.
- The invention disclosed herein is directed to a method of fabricating the cup-shape cylindrical capacitor of high density DRAMs. The drawing figures are illustrated a partially completed integrated circuit device. In the following description, numerous details are set forth in order to provide a thorough understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are while still achieving the results of the present invention. In other instance, well-known processing steps are not described in detail in order not unnecessarily to obscure the present invention.
- Referring now more particularly to FIG. 1, there is shown a portion of partially completed Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). First, filed
oxide regions 12 served for isolation are formed on a single crystallinesemiconductor silicon substrates 10 to a thickness of about 3000 to 6000 Angstroms by the conventional localized oxidation of silicon (LOCOS) or shallow trench isolation (STI) techniques. Bitlines and MOSFET regions which are usually consist of gate oxides,gates 14,pad oxides 16, lightly doped regions, spacers, and source/drain regions 18 are then formed. - The
gate 14 of the MOSFET is usually composed of polysilicon or polycide formed by low pressure chemical vapor deposition (LPCVD) to a thickness of about 2000 to 3500 Angstroms. The source/drain region 18 of the MOSFET which is formed by ion implantation technique, is preferably doped with arsenic (As75) or phosphorus (p31) ions, with an implantation dose of 2E15 to 5E16 cm−2, and an implantation energy of 30 to 80 keV. - Referring to FIG. 1 again, the first dielectric20 and second dielectric 22 layers are continuously deposited on the
silicon substrate 10. The firstdielectric layer 20 is usually using boronphosphosilicate glass (BPSG) which is formed by atmosphere CVD (APCVD) technique under the following conditions: a temperature is about 400° C., and a pressure is about 1.0 torr, with reactant gases of Si(C2H5O)4, N2 and TMB (Tri-Methyl-Borate). The thickness of the firstdielectric layer 20 is about 3000 to 8000 Angstroms. Thereafter, the firstdielectric layer 20 is planarized by thermal reflow, etchback or chemical mechanical polishing (CMP) techniques. Alternatively, The firstdielectric layer 20 can be natural silicate glass (NSG) formed by LPCVD under a temperature about 720° C., a pressure about 0.25 torr, with reactant gases of Si(C2H5O)4, N2O and O2. Even Tetra-Ethyl-Ortho Silicate (TEOS) or BPSG/NSG multilayers can also work. The seconddielectric layer 22 which serves as polysilicon etch stopper is usually using nitride (SiNx) formed by LPCVD technique under the following conditions: a pressure is between 200 to 400 mTorr, with a temperature of about 720° C., and reactant gases SiH2Cl2 and NH3 flowing to a thickness of 200 to 1000 Angstroms. Alternatively, the materials with high etch selectivity respect to polysilicon can also be used such as oxynitride (SiON). - Referring now to FIG. 2, the first dielectric and second dielectric layers are partially etched to open
cell contact windows 25 for the sources/drains 18 of the MOSFET by the conventional lithography and plasma-etching techniques. In order to ensure there is no electrically-short problem due to misalignment,sidewall spacers 28 may be formed inside the cell contact windows. - The plasma etching process can use magnetic enhanced reactive ion etching (MERIE), electron cyclotron etching (ECR) or reactive ion etching (RIE) methods with reactant gases such as CF4, CHF3 and Ar. The sidewall spacers 28 are usually composed of silicon dioxide such as TEOS by the LPCVD technique, followed by vertically anisotropically etching to complete the spacer formation.
- Referring now to FIG. 3, the
first polysilicon layer 30 which is overlaying thesecond dielectric layer 22 and filling into thecell contact window 25 is deposited. Next, athird dielectric layer 32 is formed overlaying thefirst polysilicon layer 30 as shown in FIG. 3. - The
first polysilicon layer 30 is usually formed by in-situ phosphorus doped LPCVD method under a mixture of 15% PH3+85% SiH4 and 5% PH3+95% N2, at a temperature about 550° C. to obtain a thickness of between 500 to 1500 Angstroms. Thethird dielectric layer 32 is usually using BPSG which is formed by APCVD technique as described above. The thickness of thethird dielectric layer 32 is about 4000 to 10000 Angstroms. Thereafter, thethird dielectric layer 32 is subjected to planarize. Alternatively, Thethird dielectric layer 32 can be NSG, phosphosilicate glass PSG), spin on glass (SOG) or the like. - Referring now to FIG. 4. the
third dielectric layer 32 is vertically etched to form thirddielectric crowns 32A by the conventional lithography and plasma-etching techniques. Next, asecond polysilicon layer 34 is deposited overlaying the thirddielectric crowns 32A andfirst polysilicon layer 30 as shown in FIG. 4. - The
third dielectric layer 32 plasma-etching process can still use MERIE, ECR or RIE methods with reactant gases such as CF4, CHF3 and Ar as described before. Thesecond polysilicon layer 34 is also formed by in-situ phosphorus doped LPCVD method to a thickness of between 1000 to 2000 Angstroms. Alternatively, thesecond polysilicon 34 may be doped by ion implant technique. - Referring now to FIG. 5. the
first polysilicon 30 andsecond polysilicon 34 layers are vertically anisotropically etchback to define storage nodes of the cylindrical capacitors. The etchback process which is automatically stopped at thesecond dielectric layer 22 without damaging underlayers is usually employed MERIE method with reactant gases of Cl2, SF6 and HBr. - Referring now to FIG. 6, the third
dielectric crowns 32A are removed by wet etching such as the mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F) or buffer oxide etch (BOE). The remaining of thesecond dielectric layer 22 can be removed or left as it was. Thereafter, the cup shape storage nodes which are consist of the remaining offirst polysilicon 30A andsecond polysilicon 34A layers according to the present invention are created as shown in FIG. 6. - Referring now to FIG. 7, a
capacitor dielectric layer 36 and athird polysilicon layer 38 as top plate of the capacitor are sequentially formed by standard integrated circuit processing procedure. The cup shape cylindrical capacitor for high density DRAM applications is finally accomplished. Thecapacitor dielectric layer 36 is usually using nitride/oxide (NO) doublelayer or oxide/nitride/oxide (ONO) triplelayer or even tantalum oxide (Ta2O5) material. The thickness of thecapacitor dielectric layer 36 is about 20 to 150 Angstroms. The third polysilicon layer is deposited by the same method of the first polysilicon as described before. The thickness of thethird polysilicon layer 38 is about 1000 to 2000 Angstroms. - While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.
Claims (20)
1. A method of fabricating at least one cup-shape capacitor of a DRAM cell, said method comprising the steps of:
(a) forming isolation regions and MOSFET structures on a silicon substrate, wherein said MOSFET comprises of gate oxide, gate electrode and drain/source regions;
(b) continuously forming a first dielectric and a second dielectric layers overlaying the surface of said silicon substrate;
(c) partially etching said first dielectric and said second dielectric layers to open cell contact windows for said source regions of said MOSFET;
(d) forming a first polysilicon layer overlaying said second dielectric layer and filling into said cell contact windows;
(e) forming a third dielectric layer overlaying said first polysilicon layer, and defining third dielectric crowns;
(f) depositing a second polysilicon layer overlaying said first polysilicon layer and said third dielectric crowns;
(g) anisotropically etching said second polysilicon layer to construct the storage node of said capacitor which consists of the remaining said first polysilicon and said second polysilicon;
(h) removing said third dielectric crowns.
(i) forming a capacitor dielectric layer overlaying said storage node of said capacitor; and
(j) forming a third polysilicon layer overlaying said capacitor dielectric layer as top electrode of said capacitor.
2. The method of , further comprising a step of removing the remaining of said second dielectric layer prior to the step (i) of forming a capacitor dielectric layer overlaying said storage node of said capacitor.
claim 1
3. The method of , wherein said first dielectric layer is a material selecting from the group consisting of boronphosphosilicate glass (BPSG), natural silicate glass (NSG) and Tetra-Ethyl-Ortho Silicate (TEOS).
claim 1
4. The method of , wherein said second dielectric layer is a material selecting from the group consisting of nitride (SiNx) and oxynitride (SiON).
claim 1
5. The method of , wherein said second dielectric layer has a thickness of 200 to 1000 Angstroms.
claim 1
6. The method of , wherein said third dielectric layer is a material selecting from the group consisting of BPSG, NSG, phosphosilicate glass (PSG) and spin on glass (SOG).
claim 1
7. The method of , wherein said third dielectric layer has a thickness of 4000 to 10000 Angstroms.
claim 1
8. The method of , wherein said capacitor dielectric layer is a material selecting from the group consisting of nitride/oxide (NO) doublelayer, oxide/nitride/oxide (ONO) triplelayer and tantalum oxide (Ta2O5).
claim 1
9. The method of , wherein said capacitor dielectric layer has a thickness of 20 to 150 Angstroms.
claim 1
10. The method of , wherein said third polysilicon layer has a thickness of 1000 to 2000 Angstroms.
claim 1
11. A method of forming cup shape capacitor structure, said method comprising the steps of:
(a) continuously forming a first dielectric and a second dielectric layers on a silicon substrate;
(b) partially etching said first dielectric and said second dielectric layers to open contact windows;
(c) forming a first polysilicon layer overlaying said second dielectric layer and filling into said contact windows;
(d) forming a third dielectric layer overlaying said first polysilicon layer, and defining third dielectric crowns;
(e) depositing a second polysilicon layer overlaying said first polysilicon layer and said third dielectric crowns;
(f) anisotropically etching said second polysilicon layer, the storage node of said capacitor which is consist of the remaining said first polysilicon and said second polysilicon is constructed;
(g) removing said third dielectric crowns;
(h) forming a capacitor dielectric layer overlaying said storage node of said capacitor; and
(i) forming a third polysilicon layer overlaying said capacitor dielectric layer as top electrode of said capacitor.
12. The method of , further comprising a step of removing the remaining of said second dielectric layer prior to the step (h) of forming a capacitor dielectric layer overlaying said storage node of said capacitor.
claim 11
13. The method of , wherein said first dielectric layer is a material selecting from the group consisting of BPSG, NSG and TEOS.
claim 11
14. The method of , wherein said second dielectric layer is a material selecting from the group consisting of nitride and oxynitride.
claim 11
15. The method of , wherein said second dielectric layer has a thickness of 200 to 1000 Angstroms.
claim 11
16. The method of , wherein said third dielectric layer is a material selecting from the group consisting of BPSG, NSG, PSG and SOG.
claim 11
17. The method of , wherein said third dielectric layer has a thickness of 4000 to 10000 Angstroms.
claim 11
18. The method of , wherein said capacitor dielectric layer is a material selecting from the group consisting of NO, ONO and tantalum oxide (Ta2O5).
claim 1
19. The method of , wherein said capacitor dielectric layer has a thickness of 20 to 150 Angstroms.
claim 11
20. The method of , wherein said third polysilicon layer has a thickness of 1000 to 2000 Angstroms.
claim 11
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US09/551,535 US6403418B2 (en) | 1997-05-20 | 2000-04-18 | Method of fabricating cup-shape cylindrical capacitor of high density DRAMs |
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TW086106703A TW463288B (en) | 1997-05-20 | 1997-05-20 | Manufacturing method for cup-like capacitor |
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TW86106703A | 1997-07-29 | ||
US650098A | 1998-01-14 | 1998-01-14 | |
US09/551,535 US6403418B2 (en) | 1997-05-20 | 2000-04-18 | Method of fabricating cup-shape cylindrical capacitor of high density DRAMs |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060024853A1 (en) * | 2004-07-29 | 2006-02-02 | International Busines Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
CN100390967C (en) * | 2005-03-31 | 2008-05-28 | 英飞凌科技股份公司 | Method of production of charge-trapping memory devices |
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US7247537B2 (en) * | 2003-08-18 | 2007-07-24 | Samsung Electronics Co., Ltd. | Semiconductor device including an improved capacitor and method for manufacturing the same |
KR100538098B1 (en) * | 2003-08-18 | 2005-12-21 | 삼성전자주식회사 | Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and Method for manufacturing the same |
KR100546395B1 (en) * | 2003-11-17 | 2006-01-26 | 삼성전자주식회사 | Capacitor of semiconductor device and method of manufacturing the same |
US20070037349A1 (en) * | 2004-04-30 | 2007-02-15 | Martin Gutsche | Method of forming electrodes |
DE102004021401B4 (en) * | 2004-04-30 | 2011-02-03 | Qimonda Ag | Manufacturing method for a stacked capacitor array |
DE102005042524A1 (en) * | 2005-09-07 | 2007-03-08 | Infineon Technologies Ag | Process for the production of stacked capacitors for dynamic storage cells |
JP2007208069A (en) * | 2006-02-02 | 2007-08-16 | Elpida Memory Inc | Semiconductor device and manufacturing method thereof |
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JP2769664B2 (en) * | 1992-05-25 | 1998-06-25 | 三菱電機株式会社 | Semiconductor memory device and method of manufacturing the same |
US5436187A (en) * | 1994-02-22 | 1995-07-25 | Nec Corporation | Process for fabricating a semiconductor memory device including a capacitor having a cylindrical storage node electrode |
JPH0817943A (en) * | 1994-06-30 | 1996-01-19 | Texas Instr Japan Ltd | Manufacture of semiconductor device |
US5688726A (en) * | 1994-08-03 | 1997-11-18 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating capacitors of semiconductor device having cylindrical storage electrodes |
JP2751906B2 (en) * | 1996-01-17 | 1998-05-18 | 日本電気株式会社 | Method of forming capacitive element |
US6096597A (en) * | 1997-01-31 | 2000-08-01 | Texas Instruments Incorporated | Method for fabricating an integrated circuit structure |
-
1997
- 1997-05-20 TW TW086106703A patent/TW463288B/en not_active IP Right Cessation
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2000
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060024853A1 (en) * | 2004-07-29 | 2006-02-02 | International Busines Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
US7135346B2 (en) | 2004-07-29 | 2006-11-14 | International Business Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
US20070087593A1 (en) * | 2004-07-29 | 2007-04-19 | International Business Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
US7396694B2 (en) | 2004-07-29 | 2008-07-08 | International Business Machines Corporation | Structure for monitoring semiconductor polysilicon gate profile |
CN100390967C (en) * | 2005-03-31 | 2008-05-28 | 英飞凌科技股份公司 | Method of production of charge-trapping memory devices |
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US6403418B2 (en) | 2002-06-11 |
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