US20010034828A1 - Microcode scalable processor - Google Patents
Microcode scalable processor Download PDFInfo
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- US20010034828A1 US20010034828A1 US09/109,762 US10976298A US2001034828A1 US 20010034828 A1 US20010034828 A1 US 20010034828A1 US 10976298 A US10976298 A US 10976298A US 2001034828 A1 US2001034828 A1 US 2001034828A1
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- 230000006870 function Effects 0.000 claims abstract description 42
- 238000012545 processing Methods 0.000 claims abstract description 19
- 230000004044 response Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 7
- 238000013459 approach Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Definitions
- the present invention relates generally to a processing system and more particularly to a processing system that is scalable via microcode.
- Processor architectures are utilized for a variety of functions. For example, they are utilized for media applications, for a fast fourier transfer (FFT), for a discrete cosine transform (DCT) or a finite input response (FIR) application. Conventional processor architectures are utilized to implement these functions. Each of these known architectures have problems when attempting to implement a particular function.
- FFT fast fourier transfer
- DCT discrete cosine transform
- FIR finite input response
- DSP digital signal processor
- a DSP is typically utilized to provide a specific function such as a FFT.
- the functionality of a DSP is hardware specific, that is, the register bank associated therewith is specific to a particular application and the instructions associated therewith are specific to the function. Therefore this system is not flexible enough to accommodate various functions.
- ASSP Application Specific Signal Processor
- a third approach is to provide a MMX type processor such as a Pentium processor manufactured by Intel Corporation, or a K6 processor manufactured by Advanced Micro Devices to implement a plurality of functions.
- MMX type processor such as a Pentium processor manufactured by Intel Corporation, or a K6 processor manufactured by Advanced Micro Devices to implement a plurality of functions.
- these chips are large and complex and have high memory requirements. They typically include a large cache memory that increases the overall size of the processor.
- a fourth approach is to utilize a RISC processor in conjunction with a coprocessor.
- this approach there are two different fetch streams and both processors fight for control of the bus.
- this system requires has a high memory requirement and low code density which also affects chip size.
- a final approach is to utilize a general purpose media processor.
- this type of processor requires a large register file and therefore context switching is slow.
- this approach has a large datapath, low code density and is therefore difficult to program.
- this approach is not suitable for real time applications.
- a processing system in accordance with the present invention comprises a processor and a microcode sequencer coupled to the processor.
- the microcode sequencer includes a plurality of modules and an associated pipeline if needed. Each of the modules enables a specific function based upon a selection signal from the processor.
- a system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable and synthesizable. Unlike RISC or MMX type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory or dual port memory is not required while having a higher code density for a particular application.
- FIG. 1 is a simple block diagram of a processing system in accordance with the present invention.
- FIG. 2 is a detailed block diagram of a system in accordance with the present invention.
- FIG. 3 is a block diagram of the decoder block of FIG. 2.
- FIG. 4 illustrates a microcode ROM/RAM structure in accordance with the present invention.
- the present invention relates to an improvement in a processing system.
- the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
- Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments.
- the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
- FIG. 1 is a simple block diagram of a processing system 10 in accordance with the present invention.
- the pipeline stages of the processing system 10 comprise a fetch (F) stage, a decode (D) stage, an execute (E) stage, a memory (M) stage and a writeback(W) stage.
- the processing system 10 includes a general purpose processor 12 and a microcode sequencer 14 coupled to the general purpose processor 12 .
- the microcode sequencer 14 includes a plurality of modules when enable a plurality of media functions such as a FFT, DCT, FIR or the like. A specific media function is enabled based upon a selection signal from the general purpose processor 12 .
- FIG. 2 is a detailed block diagram of a processing system 100 in accordance with the present invention.
- the processing system 100 includes a general purpose processor 102 and a microcode sequencer 104 b .
- a microcode sequencer is traditional microcode or a regular RISC like instruction stream.
- the microcode sequencer could be implemented utilizing a SRAM base media and a DSP engine.
- the DSP engine could then provide DSP/decoder like instructions.
- a bit would be enabled within the decode to enable clocking of the DSP/media engine.
- This system is a microcode scalable processing system, which includes the fetch stage, decode stage, execute stage, execution stage, memory stage and writeback stage as described with FIG. 1.
- the general purpose processor 102 operates in a conventional manner. For example, when instructions are provided to the decoder 106 via decode buffer 101 , the decoder 106 provides information to the register file (RF) 108 .
- the RF 108 provides control information to a load store register 110 .
- the load store register 110 retains information for the operation of the load store unit 112 .
- the decoder 106 provides control information to an arithmetic logic unit register 114 .
- An ALU register 114 holds information to control the ALU 116 .
- the RF 108 provides operand information to three registers 118 , 120 and 122 .
- the results of register 118 , 120 and 122 are provided to a multiply/ multiply add unit 124 .
- the results of register 120 and register 122 are provided to the ALU 116 .
- all the addresses to the E stage are provided as is shown to the data register 125 , and the data will come back in the M stage. Accordingly, if the data is a multiply instruction, the multiply unit 124 will generate the result 128 during the M stage. If the data is an ALU instruction, then the ALU 116 will generate the result during the execution stage.
- the microcode sequencer 104 allows for a very specific subroutine to be implemented to provide the particular function based upon the selection by the decoder 106 .
- the function could be an FFT subroutine, a DCT subroutine, or some other type of subroutine to implement the particular function.
- the microcode sequencer 104 includes a microcode engine 159 , which is typically RAM/ROM which receives the entry address from the decoder 106 .
- the microcode sequencer also includes a microcode instruction register 160 which receives microcode instructions from the microcode engine 159 .
- the microcode instruction register 160 in turn provides those instructions to a microcode decoder 162 .
- the microcode decoder 162 receives operands from either a register file 164 from within the microcode sequencer 104 or from a buffer or FIFO 166 which receives information from the system bus (not shown).
- the decoder 102 provides control signals to the hardware 168 of the microcode sequencer 104 .
- the hardware 168 in turn provides signals during the execute stage either to a streamlined write buffer 170 which provides this information on a bus (not shown) or provides the information directly to the general purpose processor 102 through the W stage.
- a bit in the decoder 106 is set to indicate whether the instruction from the data buffer 101 is for the general purpose processor 102 or for the microcode sequencer 104 . Accordingly, the decoder 106 dispatches an entry instruction or entry address to the microcode engine 130 within the microcode sequencer 104 and thereafter the microcode engine 130 will operate to execute the particular function.
- FIG. 3 shows the decoder 106 fetching in a preferred embodiment a 32 bit instruction. If the instruction is a normal instruction, it will be provided to the general purpose processor 102 . However, if it is an instruction for the microcode sequencer 104 , a macro instruction entry 150 is mapped to the microcode ROM entry address 150 and a select signal 163 is provided from the decoder 106 to a multiplexer 152 to select the entry address 150 . In this embodiment, the entry address 150 is then provided to the microcode engine 130 .
- the microcode engine 130 controls the hardware 168 of the microcode sequencer 104 to provide the particular function. Accordingly, the microcode engine 130 receives consecutive entries related to a particular subroutine.
- the microcode 300 includes a plurality of functions, for example, an FFT function 302 , a DCT function 304 , an FIR function 306 and a default function 308 .
- Each of the functions are initiated by a particular macro instruction entry address, and thereafter the code associated with that entry address will continue until that function is completed.
- the microcode 300 is scalable to any size depending upon the particular function that is to be implemented. Accordingly, the particular program counters for each function can be accessed until that particular instruction is completed. In so doing, the particular function can be executed.
- the microcode can therefore be tailored to a specific subroutine rather than having to have the overhead associated with the conventional processors such as the MMX processor. Since it is also configurable, based on the microcode, the system does not have to be limited to a specific function.
- the hardware 168 provides data to either a buffer which can provide data back to the register file of the general purpose processor, or provides it directly to the general purpose processor, depending on timing issues.
- a system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC and coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory or dual port memory is not required while having a higher code density for a particular application.
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Abstract
Description
- The present invention relates generally to a processing system and more particularly to a processing system that is scalable via microcode.
- Processor architectures are utilized for a variety of functions. For example, they are utilized for media applications, for a fast fourier transfer (FFT), for a discrete cosine transform (DCT) or a finite input response (FIR) application. Conventional processor architectures are utilized to implement these functions. Each of these known architectures have problems when attempting to implement a particular function.
- One conventional processor architecture comprises a digital signal processor (DSP). A DSP is typically utilized to provide a specific function such as a FFT. However, the functionality of a DSP is hardware specific, that is, the register bank associated therewith is specific to a particular application and the instructions associated therewith are specific to the function. Therefore this system is not flexible enough to accommodate various functions.
- A second approach is to implement an Application Specific Signal Processor (ASSP). This ASSP has a high gate count and is not software programmable. Accordingly, the ASSP also does not provide a low cost effective solution if the processor architecture is to implement a plurality of functions.
- A third approach is to provide a MMX type processor such as a Pentium processor manufactured by Intel Corporation, or a K6 processor manufactured by Advanced Micro Devices to implement a plurality of functions. However, these chips are large and complex and have high memory requirements. They typically include a large cache memory that increases the overall size of the processor. In addition there is no guarantee that the bandwidth for the MMX execution because an interrupt can occur in between the operation of the MMX instruction set.
- A fourth approach is to utilize a RISC processor in conjunction with a coprocessor. However, in this approach, there are two different fetch streams and both processors fight for control of the bus. In addition, this system requires has a high memory requirement and low code density which also affects chip size.
- A final approach is to utilize a general purpose media processor. However, this type of processor requires a large register file and therefore context switching is slow. In addition this approach has a large datapath, low code density and is therefore difficult to program. In addition this approach is not suitable for real time applications.
- Accordingly, what is needed is a system and method that will allow a plurality of processors to provide a variety of functions while not requiring a significant amount of processing power. The system must be easy to implement utilizing existing technologies. The present invention addresses such a need.
- A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules and an associated pipeline if needed. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable and synthesizable. Unlike RISC or MMX type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory or dual port memory is not required while having a higher code density for a particular application.
- Finally, it requires a smaller register file than a media processor, and thus context switching is faster through the general purpose processors. It does not have a big data path as a media processor. It also has higher code density and it is easier to program than a media processor application. Accordingly, a system and method in accordance with the present invention provides significant utility over existing conventional systems.
- FIG. 1 is a simple block diagram of a processing system in accordance with the present invention.
- FIG. 2 is a detailed block diagram of a system in accordance with the present invention.
- FIG. 3 is a block diagram of the decoder block of FIG. 2.
- FIG. 4 illustrates a microcode ROM/RAM structure in accordance with the present invention.
- The present invention relates to an improvement in a processing system. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
- FIG. 1 is a simple block diagram of a
processing system 10 in accordance with the present invention. The pipeline stages of theprocessing system 10 comprise a fetch (F) stage, a decode (D) stage, an execute (E) stage, a memory (M) stage and a writeback(W) stage. Theprocessing system 10 includes ageneral purpose processor 12 and amicrocode sequencer 14 coupled to thegeneral purpose processor 12. As will be discussed in detail hereinafter themicrocode sequencer 14 includes a plurality of modules when enable a plurality of media functions such as a FFT, DCT, FIR or the like. A specific media function is enabled based upon a selection signal from thegeneral purpose processor 12. - To more specifically describe the features of the present invention, refer now to FIG. 2. FIG. 2 is a detailed block diagram of a
processing system 100 in accordance with the present invention. Theprocessing system 100 includes ageneral purpose processor 102 and a microcode sequencer 104 b. What is meant by a microcode sequencer is traditional microcode or a regular RISC like instruction stream. For example, the microcode sequencer could be implemented utilizing a SRAM base media and a DSP engine. The DSP engine could then provide DSP/decoder like instructions. In this embodiment, a bit would be enabled within the decode to enable clocking of the DSP/media engine. This system is a microcode scalable processing system, which includes the fetch stage, decode stage, execute stage, execution stage, memory stage and writeback stage as described with FIG. 1. -
General Purpose Processor 102 - The
general purpose processor 102 operates in a conventional manner. For example, when instructions are provided to thedecoder 106 viadecode buffer 101, thedecoder 106 provides information to the register file (RF) 108. TheRF 108 provides control information to aload store register 110. Theload store register 110 retains information for the operation of theload store unit 112. Thedecoder 106 provides control information to an arithmeticlogic unit register 114. AnALU register 114 holds information to control the ALU 116. TheRF 108 provides operand information to threeregisters - As is seen, the results of
register add unit 124. The results of register 120 and register 122 are provided to the ALU 116. In the load store operation all the addresses to the E stage are provided as is shown to the data register 125, and the data will come back in the M stage. Accordingly, if the data is a multiply instruction, the multiplyunit 124 will generate theresult 128 during the M stage. If the data is an ALU instruction, then the ALU 116 will generate the result during the execution stage. - In addition, as has been above described, there is another path in the
processing system 100. This is the path for thedecoder 106 of thegeneral purpose processor 102 to themicrocode sequencer 104. This path is utilized for high performance or very specific requirements such as an FFT, DCT, FIR, or media DSP engine functions. -
Microcode Sequencer 104 - Accordingly, the
microcode sequencer 104 allows for a very specific subroutine to be implemented to provide the particular function based upon the selection by thedecoder 106. For example, the function could be an FFT subroutine, a DCT subroutine, or some other type of subroutine to implement the particular function. Themicrocode sequencer 104 includes amicrocode engine 159, which is typically RAM/ROM which receives the entry address from thedecoder 106. - The microcode sequencer also includes a
microcode instruction register 160 which receives microcode instructions from themicrocode engine 159. Themicrocode instruction register 160 in turn provides those instructions to a microcode decoder 162. The microcode decoder 162 receives operands from either aregister file 164 from within themicrocode sequencer 104 or from a buffer orFIFO 166 which receives information from the system bus (not shown). Thedecoder 102 provides control signals to thehardware 168 of themicrocode sequencer 104. Thehardware 168 in turn provides signals during the execute stage either to a streamlined write buffer 170 which provides this information on a bus (not shown) or provides the information directly to thegeneral purpose processor 102 through the W stage. - In a preferred embodiment, a bit in the
decoder 106 is set to indicate whether the instruction from thedata buffer 101 is for thegeneral purpose processor 102 or for themicrocode sequencer 104. Accordingly, thedecoder 106 dispatches an entry instruction or entry address to themicrocode engine 130 within themicrocode sequencer 104 and thereafter themicrocode engine 130 will operate to execute the particular function. - To describe this feature in more detail, refer now to FIG. 3. FIG. 3 shows the
decoder 106 fetching in a preferred embodiment a 32 bit instruction. If the instruction is a normal instruction, it will be provided to thegeneral purpose processor 102. However, if it is an instruction for themicrocode sequencer 104, amacro instruction entry 150 is mapped to the microcodeROM entry address 150 and a select signal 163 is provided from thedecoder 106 to amultiplexer 152 to select theentry address 150. In this embodiment, theentry address 150 is then provided to themicrocode engine 130. - Thereafter, the
microcode engine 130 controls thehardware 168 of themicrocode sequencer 104 to provide the particular function. Accordingly, themicrocode engine 130 receives consecutive entries related to a particular subroutine. - Referring now to FIG. 4 illustrates this feature in detail. As is seen in FIG. 4, the
microcode 300 includes a plurality of functions, for example, anFFT function 302, aDCT function 304, anFIR function 306 and adefault function 308. Each of the functions are initiated by a particular macro instruction entry address, and thereafter the code associated with that entry address will continue until that function is completed. As is seen, themicrocode 300 is scalable to any size depending upon the particular function that is to be implemented. Accordingly, the particular program counters for each function can be accessed until that particular instruction is completed. In so doing, the particular function can be executed. - The microcode can therefore be tailored to a specific subroutine rather than having to have the overhead associated with the conventional processors such as the MMX processor. Since it is also configurable, based on the microcode, the system does not have to be limited to a specific function. The
hardware 168 provides data to either a buffer which can provide data back to the register file of the general purpose processor, or provides it directly to the general purpose processor, depending on timing issues. - A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC and coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory or dual port memory is not required while having a higher code density for a particular application.
- Finally, it requires a smaller register file than a media processor, and thus context switching is faster through the general purpose processor. It does not have a big data path as a media processor. It also has higher code density and it is easier to program than a media processor application. Accordingly, a system and method in accordance with the present invention provides significant utility over existing conventional systems.
- Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Claims (20)
Priority Applications (3)
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US09/109,762 US6356995B2 (en) | 1998-07-02 | 1998-07-02 | Microcode scalable processor |
PCT/US1999/015111 WO2000002122A1 (en) | 1998-07-02 | 1999-07-02 | A microcode scalable processor |
EP99930870A EP1010066A1 (en) | 1998-07-02 | 1999-07-02 | A microcode scalable processor |
Applications Claiming Priority (1)
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US09/109,762 US6356995B2 (en) | 1998-07-02 | 1998-07-02 | Microcode scalable processor |
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US20010034828A1 true US20010034828A1 (en) | 2001-10-25 |
US6356995B2 US6356995B2 (en) | 2002-03-12 |
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Cited By (1)
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---|---|---|---|---|
US20050198482A1 (en) * | 2004-03-02 | 2005-09-08 | Altek Corporation | Central processing unit having a micro-code engine |
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US6438557B1 (en) * | 1999-06-23 | 2002-08-20 | Ericsson Inc. | System and method for performing context switching and rescheduling of a processor |
JP3669884B2 (en) * | 1999-11-11 | 2005-07-13 | 富士通株式会社 | Processing equipment |
AU2001243463A1 (en) | 2000-03-10 | 2001-09-24 | Arc International Plc | Memory interface and method of interfacing between functional entities |
US7206921B2 (en) * | 2003-04-07 | 2007-04-17 | Intel Corporation | Micro-operation un-lamination |
US7694110B1 (en) * | 2003-07-08 | 2010-04-06 | Globalfoundries Inc. | System and method of implementing microcode operations as subroutines |
KR100737802B1 (en) | 2004-12-30 | 2007-07-10 | 전자부품연구원 | Modular digital signal processor block and system-on-chip using thereof |
US8817035B2 (en) * | 2005-12-21 | 2014-08-26 | Nvidia Corporation | Texture pipeline context switch |
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JPS58144272A (en) | 1982-02-19 | 1983-08-27 | Sony Corp | Digital signal processor |
US4514803A (en) | 1982-04-26 | 1985-04-30 | International Business Machines Corporation | Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof |
US4870614A (en) | 1984-08-02 | 1989-09-26 | Quatse Jesse T | Programmable controller ("PC") with co-processing architecture |
IT1207346B (en) * | 1987-01-20 | 1989-05-17 | Cselt Centro Studi Lab Telecom | DISCREET DISCREET COSE COEFFI CIRCUIT FOR THE CALCULATION OF THE QUANTITIES OF NUMERICAL SIGNAL SAMPLES |
EP0442041A3 (en) * | 1990-01-18 | 1991-09-04 | National Semiconductor Corporation | Integrated digital signal processor/general purpose cpu with shared internal memory |
EP0545581B1 (en) * | 1991-12-06 | 1999-04-21 | National Semiconductor Corporation | Integrated data processing system including CPU core and parallel, independently operating DSP module |
US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
US5619665A (en) * | 1995-04-13 | 1997-04-08 | Intrnational Business Machines Corporation | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture |
US5930490A (en) | 1996-01-02 | 1999-07-27 | Advanced Micro Devices, Inc. | Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions |
US5784636A (en) * | 1996-05-28 | 1998-07-21 | National Semiconductor Corporation | Reconfigurable computer architecture for use in signal processing applications |
US5968161A (en) * | 1996-08-29 | 1999-10-19 | Altera Corporation | FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware support |
US5970254A (en) * | 1997-06-27 | 1999-10-19 | Cooke; Laurence H. | Integrated processor and programmable data path chip for reconfigurable computing |
US6105129A (en) * | 1998-02-18 | 2000-08-15 | Advanced Micro Devices, Inc. | Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction |
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- 1999-07-02 EP EP99930870A patent/EP1010066A1/en not_active Withdrawn
- 1999-07-02 WO PCT/US1999/015111 patent/WO2000002122A1/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050198482A1 (en) * | 2004-03-02 | 2005-09-08 | Altek Corporation | Central processing unit having a micro-code engine |
US20070250684A1 (en) * | 2004-03-02 | 2007-10-25 | Li-Fung Cheung | Central processing unit having a micro-code engine |
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EP1010066A1 (en) | 2000-06-21 |
US6356995B2 (en) | 2002-03-12 |
WO2000002122A1 (en) | 2000-01-13 |
WO2000002122A9 (en) | 2000-05-18 |
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