US20010027020A1 - Semiconductor device, method of fabricating the same, and sputtering apparatus - Google Patents
Semiconductor device, method of fabricating the same, and sputtering apparatus Download PDFInfo
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- US20010027020A1 US20010027020A1 US09/767,265 US76726501A US2001027020A1 US 20010027020 A1 US20010027020 A1 US 20010027020A1 US 76726501 A US76726501 A US 76726501A US 2001027020 A1 US2001027020 A1 US 2001027020A1
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- 238000004544 sputter deposition Methods 0.000 title claims abstract description 155
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 124
- 229910052751 metal Inorganic materials 0.000 claims description 124
- 239000003990 capacitor Substances 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 34
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 176
- 238000010586 diagram Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
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- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005478 sputtering type Methods 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H01L21/203—
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/225—Oblique incidence of vaporised material on substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
- C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Definitions
- Conventional capacitors known in the art include, for example, MIM (Metal-Insulator-Metal) capacitors wherein a dielectric material is sandwiched between two metal electrodes and Schottky capacitors which use Schottky barrier capacitance.
- MIM Metal-Insulator-Metal
- This method may further comprises the steps of: (f) forming a second dielectric layer at a third area over the upper surface of the semiconductor substrate within the aperture by sputtering at a third sputtering incidence direction; and (g) forming a third electrode layer at a fourth area over the upper surface of the semiconductor substrate within the aperture by sputtering at a fourth sputtering incidence direction which is different from the first to third sputtering incidence directions.
- steps (b), (c), (f) and (g) may be repeated in this order at desired times.
- a semiconductor device wherein a capacitor is formed on a chemical compound semiconductor substrate, wherein the capacitor comprises: a first electrode layer; a dielectric layer formed on the first electrode layer; and a second electrode layer formed on the dielectric layer.
- a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a target stage on which a sputtering material is set.
- the wafer stage and the target stage is installed in the sputtering chamber.
- the wafer stage comprises: a fixed stage fixed to the sputtering chamber; and a movable wafer holder holding the wafer and being free to rotate on the fixed stage, thereby making a sputtering incidence direction a desired direction.
- a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a plurality of target stages on which a sputtering material is set respectively.
- the wafer stage and the target stages is installed in the sputtering chamber, and the target stages is disposed in positions at which sputtering incidence directions with respect to an upper surface of the wafer are mutually different.
- a sputtering material set on one of the target stages is deposited over the wafer by applying a high frequency voltage between the wafer stage and the one of the target stage, thereby depositing the sputtering material over the upper surface of the wafer.
- FIG. 1A is a circuit diagram of a semiconductor device according to a first embodiment of the present invention.
- FIG. 1B partially shows an upper surface of the semiconductor device of FIG. 1A
- FIG. 1C is a cross-section taken along a line A-A′ in FIG. 1B;
- FIG. 2 is a structural diagram of a sputtering apparatus used in a process for forming a capacitor according to the present invention
- FIGS. 4A and 4B are diagrams for describing how a sputtering incidence direction is defined by an sputtering incidence angel ⁇ and an sputtering orientation angle ⁇ ;
- FIGS. 6A - 6 E are views each showing an upper surface at each step of capacitor forming process according to the first embodiment
- FIGS. 6F - 6 J are views each showing a cross-section taken along the line A-A′ shown in FIGS. 6A - 6 E;
- FIG. 7A is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.
- FIG. 7B partially shows an upper surface of the semiconductor device of FIG. 7A
- FIG. 7C is a cross-section taken along a line A-A′ in FIG. 7B;
- FIGS. 8D - 8 F are views each showing a cross-section taken along the line A-A′ shown in FIGS. 8A - 8 C.
- FIG. 1A is a circuit diagram of a semiconductor device according to a first embodiment of the present invention
- FIG. 1B partially shows an upper surface of the semiconductor device of FIG. 1A
- FIG. 1C is a cross-section taken along a line A-A′ in FIG. 1B.
- the transistors Tr 1 and Tr 2 and the capacitors C 1 and C 2 are formed on the GaAs substrate 10 . It will be understood that the resistance R is also formed on the GaAs substrate 10 , however its pattern is not shown in FIGS. 1B and 1C.
- the capacitor C 1 is a MIM capacitor of laminated construction formed by sandwiching a dielectric 3 a between a first electrode 1 a and a second electrode 2 a .
- the capacitor C 2 is a MIM capacitor of laminated construction formed by sandwiching a dielectric 3 b between a first electrode 1 b and a second electrode 2 b.
- the first electrode 1 a of the capacitor C 1 and the drain electrode 6 a of the transistor Tr 1 are connected via the contact holes 5 a and 5 e by a metal wiring 9 a .
- the second electrode 2 a of the capacitor C 1 and the gate electrode 8 b of the transistor Tr 2 are connected via the contact holes 5 b and 5 g by a metal wiring 9 b .
- the first electrode 1 b of the capacitor C 2 and the source electrode 7 a of the transistor Tr 1 are connected via the contact holes 5 c and 5 f by a metal wiring 9 c .
- the second electrode 2 b of the capacitor C 2 is connected to the grounded power supply (not shown) by a metal wiring 9 d .
- the sectional construction of the capacitor C 2 is the same as that of the capacitor C 1 shown in FIG. 1C.
- the target shutter 42 b and the wafer shutter 33 are opened, the target stages 41 a and 43 a are positively charged, the target shutters 41 b and 43 b are closed, an RF voltage is applied between a terminal 42 d of the target stage 42 a and the wafer stage 44 , and sputtering by the sputtering material 42 c is performed obliquely to the surface of the wafer 30 .
- the sputtering apparatus shown in FIG. 2 or FIG. 5 may also be a multi-chamber type including a plurality of chambers shown in FIG. 2 if necessary.
- the first metal electrode layer 11 , the lower metal electrode layer 12 and the second metal electrode layer 15 may be formed, for example, of two metal layers, titanium (Ti) and platinum (Pt) (referred to hereafter as “Ti/Pt metal”) Ti layer has a thickness of 500 [ ⁇ ], and Pt layer of a thickness of 1000 [ ⁇ ] is formed on the Ti layer. Pt also acts as a flat plate capacitor electrode, and prevents crystal mixing with the dielectric film when the dielectric film immediately above is formed by sputtering.
- a sputtering apparatus having a multi-chamber specification may be used for the sputtering as shown in FIG. 2 or FIG. 5. It should be noted that the metal electrode layer 15 a is also formed on the surface of the dielectric layer 14 a.
- This semiconductor device uses a GaAs substrate 10 . Further, FIG. 7A is the same as FIG. 1A.
- the first electrode 51 a of the capacitor C 1 is connected to the drain electrode 6 a of the transistor Tr 1 , and the second electrode 52 a of the capacitor C 1 is connected to the gate electrode 8 b of the transistor Tr 2 .
- the first electrode 51 b of the capacitor C 2 is connected to the source electrode 7 a of the transistor Tr 1 , and the second electrode 52 b of the capacitor C 2 is connected to a grounded power supply E 1 (not shown).
- the construction in section of the capacitor C 2 is the same as that of the capacitor C 1 shown in FIG. 7C.
- FIGS. 8A - 8 F are diagrams showing a process for fabricating a capacitor according to the second embodiment, wherein FIGS. 8A - 8 C show pattern upper surfaces, and FIGS. 8D - 8 F respectively show sections taken along the lines A-A′ in FIGS. 8A - 8 C.
- a mask layer 63 namely, resist pattern 63
- FIG. 8 F is formed using a photoresist of which the pattern edges have an inverted taper shape.
- a metal layer is formed by oblique sputtering where the sputtering incidence angle ⁇ lies in a range of 10 degrees to 30 degrees and the sputtering orientation angel ⁇ is 90 degrees, thereby forming the second metal electrode layer 65 in the aperture 63 a.
- This second metal electrode layer 65 overlaps with most of the surface of the first dielectric layer 64 (except for a part of the layer 64 adjacent to the first metal electrode layer 61 ), but does not overlap with the exposed surface of the first metal electrode layer 61 .
- the second metal electrode layer 65 is therefore electrically isolated from the first metal electrode layer 61 .
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Physical Vapour Deposition (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
Description
- The present invention relates to a semiconductor device having a semiconductor substrate such as a GaAs substrate and a capacitor formed thereon, a method of fabricating it, and a sputtering apparatus suited to this fabrication method.
- Conventional capacitors known in the art include, for example, MIM (Metal-Insulator-Metal) capacitors wherein a dielectric material is sandwiched between two metal electrodes and Schottky capacitors which use Schottky barrier capacitance.
- The capacitance C of a MIM capacitor may be expressed in terms of the following equation, where ∈O denotes a dielectric constant of vacuum, ∈r denotes a dielectric constant of the dielectric material, S denotes a surface area of the capacitor, and d denotes a distance between the electrodes.
- C=∈O ∈r (S/d)
- To fabricate a capacitor of high capacitance, a dielectric material of high dielectric constant ∈r may be used, the distance d between the electrodes may be reduced, or the capacitor surface area S maybe increased. However, as the use of dielectric materials of high dielectric constant is limited to certain materials, and as there is also a limit to the extent to which the distance d between the electrodes can be reduced, the chosen method is usually to increase the surface area S of the capacitor.
- However, attempts to increase the surface area S of the capacitor led to an increase of chip surface area, and this directly resulted in higher unit costs for chips.
- It is an object of the present invention to provide a semiconductor device having a high capacitance capacitor having a small surface area, to provide a method of efficiently fabricating such a semiconductor device, and to provide a sputtering apparatus suitable for this fabrication method.
- According to one aspect of the present invention, a method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
- This method may further comprises the steps of: (f) forming a second dielectric layer at a third area over the upper surface of the semiconductor substrate within the aperture by sputtering at a third sputtering incidence direction; and (g) forming a third electrode layer at a fourth area over the upper surface of the semiconductor substrate within the aperture by sputtering at a fourth sputtering incidence direction which is different from the first to third sputtering incidence directions.
- Further, in this method, the steps (b), (c), (f) and (g) may be repeated in this order at desired times.
- According to another aspect of the present invention, a semiconductor device wherein a capacitor is formed on a chemical compound semiconductor substrate, wherein the capacitor comprises: a first electrode layer; a dielectric layer formed on the first electrode layer; and a second electrode layer formed on the dielectric layer.
- According to further aspect of the present invention, a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a target stage on which a sputtering material is set. The wafer stage and the target stage is installed in the sputtering chamber. The wafer stage comprises: a fixed stage fixed to the sputtering chamber; and a movable wafer holder holding the wafer and being free to rotate on the fixed stage, thereby making a sputtering incidence direction a desired direction.
- According to still further aspect of the present invention, a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a plurality of target stages on which a sputtering material is set respectively. The wafer stage and the target stages is installed in the sputtering chamber, and the target stages is disposed in positions at which sputtering incidence directions with respect to an upper surface of the wafer are mutually different. A sputtering material set on one of the target stages is deposited over the wafer by applying a high frequency voltage between the wafer stage and the one of the target stage, thereby depositing the sputtering material over the upper surface of the wafer.
- The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
- FIG. 1A is a circuit diagram of a semiconductor device according to a first embodiment of the present invention;
- FIG. 1B partially shows an upper surface of the semiconductor device of FIG. 1A;
- FIG. 1C is a cross-section taken along a line A-A′ in FIG. 1B;
- FIG. 2 is a structural diagram of a sputtering apparatus used in a process for forming a capacitor according to the present invention;
- FIG. 3A is an enlarged view showing an upper surface of a wafer stage in the sputtering apparatus of FIG. 2;
- FIG. 3B is an enlarged view showing a longitudinal cross-section of the wafer stage in the sputtering apparatus of FIG. 2;
- FIGS. 4A and 4B are diagrams for describing how a sputtering incidence direction is defined by an sputtering incidence angel θ and an sputtering orientation angle ø;
- FIG. 5 is a structural diagram of another type of sputtering apparatus used in a process for forming a capacitor according to the present invention;
- FIGS. 6A -6E are views each showing an upper surface at each step of capacitor forming process according to the first embodiment;
- FIGS. 6F -6J are views each showing a cross-section taken along the line A-A′ shown in FIGS. 6A - 6E;
- FIG. 7A is a circuit diagram of a semiconductor device according to a second embodiment of the present invention;
- FIG. 7B partially shows an upper surface of the semiconductor device of FIG. 7A;
- FIG. 7C is a cross-section taken along a line A-A′ in FIG. 7B;
- FIGS. 8A -8C are views each showing an upper surface at each step of capacitor forming process according to the second embodiment; and
- FIGS. 8D -8F are views each showing a cross-section taken along the line A-A′ shown in FIGS. 8A - 8C.
- Preferred embodiments of the present invention will be described with reference to the accompanying drawings.
- First Embodiment
- FIG. 1A is a circuit diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 1B partially shows an upper surface of the semiconductor device of FIG. 1A, and FIG. 1C is a cross-section taken along a line A-A′ in FIG. 1B.
- This semiconductor device includes a
GaAs substrate 10. - The circuit shown in FIG. 1A includes N channel MES type transistors Tr1 and Tr2, capacitors C1 and C2, and a resistance R. The capacitor C1 is used as a condenser to cut out the D.C. component between the
drain electrode 6 a of the transistor Tr1 and thegate electrode 8 b of the transistor Tr2. The capacitor C2 is also provided in parallel with a bias resistance R between thesource electrode 7 a of the transistor Tr1 and a grounded power supply E1, and is used as a bypass capacitor. - Referring to FIGS. 1B and 1C, the transistors Tr1 and Tr2 and the capacitors C1 and C2 are formed on the
GaAs substrate 10. It will be understood that the resistance R is also formed on theGaAs substrate 10, however its pattern is not shown in FIGS. 1B and 1C. The capacitor C1 is a MIM capacitor of laminated construction formed by sandwiching a dielectric 3 a between afirst electrode 1 a and asecond electrode 2 a. The capacitor C2 is a MIM capacitor of laminated construction formed by sandwiching a dielectric 3 b between afirst electrode 1 b and asecond electrode 2 b. - A
contact hole 5 a to thefirst electrode 1 a of the capacitor C1, acontact hole 5 b to thesecond electrode 2 a of the capacitor C1, acontact hole 5 c to thefirst electrode 1 b of the capacitor C2, acontact hole 5 d to thesecond electrode 2 b of the capacitor C2, acontact hole 5 e to adrain electrode 6 a of the transistor Tr1, acontact hole 5 f to asource electrode 7 a of the transistor Tr1, and acontact hole 5 g to agate electrode 8 b of the transistor Tr2, are formed in an inter-layerinsulating film 4. Thefirst electrode 1 a of the capacitor C1 and thedrain electrode 6 a of the transistor Tr1 are connected via the contact holes 5 a and 5 e by ametal wiring 9 a. Thesecond electrode 2 a of the capacitor C1 and thegate electrode 8 b of the transistor Tr2 are connected via the contact holes 5 b and 5 g by ametal wiring 9 b. Thefirst electrode 1 b of the capacitor C2 and thesource electrode 7 a of the transistor Tr1 are connected via the contact holes 5 c and 5 f by ametal wiring 9 c. Thesecond electrode 2 b of the capacitor C2 is connected to the grounded power supply (not shown) by ametal wiring 9 d. The sectional construction of the capacitor C2 is the same as that of the capacitor C1 shown in FIG. 1C. - Next, a description of the sputtering apparatus used for the process for forming the capacitors will be given.
- FIG. 2 is a diagram showing the construction of a sputtering apparatus used in forming the capacitors. In this sputtering apparatus, sputtering can be performed at a variable, oblique incidence direction to a wafer surface (referred to hereafter as “oblique sputtering” as distinct from ordinary “vertical sputtering” where the incidence angle is perpendicular to the wafer surface). The sputtering apparatus shown in FIG. 2 includes a
target 32, awafer shutter 33 and awafer stage 34 inside achamber 31. Thetarget 32 includes atarget stage 32 a on which asputtering material 32 b is set. - FIG. 3A is an enlarged view showing an upper surface of the
wafer stage 34 in the sputtering apparatus of FIG. 2, and FIG. 3B is an enlarged view in section of the wafer stage in the sputtering apparatus of FIG. 2. Referring to FIGS. 3A and 3B, thewafer stage 34 includes a fixedstage 34 a, on the upper surface of which ahemispherical depression 34 d is formed and which is fixed to thechamber 31, amovable wafer holder 34 b having a hemispherical projection which engages with thedepression 34 d of the fixedstage 34 a, and awafer fixing ring 34 c provided on and fixed to a flat surface of themovable wafer holder 34 b. Awafer 30 is fixed to the flat surface of themovable wafer holder 34 b by thewafer fixing ring 34 c. Themovable wafer holder 34 b is fixed to the fixedstage 34 a by a fixingpin 35 such that a sputtering incidence direction with respect to the upper surface of thewafer 30 is a desired direction. - FIGS. 4A and 4B are side and plan views of the
wafer 30 for describing the sputtering incidence direction D2 relative to thewafer surface 30 a. In FIGS. 4A and 4B, the sputtering incidence direction D2 is defined by a sputtering incidence angle θ and a sputtering orientation angel ø, where the sputtering incidence angle θ denotes an angle between the normal line D1 perpendicular to thewafer surface 30 a and the sputtering incidence direction D2, and the sputtering orientation angel ø denotes an angle between a direction D3 from the center of thewafer 30 to an orientation flat OF (referred to as OF direction) and a direction D2′ obtained by projecting the direction D2 on the upper surface by a light ray parallel to the normal line D1 (i.e., an angle formed by a counterclockwise rotation from the OF direction). In the sputtering apparatus shown in FIG. 2, the sputtering orientation angel θ can be varied from 0 degrees to 90 degrees, and the sputtering orientation angel ø can be varied from 0 degrees to 360 degrees. - In the sputtering apparatus shown in FIG. 2 and FIGS. 3A and 3B, the sputtering
material 32 b is set on thetarget stage 32 a, thewafer 30 is set in themovable wafer holder 34 b by thewafer fixing ring 34 c, and themovable wafer holder 34 b is fixed at a predetermined angle using the fixingpin 35. The sputteringmaterial 32 b then is deposited by the oblique sputtering or vertical sputtering on theupper surface 30 a of thewafer 30 under a predetermined vacuum (e.g. 10-1 [torr] to 10 [torr]), supplying Ar gas at a predetermined flowrate (e.g. 1 [scam] to 30 [scam]) to thechamber 31, and applying an RF voltage of 13.56 [MHz] between thetarget stage 32 a and themovable wafer holder 34 b. - FIG. 5 is a schematic diagram of a different type of sputtering apparatus used in forming the capacitors. This is a sputtering apparatus which can change a sputtering incidence direction for allowing oblique sputtering to be performed. The sputtering apparatus shown in FIG. 5 has three
targets wafer shutter 33 and awafer stage 44 inside thechamber 31. - The three
targets target shutters wafer 30 is fixed to the surface of thewafer stage 44 by awafer fixing ring 44 a provided in thewafer stage 44. The threetarget stages target stage 41 a is set in a position where θ=0 degrees, thetarget stage 42 a is set in a position where θ=10 degrees - 30 degrees and ø=90 degrees, and thetarget stage 43 a is set in a position where θ=10 degrees - 30 degrees and ø=270 degrees. - In the sputtering apparatus of FIG. 5, a sputtering
material 41 c is set on thetarget stage 41 a, a sputteringmaterial 42 c is set on thetarget stage 42 a, a sputteringmaterial 43 c is set on thetarget stage 43 a, and awafer 30 is set on thewafer stage 44. When thetarget stage 41 is used for example, thetarget shutter 41 b and thewafer shutter 33 are opened, and the sputteringmaterial 41 c is deposited by the vertical sputtering on the upper surface of thewafer 30 under a predetermined vacuum (e.g. 10-1 [torr] to 10 [torr]), while supplying Ar gas at a predetermined flowrate to thechamber 31, and while applying an RF voltage of 13.56 [MHz] between a terminal 41 d of thetarget stage 41 a and thewafer stage 44. The target stages 42 a and 43 a are positively charged to avoid attracting ions, e.g. from the sputtering materials, and theshutters material 41 c from thetarget 41 does not adhere to thesputtering materials target 42 is used, thetarget shutter 42 b and thewafer shutter 33 are opened, the target stages 41 a and 43 a are positively charged, thetarget shutters target stage 42 a and thewafer stage 44, and sputtering by the sputteringmaterial 42 c is performed obliquely to the surface of thewafer 30. The sputtering apparatus shown in FIG. 2 or FIG. 5 may also be a multi-chamber type including a plurality of chambers shown in FIG. 2 if necessary. - FIGS. 6A -6J are diagrams showing a process for fabricating a capacitor according to the first embodiment, wherein FIGS. 6A - 6E respectively show upper surfaces, and FIGS. 6F - 6J respectively show sections taken along the lines A-A′ in FIGS. 6A - 6E. In the capacitor forming process shown in FIGS. 6A - 6J, a mask layer 13 (namely, resist pattern 13) is formed on the GaAs substrate 10 (namely, GaAs wafer 30) on which a first
metal electrode layer 11 and a lowermetal electrode layer 12 are formed. Themask layer 13 is formed using a photoresist of which the pattern edges have an inverted taper shape. Afirst dielectric layer 14, a secondmetal electrode layer 15, asecond dielectric layer 16 and a thirdmetal electrode layer 17 are formed by the different sputtering incidence directions. The OF of thewafer 30 is assumed to be in the lower part of FIGS. 6A - 6E, and in front of the paper surface in the case of FIGS. 6F - 6J. - In FIG. 6A and FIG. 6F, a first
metal electrode layer 11 and the lowermetal electrode layer 12 which are electrically isolated each other are formed on a surface of theGaAs substrate 10. The firstmetal electrode layer 11 and the lowermetal electrode layer 12 are formed, for example, by forming a metal film, by sputtering or a similar process, over the entire surface of theGaAs substrate 10, and then patterning (namely, etching) the metal layer, or by forming a metal layer film on the surface of theGaAs substrate 10 on which a photoresist pattern has been formed, and then dissolving the resist pattern to remove it. TheGaAs substrate 10 used herein may be a low dope 3 inch wafer having an impurity concentration of, for example, 1014 [cm-3] or a non-doped 3 inch wafer. - Next, a resist
pattern 13 as a mask layer having anaperture 13 a is formed by patterning using a photoresist (not shown in the figure) of which the pattern edges have an inverted taper shape. Theaperture 13 a contains an area for forming thefirst metal electrode 11 and an area for forming the lowermetal electrode layer 12. It is preferred that the taper angle of the edges of themask layer 13 subtend an angle of 10 degrees - 40 degrees at the upper surface of the substrate 10 (i.e., wafer surface). The photoresist for forming the resistpattern 13 may, for example, be a negative type photoresist (for example, brandname: FSMR). - Next, a
dielectric film 14 of a predetermined thickness (e.g. 9000 [Å] - 15000 [Å] is formed by vertical sputtering (sputtering incidence angle θ =0 degrees) on the surface of thesubstrate 10 on which the resist pattern as amask layer 13 was formed. In FIG. 6F, a sputtering incident direction is indicated by arrows IO. The resistpattern 13 acts as a mask to form this firstdielectric film 14 which overlaps with a part of the firstmetal electrode layer 11 and a part of the lowermetal electrode layer 12. - The
aforesaid dielectric film 14 may be, for example, a ferroelectric film such as silicon nitride (SiN), tantalum oxide (Ta2O5), BST (amorphous film consisting of barium, strontium, titanium and oxygen), or STO (amorphous film consisting of strontium, titanium and oxygen). Thedielectric film 14 a is also formed on the surface of the resistpattern 13. - Next, in FIG. 6B and FIG. 6G, a
metal layer 15 is formed by oblique sputtering where the sputtering angles θ=10 degrees to 30 degrees and ø=90 degrees. In FIG. 6G, a sputtering incident direction is indicated by arrows I1. This secondmetal electrode layer 15 is formed in theaperture 13 a with the resistpattern 13 acting as a mask. The secondmetal electrode layer 15 overlaps with most of the surface of the first dielectric layer 14 (except for a part of thelayer 14 adjacent to the first metal electrode layer 11) and with a part of the exposed surface of the lowermetal electrode layer 12, but does not overlap with the exposed surface of the firstmetal electrode layer 11. The secondmetal electrode layer 15 is therefore in contact with the lowermetal electrode layer 12, but is electrically isolated from the firstmetal electrode layer 11. - The first
metal electrode layer 11, the lowermetal electrode layer 12 and the secondmetal electrode layer 15 may be formed, for example, of two metal layers, titanium (Ti) and platinum (Pt) (referred to hereafter as “Ti/Pt metal”) Ti layer has a thickness of 500 [Å], and Pt layer of a thickness of 1000 [Å] is formed on the Ti layer. Pt also acts as a flat plate capacitor electrode, and prevents crystal mixing with the dielectric film when the dielectric film immediately above is formed by sputtering. In forming the aforesaid Ti/Pt metal, a sputtering apparatus having a multi-chamber specification may be used for the sputtering as shown in FIG. 2 or FIG. 5. It should be noted that themetal electrode layer 15 a is also formed on the surface of thedielectric layer 14 a. - Next, in FIG. 6C and FIG. 6H, a
second dielectric layer 16 is formed by vertical sputtering. In FIG. 6H, a sputtering incident direction is indicated by arrows I2. This seconddielectric layer 16 is formed in theaperture 13 a. Thesecond dielectric layer 16 overlaps with most of the surface of the second metal layer 15 (except for a part of thelayer 15 adjacent to the lower electrode layer 12) and with the exposed surface of thefirst dielectric layer 14. It shall be assumed that this seconddielectric layer 16 is of the same dielectric material as thefirst dielectric layer 14 and has the same film thickness. It should be noted that thedielectric layer 16 a is also formed on the surface of themetal layer 15 a. - Next, a
metal electrode layer 17 is formed by oblique sputtering where the sputtering angles θ=10 degrees to 30 degrees and ø=270 degrees. In FIG. 6G, a sputtering incident direction is indicated by arrows I3. This thirdmetal electrode layer 17 is formed in theaperture 13 a. The thirdmetal electrode layer 17 overlaps with most of the surface of thesecond dielectric layer 16 and with the exposed surface of the firstmetal electrode layer 11, but does not overlap with the exposed surfaces of the lowermetal electrode layer 12 and the second metal electrode layer. The thirdmetal electrode layer 17 is therefore in contact with the firstmetal electrode layer 11, but is electrically isolated from the lowermetal electrode layer 12. It will be assumed that this thirdmetal electrode layer 17 is of the same metal as thesecond metal electrode 15 and has the same thickness. It should be noted that themetal electrode layer 17 a is also formed on the surface of thedielectric layer 16 a. - Next, in FIG. 6D and FIG. 6I, the resist
pattern 13 is lifted off by dissolving it. The metal layers 15 a and 17 a and thedielectric layers metal electrode layer 11, the lowermetal electrode layer 12, thefirst dielectric layer 14, the secondmetal electrode layer 15, thesecond dielectric layer 16 and the thirdmetal electrode layer 17, is retained. When this capacitor is used as the capacitor C1 of FIG. 1, the firstmetal electrode layer 11 and the thirdmetal electrode layer 17 form thefirst electrode 1 a, the lowermetal electrode layer 12 and the secondmetal electrode layer 15 form thesecond electrode 2 a, and thefirst dielectric layer 14 and thesecond dielectric layer 16 form the dielectric 3 a. - Next, in FIG. 6E and FIG. 6J, an inter-layer
insulating film 18 is formed over the whole surface by plasma CVD or the like. The inter-layerinsulating film 18 may be, for example, silicon nitride (SiN) film. Acontact hole 19 a to the firstmetal electrode layer 11 and acontact hole 19 b to the lowermetal electrode layer 12 are formed in thisinter-layer insulating film 18, and connection wiring is attached through these contact holes 19 a and 19 b. When this capacitor is used as the capacitor C1 of FIG. 1, thecontact hole 19 a corresponds to thecontact hole 5 a and thecontact hole 19 b corresponds to thecontact hole 5 b. - Hence according to the first embodiment, by giving the capacitor a laminated structure having the third metal electrode layer and the second dielectric layer, the effective surface area S of the capacitor is increased. Specifically, the effective surface area S of the capacitor is increased by approximately 2 times relative to the pattern occupancy area. The capacitance of the capacitor is thereby increased by approximately 2 times for the same pattern occupancy area.
- Further, by using the resist
pattern 13 as a mask in a capacitor forming process and by varying the sputtering incidence angle in order to form each layer, thefirst dielectric layer 14, the secondmetal electrode layer 15, thesecond dielectric layer 16 and the thirdmetal electrode layer 17 are sequentially formed by sputtering. It is therefore unnecessary to perform the steps of sputtering, patterning, etching, and resist removing to form each layer as when the etching method is used, hence the process is simplified, and the capacitor can be formed efficiently. - Further, by using the sputtering apparatus shown in FIG. 2 or FIG. 5, oblique sputtering can easily be performed at any desired sputtering incidence angle.
- In the aforesaid first embodiment, a description was given in the case where the capacitor having 2 layers, however it will be understood that the number of layers is not limited to two. When a capacitor of n layers is formed, the effective surface area S of the capacitor may be increased by approximately n times relative to the pattern occupancy area, hence the capacitance of the capacitor will be n times the capacitance in the conventional case.
- Further, the capacitor was connected to an external circuit (transistors Tr1, Tr2 in FIG. 1) by connecting the metal electrodes through the contact holes formed in the inter-layer insulation film with metal wires, however the first
metal electrode layer 11 and lowermetal electrode layer 12 may also be connected to an external circuit in which case the wiring step after forming the inter-layer insulation film may be omitted. - An electrically conducting area may also be formed by ion implantation or epitaxial growth techniques in the part of the surface of the
GaAs semiconductor substrate 10 where it is desired to form the firstmetal electrode layer 11 and lowermetal electrode layer 12, and this electrically conducting area used as the first metal electrode layer and lower electrode layer. - Second Embodiment
- FIG. 7A is a circuit diagram of a semiconductor device according to a second embodiment of the present invention, FIG. 7B partially shows an upper surface of the semiconductor device of FIG. 7A, and FIG. 7C is a cross-section taken along a line A-A′ in FIG. 7B.
- This semiconductor device uses a
GaAs substrate 10. Further, FIG. 7A is the same as FIG. 1A. - In FIGS. 7B and 7C, the transistors Tr1, Tr2 and capacitors C1, C2 are formed on a
GaAs substrate 60. A resistance R is also formed on theGaAs substrate 60, but its pattern diagram is not shown. The capacitor C1 is a MIM capacitor formed by sandwiching a dielectric 53 a between afirst electrode 51 a and asecond electrode 52 a. The capacitor C2 is a MIM capacitor formed by sandwiching a dielectric 53 b between afirst electrode 2 b and asecond electrode 52 b. - The
first electrode 51 a of the capacitor C1 is connected to thedrain electrode 6 a of the transistor Tr1, and thesecond electrode 52 a of the capacitor C1 is connected to thegate electrode 8 b of the transistor Tr2. Thefirst electrode 51 b of the capacitor C2 is connected to thesource electrode 7 a of the transistor Tr1, and thesecond electrode 52 b of the capacitor C2 is connected to a grounded power supply E1 (not shown). The construction in section of the capacitor C2 is the same as that of the capacitor C1 shown in FIG. 7C. - In the capacitor C1, by applying ground potential to the
first electrode 51 a and a negative potential to thesecond electrode 52 a, the side gate effect of the transistor Tr1 disappears and deterioration of the transistor output is avoided. - Next, the formation of the capacitor according to the second embodiment will be described. In this formation process, the sputtering apparatus capable of oblique sputtering shown in FIG. 2 or FIG. 5 is used as in the first embodiment.
- FIGS. 8A -8F are diagrams showing a process for fabricating a capacitor according to the second embodiment, wherein FIGS. 8A - 8C show pattern upper surfaces, and FIGS. 8D - 8F respectively show sections taken along the lines A-A′ in FIGS. 8A - 8C. In the capacitor forming process depicted in FIG. 8, a mask layer 63 (namely, resist pattern 63) is formed using a photoresist of which the pattern edges have an inverted taper shape. A first dielectric layer, second metal electrode layer, second dielectric layer, third metal electrode layer and third dielectric layer are laminated, by using different sputtering angles, on a GaAs substrate 60 (GaAs wafer) on which is formed a first metal electrode layer connected to the
drain electrode 6 a of the transistor Tr1 of FIG. 7A. After removing the resist pattern, a fourth metal electrode layer connected to thegate electrode 8 a of the transistor Tr2 of FIG. 7 is laminated. It is assumed that the OF of the wafer is situated in the lower part of FIGS. 8A - 8C, and in front of the paper for FIGS. 8D - 8F. - In FIG. 8A and FIG. 8D, a first
metal electrode layer 61 is formed by the steps of sputtering, patterning, and etching or the steps of patterning, sputtering, and lifting-off on a surface of the GaAs substrate 60 (GaAs wafer). This firstmetal electrode layer 61 is formed so that it is connected to (overlaps with) thedrain electrode 6 a of the transistor Tr1 of FIG. 7A. TheGaAs substrate 60 may, for example, be the same as that of the first embodiment. - Next, a resist pattern63 (mask layer) having an
aperture 63 a partly comprising the area of thefirst metal electrode 61 is formed by patterning using a photoresist of which the pattern edges have an inverted taper shape, It is preferred that the edge taper angle of the resistpattern 63 relative to the wafer surface is 10 degrees to 40 degrees. The aforesaid photoresist may, for example, be the same as that used in the first embodiment. - Next, a dielectric film of a predetermined thickness (e.g. 9000 [Å] - 15000 [Å]) is formed by vertical sputtering (sputtering incidence angle θ=0 degrees) on the surface of the
substrate 60 on which the resistpattern 63 has been formed, thereby forming afirst dielectric layer 64 overlapping with the firstmetal electrode layer 61 in theaperture 63 a. This dielectric layer film may, for example, be the same as that used in the first embodiment. - Next, a metal layer is formed by oblique sputtering where the sputtering incidence angle θ lies in a range of 10 degrees to 30 degrees and the sputtering orientation angel Å is 90 degrees, thereby forming the second
metal electrode layer 65 in theaperture 63 a. This secondmetal electrode layer 65 overlaps with most of the surface of the first dielectric layer 64 (except for a part of thelayer 64 adjacent to the first metal electrode layer 61), but does not overlap with the exposed surface of the firstmetal electrode layer 61. The secondmetal electrode layer 65 is therefore electrically isolated from the firstmetal electrode layer 61. - The first
metal electrode layer 61 and the secondmetal electrode layer 65 may be formed, for example, of Ti/Pt metal as in the first embodiment. Ti film and Pt film are formed respectively to thicknesses of 500 [Å] and 1000 [Å]. - Next, a dielectric film is formed by vertical sputtering, and a
second dielectric layer 66 is thereby formed in theaperture 63 a. This seconddielectric layer 66 overlaps with most of the surface of thesecond metal layer 65 and with the exposed surface of thefirst dielectric layer 64. - Next, a metal layer is formed by oblique sputtering wherein the sputtering incident angle θ lies in a range of 10 degrees to 30 degrees and the sputtering orientation angle ø is 270 degrees. This third
metal electrode layer 67 is formed in theaperture 63 a. The thirdmetal electrode layer 67 overlaps with most of the surface of thesecond dielectric layer 66 and with the exposed surface of the firstmetal electrode layer 61, but does not overlap with the exposed surface of the second metal electrode layer. A dielectric film is also formed by vertical sputtering, athird dielectric layer 68 thereby being formed in theaperture 13 a. - Next, in FIG. 8B and FIG. 8E, the resist
pattern 63 is lifted off by dissolving it, and another resistpattern 69 having anaperture 69 is formed. This resistpattern 69 is used to form a fourth metal electrode layer 70 (described below), and to connect the fourthmetal electrode layer 70 with thegate electrode 8 b of the transistor Tr2. Theaperture 69 a therefore contains an area reaching thegate electrode 8 b of the transistor Tr2. Theaperture 69 a also contains an exposed surface area of the secondmetal electrode layer 65, but does not contains the exposed surface areas of the firstmetal electrode layer 61 and thirdmetal electrode layer 67. - Next, a metal layer is formed by vertical sputtering or vapor deposition so as to form the fourth
metal electrode layer 70 in theaperture 69 a. Thefourth metal electrode 70 overlaps with most of the exposed surface of thethird dielectric layer 68 and the exposed surface of the secondmetal electrode layer 67, but does not overlap with the exposed surfaces of the firstmetal electrode layer 61 and the third metal electrode layer. The fourthmetal electrode layer 70 also overlaps with (is connected with) the exposed surface of thegate electrode 8 b of the transistor Tr2. - Next, in FIG. 8C and FIG. 8F, the resist
pattern 69 is lifted off by dissolving it. In this way, a capacitor having a laminated structure comprising thefirst metal electrode 61,first dielectric layer 64, secondmetal electrode layer 65,second dielectric layer 66, thirdmetal electrode layer 67, thirddielectric layer 68 andfourth metal electrode 70, is formed. When this capacitor is used as the capacitor C1, the odd-numbered metal electrode layers comprise thefirst electrode 51 a, the even-numbered metal electrode layers comprise the second metal electrode 552 a, and the first-third dielectric layers comprise the dielectric 3 a. - Hence according to the second embodiment, by giving the capacitor a laminated structure comprising the fourth metal electrode layer and third dielectric layer, the effective surface area S of the capacitor is increased. Specifically, the effective surface area S of the capacitor can be increased by effectively 3 times relative to the pattern occupancy area of the capacitor. The capacitance of the capacitor may therefore be increased by approximately 3 times for the same pattern occupancy area.
- Further, by using the resist
pattern 63 as a mask in a capacitor forming process wherein the sputtering incidence angle is varied in order to form each film, thefirst dielectric layer 64, secondmetal electrode layer 65,second dielectric layer 66 and thirdmetal electrode layer 67 are sequentially formed by sputtering. It is therefore unnecessary to perform sputtering, patterning, etching, and resist removal to form each layer as when the etching method is used, hence the process is simplified. - Moreover, by arranging that the
first metal electrode 61 and thefourth metal electrode 70 are connected to an external circuit (transistors Tr1, Tr2 in FIG. 7), the wiring step after forming the interlayer insulating film can be omitted. - In the capacitor C1, by applying ground potential to the
first electrode 51 a and a negative potential to thesecond electrode 52 a, the side gate effect of the transistor Tr1 disappears and deterioration of the transistor output is avoided. - In the aforesaid second embodiment, the number of laminated layers of the capacitor was 3, however it will be understood that the number of laminated layers is not limited to this.
- Further, connection to an external circuit may be performed also after forming the inter-layer insulating film as in the first embodiment.
- An electrically conducting area may also be formed by ion implantation or epitaxial growth techniques in the part of the surface of the
GaAs semiconductor substrate 60 where it is desired to form the firstmetal electrode layer 61, and this electrically conducting area used as the first metal electrode layer.
Claims (23)
1. A method of fabricating a semiconductor device comprising the steps of:
(a) forming a mask layer over an upper surface of a semiconductor substrate such that said mask layer has an aperture penetrating said mask layer and having an inclined lateral wall so as to make said aperture inverted taper shaped;
(b) forming a first dielectric layer at a first area over said upper surface of said semiconductor substrate within said aperture by sputtering at a first sputtering incidence direction; and
(c) forming a first electrode layer at a second area over said upper surface of said semiconductor substrate within said aperture by sputtering at a second sputtering incidence direction which is different from said first sputtering incidence direction.
2. A method of , further comprising a step (d) of forming a metal electrode layer on said upper surface of said semiconductor substrate before said step (a).
claim 1
3. A method of , wherein said step (d) is conducted using an etching.
claim 2
4. A method of , further comprising a step (e) of forming a conductive area in said upper surface of said semiconductor substrate before said step (a).
claim 1
5. A method of , wherein said step (e) is conducted using an ion implantation.
claim 4
6. A method of , wherein said step (e) is conducted using an epitaxial growth.
claim 4
7. A method of , further comprising the steps of:
claim 1
(f) forming a second dielectric layer at a third area over said upper surface of said semiconductor substrate within said aperture by sputtering at a third sputtering incidence direction; and
(g) forming a third electrode layer at a fourth area over said upper surface of said semiconductor substrate within said aperture by sputtering at a fourth sputtering incidence direction which is different from said first to third sputtering incidence directions.
8. A method of , wherein said steps (b), (c), (f) and (g) are repeated in this order at desired times.
claim 7
9. A method of , wherein said first and third sputtering incidence directions are perpendicular to said upper surface of said semiconductor substrate.
claim 7
10. A method of , wherein an incident angle between said second sputtering incidence direction and a normal line perpendicular to said upper surface of said semiconductor substrate lies in a range of 10 degrees to 30 degrees, an incident angle between said fourth sputtering incidence direction and said normal line lies in a range of 10 degrees to 30 degrees, and said second sputtering incidence direction and said fourth sputtering incidence direction are opposite each other with respect to said normal line.
claim 7
11. A semiconductor device wherein a capacitor is formed on a chemical compound semiconductor substrate, wherein said capacitor comprising:
a first electrode layer;
a dielectric layer formed on said first electrode layer; and
a second electrode layer formed on said dielectric layer.
12. A semiconductor device of , wherein said first electrode layer, said dielectric layer and said second electrode layer and said dielectric layer are placed on top of each other in this order.
claim 11
13. A semiconductor device of , wherein said capacitor has a function of removing a D.C. component current.
claim 10
14. A semiconductor device of , further comprising a first transistor and a second transistor each formed on said semiconductor substrate;
claim 10
wherein one end of said first electrode layer is electrically connected to said first transistor, and one end of said second electrode layer is electrically connected to said second transistor.
15. A semiconductor device of , wherein said one end of said first electrode layer is electrically connected to a source of said first transistor, and said one end of said second electrode layer is electrically connected to a gate of said second transistor.
claim 14
16. A semiconductor device of , wherein a ground potential is applied to said first electrode layer, and a negative potential is applied to said second electrode layer.
claim 15
17. A semiconductor device of , wherein:
claim 10
said chemical compound semiconductor is a GaAs substrate; and
said dielectric layer is selected from the group consisting of a silicon nitride film, a tantalum oxide film, BST and STO.
18. A semiconductor device of , wherein said electrode layer is a laminated layer including a layer of titanium and a layer of platinum.
claim 10
19. A sputtering apparatus comprising:
a sputtering chamber;
a wafer stage on which a wafer is set; and
a target stage on which a sputtering material is set;
said wafer stage and said target stage being installed in said sputtering chamber;
wherein said wafer stage comprises:
a fixed stage fixed to said sputtering chamber; and
a movable wafer holder holding said wafer and being free to rotate on said fixed stage, thereby making a sputtering incidence direction a desired direction.
20. A sputtering apparatus of , wherein:
claim 19
said fixed stage comprises a hemispherical depression on an upper surface thereof; and
said movable wafer holder has a projection of hemispherical shape which engages with said depression.
21. A sputtering apparatus comprising:
a sputtering chamber;
a wafer stage on which a wafer is set; and
a plurality of target stages on which a sputtering material is set respectively;
said wafer stage and said target stages being installed in said sputtering chamber, and said target stages being disposed in positions at which sputtering incidence directions with respect to an upper surface of said wafer are mutually different;
wherein a sputtering material set on one of said target stages is deposited over said wafer by applying a high frequency voltage between said wafer stage and said one of said target stage, thereby depositing said sputtering material over said upper surface of said wafer.
22. A multi-chamber type sputtering apparatus comprising a plurality of said sputtering chambers of .
claim 19
23. A multi-chamber type sputtering apparatus comprising a plurality of said sputtering chambers of .
claim 21
Priority Applications (2)
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US09/767,265 US20010027020A1 (en) | 1996-10-09 | 2001-01-23 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US10/278,988 US20030089602A1 (en) | 1996-10-09 | 2002-10-24 | Semiconductor device, method of fabricating the same, and supttering apparatus |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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JP8268151A JPH10116964A (en) | 1996-10-09 | 1996-10-09 | Semiconductor device, manufacturing method thereof and sputtering device |
JP268151/96 | 1996-10-09 | ||
US08/800,219 US5903023A (en) | 1996-10-09 | 1997-02-12 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US09/321,200 US6207499B1 (en) | 1996-10-09 | 1999-05-27 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US09/767,265 US20010027020A1 (en) | 1996-10-09 | 2001-01-23 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
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US09/321,200 Division US6207499B1 (en) | 1996-10-09 | 1999-05-27 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
PCT/IL1999/000506 Continuation-In-Part WO2000015316A2 (en) | 1998-08-27 | 1999-09-16 | Interactive toys |
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US10/278,988 Division US20030089602A1 (en) | 1996-10-09 | 2002-10-24 | Semiconductor device, method of fabricating the same, and supttering apparatus |
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US08/800,219 Expired - Fee Related US5903023A (en) | 1996-10-09 | 1997-02-12 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US09/321,200 Expired - Fee Related US6207499B1 (en) | 1996-10-09 | 1999-05-27 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US09/767,265 Abandoned US20010027020A1 (en) | 1996-10-09 | 2001-01-23 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US10/278,988 Abandoned US20030089602A1 (en) | 1996-10-09 | 2002-10-24 | Semiconductor device, method of fabricating the same, and supttering apparatus |
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US08/800,219 Expired - Fee Related US5903023A (en) | 1996-10-09 | 1997-02-12 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
US09/321,200 Expired - Fee Related US6207499B1 (en) | 1996-10-09 | 1999-05-27 | Semiconductor device, method of fabricating the same, and sputtering apparatus |
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US10/278,988 Abandoned US20030089602A1 (en) | 1996-10-09 | 2002-10-24 | Semiconductor device, method of fabricating the same, and supttering apparatus |
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EP (1) | EP0836224A3 (en) |
JP (1) | JPH10116964A (en) |
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1996
- 1996-10-09 JP JP8268151A patent/JPH10116964A/en active Pending
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1997
- 1997-02-12 US US08/800,219 patent/US5903023A/en not_active Expired - Fee Related
- 1997-02-14 EP EP97102412A patent/EP0836224A3/en not_active Withdrawn
- 1997-05-15 KR KR1019970018767A patent/KR19980032122A/en not_active Application Discontinuation
-
1999
- 1999-05-27 US US09/321,200 patent/US6207499B1/en not_active Expired - Fee Related
-
2001
- 2001-01-23 US US09/767,265 patent/US20010027020A1/en not_active Abandoned
-
2002
- 2002-10-24 US US10/278,988 patent/US20030089602A1/en not_active Abandoned
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US20120132522A1 (en) * | 2007-07-19 | 2012-05-31 | Innovative Micro Technology | Deposition/bonding chamber for encapsulated microdevices and method of use |
Also Published As
Publication number | Publication date |
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US6207499B1 (en) | 2001-03-27 |
EP0836224A3 (en) | 1999-09-29 |
EP0836224A2 (en) | 1998-04-15 |
US20030089602A1 (en) | 2003-05-15 |
KR19980032122A (en) | 1998-07-25 |
US5903023A (en) | 1999-05-11 |
JPH10116964A (en) | 1998-05-06 |
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