US20010015905A1 - System having memory devices operable in a common interface - Google Patents
System having memory devices operable in a common interface Download PDFInfo
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- US20010015905A1 US20010015905A1 US09/771,307 US77130701A US2001015905A1 US 20010015905 A1 US20010015905 A1 US 20010015905A1 US 77130701 A US77130701 A US 77130701A US 2001015905 A1 US2001015905 A1 US 2001015905A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Definitions
- the present invention relates to electric devices and, more particularly, to a system having memory devices operable in a common interface.
- DRAM dynamic random access memory
- SRAM static random access memory
- non-volatile semiconductor memory device such as a NAND-type flash memory device and a NOR-type flash memory device
- the volatile and non-volatile semiconductor memory devices are controlled by their corresponding memory controllers.
- Such a memory controller is disclosed in U.S. Pat. No. 5,684,978 entitled “SYNCHRONOUS DRAM CONTROLLER WITH MEMORY ACCESS COMMANDS TIMED FOR OPTIMIZED USE OF DATA BUS”, and U.S. Pat. No. 5,893,136 entitled “MEMORY CONTROLLER FOR INDEPENDENT SUPPORTING SYNCHRONOUS AND ASYNCHRONOUS DRAM MEMORIES”.
- DRAM and SRAM devices adopt an interface mode that address pins and data pins are separated from each other while a NAND-type flash memory device adopts an interface mode (i.e., “multiplexing interface mode”) that address pins and data pins are commonly used.
- the above NAND-type flash memory device is disclosed in a data book “Flash Memories” published in Samsung Electronics Co., Ltd., March 1998.
- the above DRAM device is disclosed in a data book “MOS Memory” published by Samsung Electronics Co., Ltd., 1995.
- SRAM device is disclosed in a data book “SRAM/FIFO” published in Samsung Electronics Co., Ltd., April 1995.
- the system includes a microprocessor 1 (or a central processing unit, a baseband modem of a communication terminal, a codec, etc.), a DRAM device 2 , an SRAM device 3 , and a NAND-type flash memory device 4 .
- the microprocessor 1 includes memory controllers 5 , 6 , and 7 that control the DRAM device 2 , the SRAM device 3 , and the NAND-type flash memory device 4 , respectively.
- the memory controller 5 for the only DRAM device transfers address and control signals to the DRAM device 2 through a corresponding bus.
- the memory controller 6 for the only SRAM device transfers address and control signals to the SRAM device 3 through a corresponding bus.
- the memory controller 7 for the NAND-type flash memory device transfers address and control signals to the NAND-type flash memory device 4 through a corresponding bus.
- each memory controller for the only memory devices must be provided to the microcontroller 1 , as can be seen in FIG. 1. This causes increase in a size of the microcontroller 1 (or a central processing unit, a baseband modem of a communication terminal, a codec, etc.). Therefore, memory devices having pin arrangements and interface modes that are different from each other cannot be mounted with a chip-size package (CSP).
- CSP chip-size package
- a semiconductor memory device includes a random access memory chip and a package having the random access memory chip.
- the package includes a plurality of pins for electrically connecting the random access memory chip to an external device.
- the plural pins provide memory functions commonly to a random access memory device and an electrically erasable and programmable non-volatile semiconductor memory device.
- Each of the pins is arranged at a position of a pin corresponding to the non-volatile semiconductor memory device.
- the plural pins is composed of input/output pins for receiving address and data, power supply voltage pins, ground voltage pins, a read enable pin, a chip enable pin, a command latch enable pin, an address latch enable pin, and a write enable pin.
- a semiconductor memory device includes an electrically erasable and programmable non-volatile semiconductor memory chip, and a package having the non-volatile semiconductor memory chip.
- the package includes a plurality of pins for electrically connecting the chip to an external device.
- the plural chips are composed of a first group of pins and a second group of pins.
- the pins of the first group provide memory functions commonly to a static random access memory device and an electrically erasable and programmable non-volatile semiconductor memory device.
- the pins of the first group are arranged at a position of a corresponding pin of the static random access memory device, respectively.
- the pins of the second group provide functions of unused non-volatile semiconductor memory device to the static random access memory.
- the pins of the second group are arranged at a position of an unused pin of the static random access memory, respectively.
- FIG. 1 is a block diagram showing a system configuration in accordance with a prior art.
- FIG. 2 is a block diagram showing a system configuration in accordance with one embodiment of the present invention.
- FIG. 3 is a diagram showing pin arrangements of a DRAM, an SRAM, a NOR-type flash memory, and a NAND-type flash memory in accordance with the present invention.
- FIG. 4 is a timing diagram showing read and write operations of NAND interface DRAM and SRAM shown in FIG. 2.
- FIG. 5 is a block diagram showing a NAND-type flash memory device shown in FIG. 2.
- FIG. 6 is a timing diagram showing a read operation of a NAND-type flash memory device shown in FIG. 5.
- FIG. 7 is a block diagram showing a system configuration in accordance with another embodiment of the present invention.
- FIG. 8 is a diagram showing a ball pin arrangement of an SRAM and a NAND-type flash memory shown in FIG. 7.
- FIG. 9A through FIG. 9C are timing views showing read/program/block erase operations of an SRAM interface NAND-type flash memory device shown in FIG. 8.
- the present invention provides pin arrangements, structures, and a method of operating DRAM, SRAM, and NAND-type flash memory devices.
- the DRAM and SRAM devices have a NAND interface mode (pins whose address and data are identical to each other are used), being directly coupled to buses (an address/IO bus and a control bus) of a NAND-type flash memory device that is coupled to a microprocessor and a central processing unit or a multi-chip.
- a NOR-type flash memory device has the NAND interface mode, being directly coupled to buses same as the NAND-type flash memory device.
- the NAND-type flash memory device an SRAM interface mode (an address pin and an input/output pin are separated from each other), being directly coupled to buses (e.g., an address bus, a data bus, and a control bus) same as the SRAM device.
- buses e.g., an address bus, a data bus, and a control bus
- the DRAM, SRAM, NAND-type flash memory, and NOR-type flash memory devices have the identical interface mode, and are independently (or individually) controlled by only one memory controller. Pin arrangements, structures, and an operating method of memory devices having the identical interface mode are described in detail.
- FIG. 2 schematically shows a construction of a system in accordance with the present invention.
- a microprocessor 100 includes a memory controller 110 to which address/data bus 120 for transferring address and data and a control bus 130 for transferring a plurality of control signals (e.g., ⁇ overscore (CE) ⁇ , ⁇ overscore (RE) ⁇ , ⁇ overscore (WE) ⁇ , ALE, and CLE) are connected.
- a DRAM device 140 , an SRAM device 150 , a NOR-type flash memory device 160 , and a NAND-type flash memory device 170 are directly coupled to the buses 120 and 130 . That is, the memory devices have the identical interface mode.
- the DRAM device 140 , the SRAM device 150 , and the NOR-type flash memory device 150 have the NAND interface mode, being directly coupled to the buses 120 and 130 same as the NAND-type flash memory device 160 .
- FIG. 3 illustrates pin arrangements of memory devices supporting the NAND interface mode. Pin arrangements of a 16 Mb DRAM device, an 8 Mb SRAM device, and an 8 Mb NOR-type flash memory device are compared with those of 128 Mb NAND-type flash memory 48-pin TSOP 1 package products. A first group of pins providing memory functions to all memory devices are included in a DRAM device 140 , an SRAM device 150 , a NOR-type flash memory device 160 , and a NAND-type flash memory device 170 .
- the pins of the first group includes eight input/output pins I/ 00 -I/ 07 , two power supply voltage pin VCC, two ground voltage pins VSS, and five function pins, i.e., a chip enable pin ⁇ overscore (CE) ⁇ for selecting a corresponding memory device, a read enable pin ⁇ overscore (RE) ⁇ , a write enable pin ⁇ overscore (WE) ⁇ , an address latch enable pin ALE, and a command latch enable pin CLE.
- CE chip enable pin ⁇ overscore
- RE read enable pin
- WE write enable pin
- ALE address latch enable pin
- CLE command latch enable pin CLE
- a second group of three function pins are provided, which are included only in the NOR-type flash memory device 150 and the NAND-type flash memory device 160 .
- the pins of the second group are arranged, corresponding to non-connection (N.C) pins of the DRAM and SRAM devices 140 and 150 , commonly connecting all the memory devices to the identical buses. That is, a spare array enable pin ⁇ overscore (SE) ⁇ is arranged, being located at each 6th pin (N.C) of the memory device 140 and 150 .
- a ready/ ⁇ overscore (busy) ⁇ pin R/ ⁇ overscore (B) ⁇ are arranged, being located at each 7th pin (N.C) of the memory device 140 and 150 .
- a write protect pin ⁇ overscore (WP) ⁇ is arranged, being located at each 19th pin (N.C) of the memory device 140 and 150 . Out of 48 pins, 28 pins are non-connection (N.C) pins, as can be seen in FIG. 3.
- An input of the spare array enable pin ⁇ overscore (SE) ⁇ controls spare array selection that is provided to a corresponding flash memory device.
- An input of the write protect pin ⁇ overscore (WP) ⁇ controls write/erase protect that may occur in power transition of ⁇ overscore (WP) ⁇ .
- an internal high voltage generator not shown in a memory device is reset.
- An output of the ready/ ⁇ overscore (busy) ⁇ pin R/ ⁇ overscore (B) ⁇ indicates an operation state of a corresponding flash memory device. When the output of R/ ⁇ overscore (B) ⁇ is low, it is indicated that program, erase, and read operations of the flash memory device are proceeding.
- the memory devices 140 , 150 . 160 , and 170 have pin arrangements that are identical to one another, to be operable in the identical interface mode (specifically, an interface mode of a NAND-type flash memory device).
- all the memory devices 140 , 150 , 160 , and 170 are directly coupled to the identical buses (i.e., an address/IO bus and a control bus). Therefore, one memory controller is constructed in a microcontroller (or a baseband modem of a communication terminal or a multi-chip that a plurality of devices are constructed in one chip), controlling operations of all the memory devices 140 , 150 , 160 , and 170 .
- the memory devices 140 , 150 , 160 , and 170 have pin arrangements that are identical to one another, they can easily be constructed in a chip-size package.
- FIG. 4 illustrates a timing diagram for explaining read/write operations of DRAM and SRAM devices having the foregoing interface mode.
- a chip enable signal ⁇ overscore (CE) ⁇ for selecting a DRAM device 140 is enabled.
- a read operation is described as follows.
- a command latch enable signal CLE transitions from low level to high level
- a column address CA is provided to the DRAM device 140 through I/Oi when a read enable signal ⁇ overscore (RE) ⁇ transitions from low level to high level.
- data read-out from a memory cell array is synchronized with ⁇ overscore (RE) ⁇ through I/Oi coupled to an address/data bus 120 , being transferred to a bus 120 coupled to a microprocessor 100 .
- the read operation is finished when CLE transitions from high level to low level.
- Read/write operations of a NAND interface SRAM device are also based upon a timing view shown in FIG. 4, so that description thereof will be skipped.
- the read and write operations of the NAND interface DRAM/SRAM devices are classified using signals ⁇ overscore (RE) ⁇ and ⁇ overscore (WE) ⁇ .
- the read operation is carried out in moving the read enable signal ⁇ overscore (RE) ⁇ while the write operation is carried out in moving the write enable signal ⁇ overscore (WE) ⁇ .
- the command latch enable pin CLS and the read enable pin ⁇ overscore (RE) ⁇ substitute for a row address strobe pin ⁇ overscore (RAS) ⁇ and a row address strobe pin ⁇ overscore (CAS) ⁇ of the conventional DRAM device. Since address and data are provided through the identical input/output pins, collision between an output of read-out data by a first address and an input of a second address may occur in consecutive read operations. In order to overcome the collision, an address (i.e., burst address) for the consecutive read operations is provided into a NAND interface DRAM device.
- the burst address is created using a burst counter that is well known in the art, and is driven by the read enable signal ⁇ overscore (RE) ⁇ .
- a refresh operation of the NAND interface DRAM may be carried out using the command latch enable signal CLE and the read enable signal ⁇ overscore (RE) ⁇ .
- an ROR refresh (/RAS only refresh) of a conventional DRAM device is carried out using CLE
- a CBR refresh (/CAS before /RAS refresh) is carried out using CLE and ⁇ overscore (RE) ⁇ .
- ⁇ overscore (RE) ⁇ is used as a signal ⁇ overscore (ADV) ⁇ for controlling creation of a burst address in a bust address counter of a conventional SRAM device, and as an output enable signal ⁇ overscore (OE) ⁇ .
- the burst address counter internally creates a series of burst addresses using an initial address.
- ⁇ overscore (OE) ⁇ retains low level, data read out from a memory cell array of a NAND interface SRAM device is outputted through data input/output pins I/Oi.
- the NAND interface SRAM device of this invention uses a second-inputted address out of addresses that are inputted in twice, as a burst address.
- a NAND flash memory device of this invention is schematically shown in FIG. 5, and an operation timing diagram for describing a read operation is shown in FIG. 6. With reference to FIG. 6, the read operation will now be described more fully hereinafter.
- column addresses A 0 -A 7 and page (row) addresses A 8 -A 16 and A 17 -A 23 are latched to a Y-buffer latch 212 and an X-buffer latch 214 , respectively.
- a ready/ ⁇ overscore (busy) ⁇ signal R/ ⁇ overscore (B) ⁇ retains low level for a predetermined time so as to carry out a practical read operation (i.e., data stored in memory cells of a selected row is latched to a page buffer circuit).
- a NAND-type flash memory device is unselected so as to carry out a read/write operation of other memory device (i.e., a chip enable signal ⁇ overscore (CE) ⁇ corresponding to the NAND-type flash memory device transitions from low level to high level).
- the command 00h, a column address, and a page address are transferred to a command register 210 , a Y-buffer latch 212 , and an X-buffer latch 214 , respectively.
- a previous page address latched to the X-buffer latch 214 is transferred to an X-buffer latch 218 .
- a comparator 220 compares whether the latched address to the X-buffer latches 214 and 218 are matched with each other, outputting a signal HIT/MISS as a comparison result.
- a read control logic 216 controls a sensing operation associated with a currently inputted address (i.e., an address latched to the X-buffer latch 214 ) not to be carried out.
- an X-predecoder 222 is disabled by the read control logic 216 . 16 .
- the data which is latched to a page buffer circuit 224 by a sensing operation that is previously carried out, is then transferred to a bus 120 through the input/output pins I/Oi by the control of the read control logic 216 .
- a system configuration according to another embodiment is schematically shown in FIG. 7.
- a microprocessor 300 includes a memory controller 310 that generates a control signal for controlling an operation of a memory device and address signals.
- An address bus 320 for transferring an address, a data bus 330 for transferring data, and a control bus 340 for transferring control signals are connected to the memory controller 310 .
- a NAND-type flash memory device 350 and an SRAM device 360 are directly coupled to the buses 320 , 330 , and 340 . That is, each memory device has the identical interface mode.
- each memory device has an SRAM interface mode (an address pin and a data pin are separated from each other), directly being coupled to the buses 320 , 330 , and 340 same as the SRAM device 360 .
- SRAM interface mode an address pin and a data pin are separated from each other
- a ball pin arrangement of a NAND-type flash memory device is compared with that of an SRAM 48-pin FBGA package product.
- a first group of pins providing common memory operations to both memory devices are included in a NAND-type flash memory device 350 and an SRAM device 360 .
- the pins of the first group are composed of address pins A 0 -A 16 for receiving an address, input/input pins I/O 1 -I/O 16 for receiving data, two power supply voltage pins VCC, two ground voltage pins VSS, and six function pins.
- the six function pins are composed of chip selection pins CS 2 and ⁇ overscore (CS 1 ) ⁇ for selecting a corresponding memory device, an output enable pin ⁇ overscore (OE) ⁇ , a write enable pin ⁇ overscore (WE) ⁇ , a pin ⁇ overscore (LB) ⁇ for selecting data bits of a lower byte, and a pin ⁇ overscore (UB) ⁇ for selecting data bits of an upper byte.
- two function pins are provided which compose a second group of pins included only in the NAND-type flash memory device 350 .
- the pins of the second group are arranged, corresponding to non-connection (N.C) pins of an SRAM device.
- the memory devices 350 and 360 are commonly coupled to the address, data, and control buses. That is, a ready/ ⁇ overscore (busy) ⁇ pin R/ ⁇ overscore (B) ⁇ is arranged, being situated at a 1 H pin (N.C) of the SRAM device 360 .
- a hardware rest pin ⁇ overscore (RESET) ⁇ is arranged, being situated at a 6 H pin (N.C) of the SRAM device 360 .
- the NAND-type flash memory device 350 further includes address pins A 17 and A 18 that are arranged, being situated at 3 D and 3 E pins of the SRAM device 360 , respectively. Remaining pins out of 48 pins are non-connection (N.C) pins.
- N.C non-connection
- the NAND-type flash memory device of this invention applies suitable command signals to input/output pins, carrying out page program, block erase, chip erase, and erase interrupt/refresh operations. For example, if a command signal “80h” (FF hexadecimal) is applied to an input/output pin, the NAND-type flash memory device senses the command and carries out a page program operation, as shown in the following [TABLE 3]. Similarly, command signals “FFh”, “60h”, and “BOh/DOh” enable the NAND-type flash memory device to carry out reset, block erase, and erase interrupt/refresh operations, respectively. If a command signal is not inputted, a read operation is carried out, as a default mode. TABLE 3 Command Set Mode of Operation First Cycle Second Cycle Read Address Reset FFh Page Program 80 h Block Erase 60 h DOh Erase Interrupt/Refresh BOh/DOh
- a chip selection signal ⁇ overscore (CSI) ⁇ transitions from high level to low level
- a NAND-type flash memory device is selected. Without an input of a command signal, a page address is then applied through address pins Ai, as shown in FIG. 9A.
- a ready/ ⁇ overscore (busy) ⁇ signal R/ ⁇ overscore (B) ⁇ transitions from high level to low level for a predetermined time tR that is taken to carry out a read operation of the NAND-type flash memory device.
- a conventional page buffer circuit senses and latches data from memory cells of a selected row for the reading time. The latched data is synchronized with an output enable signal ⁇ overscore (OE) ⁇ , being outputted to the outside (e.g., a memory controller coupled to a data bus) through input/output pins I/Oi.
- OE output enable signal
- a dummy address command AAh (provided to prevent an unwanted program operation caused by unspecific data)
- a serial data input command SOh a column/row address ADD
- a series of data Din are sequentially inputted.
- a serial data input command 80h and data Din are inputted through input/output pins I/Oi in a low-to-high transition of a write enable signal ⁇ overscore (WE) ⁇ .
- the command AAh and address ADD are inputted through address pins Ai in a high-to-low transition of ⁇ overscore (WE) ⁇ .
- a block erase operation of a NAND-type flash memory device coupled to the same bus as an SRAM is similar to the program operation.
- a dummy address command AAh (provided to prevent an unwanted program operation caused by unspecific data) and a block address are inputted.
- a block erase setup command 60h and a command DOh to confirm a block erase operation are inputted.
- a ready/ ⁇ overscore (busy) ⁇ signal R/ ⁇ overscore (B) ⁇ retains low level for a predetermined erase time tBERS
- the block erase operation is then carried out.
- a signal outputted through an input/output pin I/O 0 is used as a flag signal that indicates erase pass or erase fail.
- memory devices provided to a system have pin arrangements that are identical to each other, being operable in the identical interface mode (e.g., an interface mode of a NAND-type flash memory device or an SRAM device). So all the memory devices are directly coupled to identical buses.
- one memory controller is constructed in a microprocessor (or a baseband modem of a communication terminal, a multi-chip that a plurality of devices are established in one chip, etc.), controlling operations of all the memory devices. Having the identical pin arrangement, the memory devices can easily be established in a chip-size package.
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Abstract
Description
- This application relies for priority upon Korean Patent Application No. 2000-03708, filed on Jan. 26, 2000, the contents of which are herein incorporated by reference in their entirety.
- The present invention relates to electric devices and, more particularly, to a system having memory devices operable in a common interface.
- Recently, various memory devices are employed in a computer- or microprocessor-based system. As storage elements within such a system, volatile semiconductor memory devices such as a dynamic random access memory device (DRAM) or a static random access memory device (SRAM), and non-volatile semiconductor memory device such as a NAND-type flash memory device and a NOR-type flash memory device are required therein. The volatile and non-volatile semiconductor memory devices are controlled by their corresponding memory controllers. Such a memory controller is disclosed in U.S. Pat. No. 5,684,978 entitled “SYNCHRONOUS DRAM CONTROLLER WITH MEMORY ACCESS COMMANDS TIMED FOR OPTIMIZED USE OF DATA BUS”, and U.S. Pat. No. 5,893,136 entitled “MEMORY CONTROLLER FOR INDEPENDENT SUPPORTING SYNCHRONOUS AND ASYNCHRONOUS DRAM MEMORIES”.
- As well known in the art, DRAM and SRAM devices adopt an interface mode that address pins and data pins are separated from each other while a NAND-type flash memory device adopts an interface mode (i.e., “multiplexing interface mode”) that address pins and data pins are commonly used. The above NAND-type flash memory device is disclosed in a data book “Flash Memories” published in Samsung Electronics Co., Ltd., March 1998. The above DRAM device is disclosed in a data book “MOS Memory” published by Samsung Electronics Co., Ltd., 1995. And, the above SRAM device is disclosed in a data book “SRAM/FIFO” published in Samsung Electronics Co., Ltd., April 1995.
- A conventional system is schematically shown in FIG. 1. The system includes a microprocessor1 (or a central processing unit, a baseband modem of a communication terminal, a codec, etc.), a
DRAM device 2, anSRAM device 3, and a NAND-typeflash memory device 4. Themicroprocessor 1 includesmemory controllers DRAM device 2, theSRAM device 3, and the NAND-typeflash memory device 4, respectively. Thememory controller 5 for the only DRAM device transfers address and control signals to theDRAM device 2 through a corresponding bus. Thememory controller 6 for the only SRAM device transfers address and control signals to theSRAM device 3 through a corresponding bus. And, thememory controller 7 for the NAND-type flash memory device transfers address and control signals to the NAND-typeflash memory device 4 through a corresponding bus. - Since memory devices used in a system have pin arrangements and interface modes that are different from each other, each memory controller for the only memory devices must be provided to the
microcontroller 1, as can be seen in FIG. 1. This causes increase in a size of the microcontroller 1 (or a central processing unit, a baseband modem of a communication terminal, a codec, etc.). Therefore, memory devices having pin arrangements and interface modes that are different from each other cannot be mounted with a chip-size package (CSP). - It is therefore an object of the present invention to provide a system having NAND interface DRAM, SRAM, and NOR-type flash memory devices which are commonly connected to one bus.
- It is another object of the present invention to a NAN-type flash memory device having an SRAM interface mode.
- It is further another object of the present invention to provide a NAND-type flash memory device capable of enhancing a bus use efficiency.
- According to one aspect of the present invention, a semiconductor memory device includes a random access memory chip and a package having the random access memory chip. The package includes a plurality of pins for electrically connecting the random access memory chip to an external device. The plural pins provide memory functions commonly to a random access memory device and an electrically erasable and programmable non-volatile semiconductor memory device. Each of the pins is arranged at a position of a pin corresponding to the non-volatile semiconductor memory device.
- The plural pins is composed of input/output pins for receiving address and data, power supply voltage pins, ground voltage pins, a read enable pin, a chip enable pin, a command latch enable pin, an address latch enable pin, and a write enable pin.
- According to another aspect of the present invention, a semiconductor memory device includes an electrically erasable and programmable non-volatile semiconductor memory chip, and a package having the non-volatile semiconductor memory chip. The package includes a plurality of pins for electrically connecting the chip to an external device. The plural chips are composed of a first group of pins and a second group of pins. The pins of the first group provide memory functions commonly to a static random access memory device and an electrically erasable and programmable non-volatile semiconductor memory device. And, the pins of the first group are arranged at a position of a corresponding pin of the static random access memory device, respectively. The pins of the second group provide functions of unused non-volatile semiconductor memory device to the static random access memory. The pins of the second group are arranged at a position of an unused pin of the static random access memory, respectively.
- FIG. 1 is a block diagram showing a system configuration in accordance with a prior art.
- FIG. 2 is a block diagram showing a system configuration in accordance with one embodiment of the present invention.
- FIG. 3 is a diagram showing pin arrangements of a DRAM, an SRAM, a NOR-type flash memory, and a NAND-type flash memory in accordance with the present invention.
- FIG. 4 is a timing diagram showing read and write operations of NAND interface DRAM and SRAM shown in FIG. 2.
- FIG. 5 is a block diagram showing a NAND-type flash memory device shown in FIG. 2.
- FIG. 6 is a timing diagram showing a read operation of a NAND-type flash memory device shown in FIG. 5.
- FIG. 7 is a block diagram showing a system configuration in accordance with another embodiment of the present invention.
- FIG. 8 is a diagram showing a ball pin arrangement of an SRAM and a NAND-type flash memory shown in FIG. 7.
- FIG. 9A through FIG. 9C are timing views showing read/program/block erase operations of an SRAM interface NAND-type flash memory device shown in FIG. 8.
- The present invention will now be described more fully hereinafter with reference to accompanying drawings wherein preferred embodiments of the invention are illustrated.
- The present invention provides pin arrangements, structures, and a method of operating DRAM, SRAM, and NAND-type flash memory devices. The DRAM and SRAM devices have a NAND interface mode (pins whose address and data are identical to each other are used), being directly coupled to buses (an address/IO bus and a control bus) of a NAND-type flash memory device that is coupled to a microprocessor and a central processing unit or a multi-chip. Also, a NOR-type flash memory device has the NAND interface mode, being directly coupled to buses same as the NAND-type flash memory device. And, the NAND-type flash memory device an SRAM interface mode (an address pin and an input/output pin are separated from each other), being directly coupled to buses (e.g., an address bus, a data bus, and a control bus) same as the SRAM device. In brief, the DRAM, SRAM, NAND-type flash memory, and NOR-type flash memory devices have the identical interface mode, and are independently (or individually) controlled by only one memory controller. Pin arrangements, structures, and an operating method of memory devices having the identical interface mode are described in detail.
- FIG. 2 schematically shows a construction of a system in accordance with the present invention. A
microprocessor 100 includes amemory controller 110 to which address/data bus 120 for transferring address and data and acontrol bus 130 for transferring a plurality of control signals (e.g., {overscore (CE)}, {overscore (RE)}, {overscore (WE)}, ALE, and CLE) are connected. ADRAM device 140, anSRAM device 150, a NOR-typeflash memory device 160, and a NAND-typeflash memory device 170 are directly coupled to thebuses DRAM device 140, theSRAM device 150, and the NOR-typeflash memory device 150 have the NAND interface mode, being directly coupled to thebuses flash memory device 160. - FIG. 3 illustrates pin arrangements of memory devices supporting the NAND interface mode. Pin arrangements of a 16 Mb DRAM device, an 8 Mb SRAM device, and an 8 Mb NOR-type flash memory device are compared with those of 128 Mb NAND-type flash memory 48-pin TSOP1 package products. A first group of pins providing memory functions to all memory devices are included in a
DRAM device 140, anSRAM device 150, a NOR-typeflash memory device 160, and a NAND-typeflash memory device 170. The pins of the first group includes eight input/output pins I/00-I/07, two power supply voltage pin VCC, two ground voltage pins VSS, and five function pins, i.e., a chip enable pin {overscore (CE)} for selecting a corresponding memory device, a read enable pin {overscore (RE)}, a write enable pin {overscore (WE)}, an address latch enable pin ALE, and a command latch enable pin CLE. - As shown in FIG. 3, a second group of three function pins are provided, which are included only in the NOR-type
flash memory device 150 and the NAND-typeflash memory device 160. The pins of the second group are arranged, corresponding to non-connection (N.C) pins of the DRAM andSRAM devices memory device memory device memory device - An input of the spare array enable pin {overscore (SE)} controls spare array selection that is provided to a corresponding flash memory device. An input of the write protect pin {overscore (WP)} controls write/erase protect that may occur in power transition of {overscore (WP)}. When the input of {overscore (WP)} is enabled, an internal high voltage generator (not shown) in a memory device is reset. An output of the ready/{overscore (busy)} pin R/{overscore (B)} indicates an operation state of a corresponding flash memory device. When the output of R/{overscore (B)} is low, it is indicated that program, erase, and read operations of the flash memory device are proceeding. The
memory devices memory devices memory devices memory devices - FIG. 4 illustrates a timing diagram for explaining read/write operations of DRAM and SRAM devices having the foregoing interface mode. Assuming that a chip enable signal {overscore (CE)} for selecting a
DRAM device 140 is enabled. Under the assumption, a read operation is described as follows. When a command latch enable signal CLE transitions from low level to high level, a row address RA is provided to theDRAM device 140 through input/output pins I/Oi (i=0-7). Then, a column address CA is provided to theDRAM device 140 through I/Oi when a read enable signal {overscore (RE)} transitions from low level to high level. After a predetermined access time tREA, data read-out from a memory cell array is synchronized with {overscore (RE)} through I/Oi coupled to an address/data bus 120, being transferred to abus 120 coupled to amicroprocessor 100. The read operation is finished when CLE transitions from high level to low level. - Under the identical assumption, a read operation is described as follows. When the command latch enable signal CLE transitions from low level to high level again after a row precharge time tCLEP, a row address RA is provided through input/output pins I/Oi (i=1-7). A column address CA is then provided through I/Oi when {overscore (CE)} transitions from low level to high level. And then, data DIN synchronized with a write enable signal {overscore (WE)} inputs through data input/output pins I/Oi coupled to the
bus 120, and is stored in the memory cell array according to a late write mode that is known in the art. - In FIG. 4, comparing AC characteristic parameters of NAND interface DRAM and SRAM devices with those of conventional DRAM and SRAM devices, the comparison results are shown in the following tables.
TABLE 1 Conventional DRAM tCAC tHPC tDOH TRP NI-DRAM tREA TRC(tWC) tRHZ TCLEP Speed 15 ns 25(25) ns 15 ns 30 ns -
TABLE 2 Conventional TACCB tCLK tOHZ tAS/tAH tACC2 SRAM NI-SRAM TREA TRC(tWC) tRHZ tAS/ tAH tACC Speed 15 ns 25(25) ns 15 ns 20/0 ns 100 ns - Read/write operations of a NAND interface SRAM device according to the present invention are also based upon a timing view shown in FIG. 4, so that description thereof will be skipped. The read and write operations of the NAND interface DRAM/SRAM devices are classified using signals {overscore (RE)} and {overscore (WE)}. For example, the read operation is carried out in moving the read enable signal {overscore (RE)} while the write operation is carried out in moving the write enable signal {overscore (WE)}.
- By the above description, it is known that the command latch enable pin CLS and the read enable pin {overscore (RE)} substitute for a row address strobe pin {overscore (RAS)} and a row address strobe pin {overscore (CAS)} of the conventional DRAM device. Since address and data are provided through the identical input/output pins, collision between an output of read-out data by a first address and an input of a second address may occur in consecutive read operations. In order to overcome the collision, an address (i.e., burst address) for the consecutive read operations is provided into a NAND interface DRAM device. The burst address is created using a burst counter that is well known in the art, and is driven by the read enable signal {overscore (RE)}. A refresh operation of the NAND interface DRAM may be carried out using the command latch enable signal CLE and the read enable signal {overscore (RE)}. For example, an ROR refresh (/RAS only refresh) of a conventional DRAM device is carried out using CLE, and a CBR refresh (/CAS before /RAS refresh) is carried out using CLE and {overscore (RE)}.
- In the NAND interface SRAM device, {overscore (RE)} is used as a signal {overscore (ADV)} for controlling creation of a burst address in a bust address counter of a conventional SRAM device, and as an output enable signal {overscore (OE)}. For example, when {overscore (ADV)} is enabled, the burst address counter internally creates a series of burst addresses using an initial address. When {overscore (OE)} retains low level, data read out from a memory cell array of a NAND interface SRAM device is outputted through data input/output pins I/Oi. The NAND interface SRAM device of this invention uses a second-inputted address out of addresses that are inputted in twice, as a burst address.
- A NAND flash memory device of this invention is schematically shown in FIG. 5, and an operation timing diagram for describing a read operation is shown in FIG. 6. With reference to FIG. 6, the read operation will now be described more fully hereinafter.
- Referring to FIG. 5, a
command 00h, inputted through input/output pins I/Oi (i=0-7), to indicate a read operation, is transferred to acommand register 210. Consecutively, column addresses A0-A7 and page (row) addresses A8-A16 and A17-A23 are latched to a Y-buffer latch 212 and anX-buffer latch 214, respectively. Based upon control of aread control logic 216, a ready/{overscore (busy)} signal R/{overscore (B)} retains low level for a predetermined time so as to carry out a practical read operation (i.e., data stored in memory cells of a selected row is latched to a page buffer circuit). A NAND-type flash memory device is unselected so as to carry out a read/write operation of other memory device (i.e., a chip enable signal {overscore (CE)} corresponding to the NAND-type flash memory device transitions from low level to high level). - If the read/write operation of other memory device is completed and the chip enable signal {overscore (CE)} for selecting the NAND-type flash memory device has a high-to-low transition, the
command 00h, a column address, and a page address are transferred to acommand register 210, a Y-buffer latch 212, and anX-buffer latch 214, respectively. At this time, a previous page address latched to theX-buffer latch 214 is transferred to anX-buffer latch 218. And, acomparator 220 compares whether the latched address to the X-buffer latches 214 and 218 are matched with each other, outputting a signal HIT/MISS as a comparison result. In response to, for example, a high-level signal HIT/MISS indicating that two addresses are matched with each other, aread control logic 216 controls a sensing operation associated with a currently inputted address (i.e., an address latched to the X-buffer latch 214) not to be carried out. For example, an X-predecoder 222 is disabled by theread control logic 216. 16. The data, which is latched to apage buffer circuit 224 by a sensing operation that is previously carried out, is then transferred to abus 120 through the input/output pins I/Oi by the control of the readcontrol logic 216. - In such a read operation, when a previously inputted page (row) address is matched with a currently inputted page (row) address, a practical read operation (specifically, sensing operation) is not carried out. And, data (corresponding to a previously inputted page) latched to the
page buffer circuit 224 is outputted to the outside, as data required to a current read operation. As shown in FIG. 6, a time tC (e.g., 100 ns) required in the current read operation is shorter than a time tR (e.g., 10 μs) required in a previous read operation. Therefore, other memory device can uses the identical buses (to which an SRAM, a DRAM, a NOR-type flash memory, and a NAND-type flash memory are coupled) for a shortened time. This leads to enhancement of bus use efficiency of memory devices that are established by a common interface mode. - A system configuration according to another embodiment is schematically shown in FIG. 7. A
microprocessor 300 includes amemory controller 310 that generates a control signal for controlling an operation of a memory device and address signals. Anaddress bus 320 for transferring an address, adata bus 330 for transferring data, and acontrol bus 340 for transferring control signals are connected to thememory controller 310. A NAND-typeflash memory device 350 and anSRAM device 360 are directly coupled to thebuses buses SRAM device 360. A ball pin arrangement satisfying such a situation is shown in FIG. 8. - Referring now to FIG. 8, a ball pin arrangement of a NAND-type flash memory device is compared with that of an SRAM 48-pin FBGA package product. A first group of pins providing common memory operations to both memory devices are included in a NAND-type
flash memory device 350 and anSRAM device 360. The pins of the first group are composed of address pins A0-A16 for receiving an address, input/input pins I/O1-I/O16 for receiving data, two power supply voltage pins VCC, two ground voltage pins VSS, and six function pins. The six function pins are composed of chip selection pins CS2 and {overscore (CS1)} for selecting a corresponding memory device, an output enable pin {overscore (OE)}, a write enable pin {overscore (WE)}, a pin {overscore (LB)} for selecting data bits of a lower byte, and a pin {overscore (UB)} for selecting data bits of an upper byte. - Referring to FIG. 8 again, two function pins are provided which compose a second group of pins included only in the NAND-type
flash memory device 350. The pins of the second group are arranged, corresponding to non-connection (N.C) pins of an SRAM device. Thus, thememory devices SRAM device 360. A hardware rest pin {overscore (RESET)} is arranged, being situated at a 6H pin (N.C) of theSRAM device 360. And, the NAND-typeflash memory device 350 further includes address pins A17 and A18 that are arranged, being situated at 3D and 3E pins of theSRAM device 360, respectively. Remaining pins out of 48 pins are non-connection (N.C) pins. - The NAND-type flash memory device of this invention applies suitable command signals to input/output pins, carrying out page program, block erase, chip erase, and erase interrupt/refresh operations. For example, if a command signal “80h” (FF hexadecimal) is applied to an input/output pin, the NAND-type flash memory device senses the command and carries out a page program operation, as shown in the following [TABLE 3]. Similarly, command signals “FFh”, “60h”, and “BOh/DOh” enable the NAND-type flash memory device to carry out reset, block erase, and erase interrupt/refresh operations, respectively. If a command signal is not inputted, a read operation is carried out, as a default mode.
TABLE 3 Command Set Mode of Operation First Cycle Second Cycle Read Address Reset FFh Page Program 80 h Block Erase 60 h DOh Erase Interrupt/Refresh BOh/DOh - With reference to FIG. 9A through FIG. 9C, read/program/block erase operations of a NAND-type flash memory device having the foregoing common interface mode will be described more fully hereinafter.
- As a chip selection signal {overscore (CSI)} transitions from high level to low level, a NAND-type flash memory device is selected. Without an input of a command signal, a page address is then applied through address pins Ai, as shown in FIG. 9A. At this time, a ready/{overscore (busy)} signal R/{overscore (B)} transitions from high level to low level for a predetermined time tR that is taken to carry out a read operation of the NAND-type flash memory device. A conventional page buffer circuit senses and latches data from memory cells of a selected row for the reading time. The latched data is synchronized with an output enable signal {overscore (OE)}, being outputted to the outside (e.g., a memory controller coupled to a data bus) through input/output pins I/Oi.
- Referring now to FIG. 9B, after a high-to-low transition of a chip selection circuit {overscore (CSI)}, a dummy address command AAh (provided to prevent an unwanted program operation caused by unspecific data), a serial data input command SOh, a column/row address ADD, and a series of data Din are sequentially inputted. A serial
data input command 80h and data Din are inputted through input/output pins I/Oi in a low-to-high transition of a write enable signal {overscore (WE)}. And, the command AAh and address ADD are inputted through address pins Ai in a high-to-low transition of {overscore (WE)}. As a ready/{overscore (busy)} signal R/{overscore (B)} retains low level for a predetermined program time tPROG, a practical program operation is then carried out to memory cells. After the program operation, a signal outputted through an input/output pin I/OO is used as a flag signal that indicates program pass or program fail. - A block erase operation of a NAND-type flash memory device coupled to the same bus as an SRAM is similar to the program operation. Referring to FIG. 9C, on the basis of a falling edge of a write enable signal {overscore (WE)}, a dummy address command AAh (provided to prevent an unwanted program operation caused by unspecific data) and a block address are inputted. And, on the basis of a rising edge of {overscore (WE)}, a block erase
setup command 60h and a command DOh to confirm a block erase operation are inputted. As a ready/{overscore (busy)} signal R/{overscore (B)} retains low level for a predetermined erase time tBERS, the block erase operation is then carried out. After the block erase operation, a signal outputted through an input/output pin I/O0 is used as a flag signal that indicates erase pass or erase fail. - As mentioned so far, memory devices provided to a system have pin arrangements that are identical to each other, being operable in the identical interface mode (e.g., an interface mode of a NAND-type flash memory device or an SRAM device). So all the memory devices are directly coupled to identical buses. As a result, one memory controller is constructed in a microprocessor (or a baseband modem of a communication terminal, a multi-chip that a plurality of devices are established in one chip, etc.), controlling operations of all the memory devices. Having the identical pin arrangement, the memory devices can easily be established in a chip-size package.
- In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation, the scope of the invention being set forth in the following claims.
Claims (11)
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Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003021602A2 (en) | 2001-08-28 | 2003-03-13 | Intel Corporation | Multiple word-line accessing and accessor |
US20030172261A1 (en) * | 2002-03-08 | 2003-09-11 | Seok-Heon Lee | System boot using NAND flash memory and method thereof |
EP1387284A2 (en) * | 2002-07-29 | 2004-02-04 | Samsung Electronics Co., Ltd. | Computer system with nand flash memory for booting and data storage |
US20050273564A1 (en) * | 2004-06-02 | 2005-12-08 | Sridhar Lakshmanamurthy | Memory controller |
US20060041711A1 (en) * | 2002-11-28 | 2006-02-23 | Renesas Technology Corporation | Memory module, memory system, and information device |
US20060174056A1 (en) * | 2003-03-19 | 2006-08-03 | Koninklijke Philips Electronics N.V. | Universal memory device having a profil storage unit |
US20060184724A1 (en) * | 2005-02-11 | 2006-08-17 | M-Systems Flash Disk Pioneers, Ltd. | NAND flash memory system architecture |
US20070058480A1 (en) * | 2005-09-12 | 2007-03-15 | Sang-Won Hwang | NAND flash memory device with burst read latency function |
EP1343082A3 (en) * | 2002-03-08 | 2007-03-28 | Samsung Electronics Co., Ltd. | System boot using nand flash memory and method thereof |
US20070171722A1 (en) * | 2006-01-24 | 2007-07-26 | Sang-Gu Kang | Flash memory system compensating reduction in read margin between memory cell program states |
US20080046665A1 (en) * | 2006-05-24 | 2008-02-21 | Kyoung-Park Kim | Multiport Memory Device, Multiprocessor System Including the Same, and Method of Transmitting Data In Multiprocessor System |
US20100205504A1 (en) * | 2009-02-11 | 2010-08-12 | Mosys, Inc. | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process |
US20110145486A1 (en) * | 2009-12-16 | 2011-06-16 | Tsutomu Owa | Memory management device and method |
CN101281494B (en) * | 2002-09-11 | 2012-04-04 | 株式会社日立制作所 | System and method for using dynamic random access memory and flash memory |
WO2015034580A1 (en) * | 2013-09-03 | 2015-03-12 | Qualcomm Incorporated | Unified memory controller for heterogeneous memory on a multi-chip package |
US10416932B2 (en) | 2013-04-25 | 2019-09-17 | Microsoft Technology Licensing, Llc | Dirty data management for hybrid drives |
CN111758160A (en) * | 2020-05-20 | 2020-10-09 | 长江存储科技有限责任公司 | 3D NAND flash memory device and integration method thereof |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6721840B1 (en) * | 2000-08-18 | 2004-04-13 | Triscend Corporation | Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory |
JP4722305B2 (en) | 2001-02-27 | 2011-07-13 | 富士通セミコンダクター株式会社 | Memory system |
KR100506062B1 (en) | 2002-12-18 | 2005-08-05 | 주식회사 하이닉스반도체 | Composite Memory Device |
US7287115B2 (en) * | 2003-10-30 | 2007-10-23 | Kabushiki Kaisha Toshiba | Multi-chip package type memory system |
JP2006004559A (en) | 2004-06-18 | 2006-01-05 | Elpida Memory Inc | Semiconductor storage device |
US7296143B2 (en) * | 2004-06-22 | 2007-11-13 | Lenovo (Singapore) Pte. Ltd. | Method and system for loading processor boot code from serial flash memory |
KR100695890B1 (en) | 2004-10-29 | 2007-03-19 | 삼성전자주식회사 | Multi-chip system and its data transfer method |
US7889571B2 (en) * | 2008-01-09 | 2011-02-15 | Unity Semiconductor Corporation | Buffering systems methods for accessing multiple layers of memory in integrated circuits |
JP4954626B2 (en) * | 2005-07-29 | 2012-06-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
KR100673013B1 (en) * | 2005-09-21 | 2007-01-24 | 삼성전자주식회사 | Memory controller and data processing system with the same |
US7519754B2 (en) * | 2005-12-28 | 2009-04-14 | Silicon Storage Technology, Inc. | Hard disk drive cache memory and playback device |
US7716411B2 (en) | 2006-06-07 | 2010-05-11 | Microsoft Corporation | Hybrid memory device with single interface |
JP4945186B2 (en) | 2006-07-28 | 2012-06-06 | 株式会社東芝 | Storage device and memory system including the same |
KR100769771B1 (en) * | 2006-09-29 | 2007-10-23 | 주식회사 하이닉스반도체 | Flash memory device and method of erasing thereof |
KR100803005B1 (en) | 2006-10-26 | 2008-02-14 | 삼성전자주식회사 | Memory interfacing method and apparatus |
KR100875293B1 (en) | 2007-02-08 | 2008-12-23 | 삼성전자주식회사 | Flash memory system can improve system performance |
US8135900B2 (en) | 2007-03-28 | 2012-03-13 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
JP5032172B2 (en) | 2007-03-28 | 2012-09-26 | 株式会社東芝 | Integrated memory management apparatus and method, and data processing system |
KR100887417B1 (en) * | 2007-04-11 | 2009-03-06 | 삼성전자주식회사 | Multi-path accessible semiconductor memory device for providing multi processor system with shared use of non volatile memory |
SG142321A1 (en) | 2008-04-24 | 2009-11-26 | Micron Technology Inc | Pre-encapsulated cavity interposer |
KR101038167B1 (en) | 2008-09-09 | 2011-05-31 | 가부시끼가이샤 도시바 | Information processing device including memory management device managing access from processor to memory and memory management method |
JP2010165251A (en) | 2009-01-16 | 2010-07-29 | Toshiba Corp | Information processing device, processor, and information processing method |
JP5343734B2 (en) * | 2009-06-26 | 2013-11-13 | 富士通株式会社 | Semiconductor memory device |
WO2011007599A1 (en) | 2009-07-17 | 2011-01-20 | 株式会社 東芝 | Memory management device |
JP2011118469A (en) | 2009-11-30 | 2011-06-16 | Toshiba Corp | Device and method for managing memory |
KR20120005826A (en) * | 2010-07-09 | 2012-01-17 | 주식회사 하이닉스반도체 | Semiconductor memory device and operation method thereof |
JP2012033001A (en) | 2010-07-30 | 2012-02-16 | Toshiba Corp | Information processing apparatus and information processing method |
JP2012033047A (en) | 2010-07-30 | 2012-02-16 | Toshiba Corp | Information processor, memory management device, memory management method and program |
TWI473110B (en) * | 2010-11-02 | 2015-02-11 | Winbond Electronics Corp | Flash memory apparatus with serial interface and rsest method thereof |
US8914569B2 (en) | 2011-02-24 | 2014-12-16 | Winbond Electronics Corp. | Flash memory apparatus with serial interface and reset method thereof |
US9170744B1 (en) | 2011-04-06 | 2015-10-27 | P4tents1, LLC | Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system |
US9158546B1 (en) | 2011-04-06 | 2015-10-13 | P4tents1, LLC | Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory |
US9164679B2 (en) | 2011-04-06 | 2015-10-20 | Patents1, Llc | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9176671B1 (en) | 2011-04-06 | 2015-11-03 | P4tents1, LLC | Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system |
US9417754B2 (en) | 2011-08-05 | 2016-08-16 | P4tents1, LLC | User interface system, method, and computer program product |
US8812744B1 (en) | 2013-03-14 | 2014-08-19 | Microsoft Corporation | Assigning priorities to data for hybrid drives |
JP2013137841A (en) * | 2013-04-12 | 2013-07-11 | Renesas Electronics Corp | Memory system |
US9626126B2 (en) | 2013-04-24 | 2017-04-18 | Microsoft Technology Licensing, Llc | Power saving mode hybrid drive access management |
CN104240756B (en) * | 2013-06-20 | 2018-08-21 | 慧荣科技股份有限公司 | Control device and access system |
KR102249416B1 (en) | 2014-06-11 | 2021-05-07 | 삼성전자주식회사 | Memory system and method of operating memory system |
KR102379166B1 (en) * | 2015-02-05 | 2022-03-25 | 삼성전자주식회사 | Electric component, semiconductor package and electronic device using the same |
US10331586B2 (en) | 2015-10-30 | 2019-06-25 | Samsung Electronics Co., Ltd. | Nonvolatile memory device for providing fast booting and system including the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4713756A (en) * | 1985-02-28 | 1987-12-15 | Westinghouse Electric Corp. | Non-volatile memory device for a programmable controller |
JPH0337897A (en) * | 1989-07-05 | 1991-02-19 | Nec Corp | Microcomputer |
JPH0460994A (en) * | 1990-06-27 | 1992-02-26 | Hitachi Ltd | Static ram, rom and information processor |
US5663901A (en) * | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
JPH0512894A (en) * | 1991-07-05 | 1993-01-22 | Mitsubishi Electric Corp | Microcomputer and its rom reading method |
JP3310011B2 (en) * | 1992-03-30 | 2002-07-29 | 株式会社東芝 | Semiconductor memory and semiconductor memory board using the same |
KR960039006A (en) * | 1995-04-26 | 1996-11-21 | 김광호 | Nonvolatile semiconductor memory device connectable to DRAM bus |
JPH09167059A (en) * | 1995-12-14 | 1997-06-24 | Sony Corp | Information recording device and information transfer device |
US6108236A (en) * | 1998-07-17 | 2000-08-22 | Advanced Technology Materials, Inc. | Smart card comprising integrated circuitry including EPROM and error check and correction system |
-
2000
- 2000-01-26 KR KR10-2000-0003708A patent/KR100383774B1/en not_active IP Right Cessation
-
2001
- 2001-01-22 JP JP2001013376A patent/JP2001266580A/en active Pending
- 2001-01-26 US US09/771,307 patent/US6456517B2/en not_active Expired - Fee Related
Cited By (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003021602A2 (en) | 2001-08-28 | 2003-03-13 | Intel Corporation | Multiple word-line accessing and accessor |
WO2003021602A3 (en) * | 2001-08-28 | 2003-12-11 | Intel Corp | Multiple word-line accessing and accessor |
CN100433188C (en) * | 2001-08-28 | 2008-11-12 | 英特尔公司 | Multiple word-line accessing and accessor |
US20030172261A1 (en) * | 2002-03-08 | 2003-09-11 | Seok-Heon Lee | System boot using NAND flash memory and method thereof |
US20070220247A1 (en) * | 2002-03-08 | 2007-09-20 | Seok-Heon Lee | System boot using nand flash memory and method thereof |
US8185728B2 (en) | 2002-03-08 | 2012-05-22 | Samsung Electronics Co., Ltd. | System boot using NAND flash memory and method thereof |
US7234052B2 (en) | 2002-03-08 | 2007-06-19 | Samsung Electronics Co., Ltd | System boot using NAND flash memory and method thereof |
EP1343082A3 (en) * | 2002-03-08 | 2007-03-28 | Samsung Electronics Co., Ltd. | System boot using nand flash memory and method thereof |
US20070211559A1 (en) * | 2002-07-29 | 2007-09-13 | Samsung Electronics Co., Ltd. | Computer system with nand flash memory for booting and storage |
EP1387284A3 (en) * | 2002-07-29 | 2005-09-07 | Samsung Electronics Co., Ltd. | Computer system with nand flash memory for booting and data storage |
EP1387284A2 (en) * | 2002-07-29 | 2004-02-04 | Samsung Electronics Co., Ltd. | Computer system with nand flash memory for booting and data storage |
CN101281494B (en) * | 2002-09-11 | 2012-04-04 | 株式会社日立制作所 | System and method for using dynamic random access memory and flash memory |
US7991954B2 (en) | 2002-11-28 | 2011-08-02 | Renesas Electronics Corporation | Memory module, memory system, and information device |
US20060041711A1 (en) * | 2002-11-28 | 2006-02-23 | Renesas Technology Corporation | Memory module, memory system, and information device |
US8185690B2 (en) | 2002-11-28 | 2012-05-22 | Renesas Electronics Corporation | Memory module, memory system, and information device |
US20100030952A1 (en) * | 2002-11-28 | 2010-02-04 | Renesas Technology Corp. | Memory Module, Memory System, and Information Device |
US7613880B2 (en) * | 2002-11-28 | 2009-11-03 | Renesas Technology Corp. | Memory module, memory system, and information device |
US7831790B2 (en) * | 2003-03-19 | 2010-11-09 | Nxp B.V. | Universal memory device having a profile storage unit |
US20060174056A1 (en) * | 2003-03-19 | 2006-08-03 | Koninklijke Philips Electronics N.V. | Universal memory device having a profil storage unit |
US20050273564A1 (en) * | 2004-06-02 | 2005-12-08 | Sridhar Lakshmanamurthy | Memory controller |
US7308526B2 (en) * | 2004-06-02 | 2007-12-11 | Intel Corporation | Memory controller module having independent memory controllers for different memory types |
WO2006085324A3 (en) * | 2005-02-11 | 2007-05-03 | Milsys Ltd | Nand flash memory system architecture |
US20080104311A1 (en) * | 2005-02-11 | 2008-05-01 | Sandisk Il Ltd. | Nand flash memory system architecture |
US8990475B2 (en) * | 2005-02-11 | 2015-03-24 | Sandisk Il Ltd. | NAND flash memory system architecture |
US9063848B2 (en) | 2005-02-11 | 2015-06-23 | Sandisk Il Ltd. | NAND flash memory system architecture |
WO2006085324A2 (en) * | 2005-02-11 | 2006-08-17 | Sandisk Il Ltd. | Nand flash memory system architecture |
US20060184724A1 (en) * | 2005-02-11 | 2006-08-17 | M-Systems Flash Disk Pioneers, Ltd. | NAND flash memory system architecture |
US20070058480A1 (en) * | 2005-09-12 | 2007-03-15 | Sang-Won Hwang | NAND flash memory device with burst read latency function |
US7609553B2 (en) * | 2005-09-12 | 2009-10-27 | Samsung Electronics Co., Ltd. | NAND flash memory device with burst read latency function |
US7734880B2 (en) * | 2006-01-24 | 2010-06-08 | Samsung Electronics Co., Ltd. | Flash memory system compensating reduction in read margin between memory cell program states |
US20070171722A1 (en) * | 2006-01-24 | 2007-07-26 | Sang-Gu Kang | Flash memory system compensating reduction in read margin between memory cell program states |
US20080046665A1 (en) * | 2006-05-24 | 2008-02-21 | Kyoung-Park Kim | Multiport Memory Device, Multiprocessor System Including the Same, and Method of Transmitting Data In Multiprocessor System |
US8161355B2 (en) * | 2009-02-11 | 2012-04-17 | Mosys, Inc. | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process |
US20100205504A1 (en) * | 2009-02-11 | 2010-08-12 | Mosys, Inc. | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process |
US20110145486A1 (en) * | 2009-12-16 | 2011-06-16 | Tsutomu Owa | Memory management device and method |
US10416932B2 (en) | 2013-04-25 | 2019-09-17 | Microsoft Technology Licensing, Llc | Dirty data management for hybrid drives |
WO2015034580A1 (en) * | 2013-09-03 | 2015-03-12 | Qualcomm Incorporated | Unified memory controller for heterogeneous memory on a multi-chip package |
CN105493061A (en) * | 2013-09-03 | 2016-04-13 | 高通股份有限公司 | Unified memory controller for heterogeneous memory on a multi-chip package |
US10185515B2 (en) | 2013-09-03 | 2019-01-22 | Qualcomm Incorporated | Unified memory controller for heterogeneous memory on a multi-chip package |
CN105493061B (en) * | 2013-09-03 | 2020-11-03 | 高通股份有限公司 | Unified memory controller for heterogeneous memory on multi-chip package |
CN111758160A (en) * | 2020-05-20 | 2020-10-09 | 长江存储科技有限责任公司 | 3D NAND flash memory device and integration method thereof |
US10963191B1 (en) | 2020-05-20 | 2021-03-30 | Yangtze Memory Technologies Co., Ltd. | 3D NAND flash memory device and integration method thereof |
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US6456517B2 (en) | 2002-09-24 |
JP2001266580A (en) | 2001-09-28 |
KR20010076518A (en) | 2001-08-16 |
KR100383774B1 (en) | 2003-05-12 |
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