US20010004387A1 - Arrangement for reducing power dissipation in a line driver - Google Patents

Arrangement for reducing power dissipation in a line driver Download PDF

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Publication number
US20010004387A1
US20010004387A1 US09/727,694 US72769400A US2001004387A1 US 20010004387 A1 US20010004387 A1 US 20010004387A1 US 72769400 A US72769400 A US 72769400A US 2001004387 A1 US2001004387 A1 US 2001004387A1
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Prior art keywords
supply
line driver
signal processor
digital signal
controllable
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Granted
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US09/727,694
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US6407578B2 (en
Inventor
Stefan Barkarö
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Telefonaktiebolaget LM Ericsson AB
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Individual
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Assigned to TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) reassignment TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BARKARO, STEFAN
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/16—Arrangements for providing special services to substations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0244—Stepped control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/504—Indexing scheme relating to amplifiers the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure
    • H04L27/2605—Symbol extensions, e.g. Zero Tail, Unique Word [UW]
    • H04L27/2607—Cyclic extensions

Definitions

  • the invention relates generally to line drivers, and more specifically to an arrangement for reducing power dissipation in line drivers connected to transmission lines in multitone systems, such as e.g. ADSL (Asymmetric Digital Subscriber Line) systems.
  • ADSL Asymmetric Digital Subscriber Line
  • a multitone system such as an ADSL-system
  • data information is randomly coded into the phase and amplitude of a plurality of sine tones that are transmitted by line drivers on transmission lines in bursts with a so-called symbol rate or length, which in the ADSL case is 246.3 ⁇ s.
  • cyclic prefix To enable Fourier transformations to be made on each symbol, a so-called cyclic prefix is inserted between the symbols.
  • the cyclic prefix does not contain any valid data but ensures that the multitone signal appears continuous for the Fourier transformation.
  • each cyclic prefix has a length of 32 samples or about 15 ⁇ s.
  • the object of the invention is to bring about an arrangement for reducing the power dissipation in such line drivers.
  • FIG. 1 schematically illustrates two successive symbols to be transmitted in an ADSL system
  • FIG. 2 is a schematic block diagram of one end of an ADSL connection with an embodiment of an arrangement according to the invention.
  • FIG. 1 schematically illustrates two successive symbols S 1 and S 2 to be transmitted in an ADSL system.
  • each symbol S 1 and S 2 is preceded by a so-called cyclic prefix CP 1 and CP 2 , respectively.
  • the symbol length is 246.3 ⁇ s, while the length of the cyclic prefix is 32 samples or about 15 ⁇ s as already mentioned.
  • the peak-to-peak value of the symbol S 1 is U 1
  • the peak-to-peak value of the symbol S 2 equals U 2 , which in FIG. 1 is supposed to be a lower value than U 1 .
  • FIG. 2 an arrangement according to the invention for reducing the power dissipation in a line driver is schematically illustrated.
  • a digital signal processor 1 is connected with its digital input/output terminals to corresponding output/input terminals of an analog front end or line driver 2 connected to a transmission line 3 for transmitting and receiving data information in the form of symbols as illustrated in FIG. 1.
  • the line driver 2 comprises a digital-to-analog converter (not shown) for converting digital signals from the digital signal processor 1 into analog signals to be transmitted as symbols in accordance with FIG. 1, and an analog-to-digital converter (not shown) for converting analog symbols received into digital signals to the digital signal processor 1 .
  • the digital signal processor 1 knows the peak value of the tones to be transmitted in each symbol.
  • the digital signal processor 1 has knowledge of the peak value U 1 in the symbol S 1 in FIG. 1 before it is transmitted to the line driver 2 as well as of the peak value U 2 in the symbol S 2 in FIG. 1.
  • the digital signal processor 1 can select the most appropriate supply voltage to the driver 2 for each symbol.
  • FIG. 2 An embodiment of an arrangement for enabling such a supply voltage selection is illustrated in FIG. 2.
  • the digital signal processor 1 is connected via a control bus 4 to a switch 5 which is adapted to apply different supply voltages SV 1 , SV 2 . . . SVn to a supply voltage input terminal 6 of the driver 2 in response to different control signals from the digital signal processor 1 on the control bus 4 .
  • the selection of the appropriate supply voltage to the driver 2 takes place during each cyclic prefix CP 1 , CP 2 , i.e. at times when no relevant information is transmitted.
  • an optimum supply voltage for the driver 2 for the next symbol to be transmitted can be selected without causing any disturbances.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Valves And Accessory Devices For Braking Systems (AREA)
  • Transmitters (AREA)

Abstract

To reduce power dissipation in a line driver (2) connected to a transmission line (3) for transmitting multitone signals in the form of successive symbols separated by cyclic prefixes, generated by a digital signal processor (1), a controllable voltage supply (5) is connected with its output terminal to a supply voltage terminal (6) of the line driver (2) to supply a controllable supply voltage thereto, and with its control input terminal to a control output terminal of the digital signal processor (1). In response to an expected peak-to-peak value of the next symbol to be transmitted, the digital signal processor (1) controls the controllable voltage supply (5) during each cyclic prefix to set the supply voltage to the line driver (2).

Description

    TECHNICAL FIELD
  • The invention relates generally to line drivers, and more specifically to an arrangement for reducing power dissipation in line drivers connected to transmission lines in multitone systems, such as e.g. ADSL (Asymmetric Digital Subscriber Line) systems. [0001]
    • BACKGROUND OF THE INVENTION
  • In a multitone system, such as an ADSL-system, data information is randomly coded into the phase and amplitude of a plurality of sine tones that are transmitted by line drivers on transmission lines in bursts with a so-called symbol rate or length, which in the ADSL case is 246.3 μs. [0002]
  • To enable Fourier transformations to be made on each symbol, a so-called cyclic prefix is inserted between the symbols. The cyclic prefix does not contain any valid data but ensures that the multitone signal appears continuous for the Fourier transformation. [0003]
  • In the ADSL case, each cyclic prefix has a length of 32 samples or about 15 μs. [0004]
  • Since the phase and amplitude of each individual tone can be seen as random and the total signal consists of a sum of many tones, there will be a great difference between successive symbols in the peak-to-peak voltage of the total signal that is to be transmitted. [0005]
  • In view hereof, in normal ADSL systems, the supply voltage of the line drivers that are connected to the transmission line for transmitting such multitone signals must be selected such that the theoretical maximum peak can be transmitted without being clipped. [0006]
  • This causes the supply voltage of the line driver to be far too high for the majority of the symbols that are transmitted. [0007]
  • Consequently, the power dissipation in the line driver will be higher than necessary for most of the symbols. [0008]
    • SUMMARY OF THE INVENTION
  • The object of the invention is to bring about an arrangement for reducing the power dissipation in such line drivers. [0009]
  • This is attained essentially in that the supply voltage to the line driver is controlled from symbol to symbol during the cyclic prefixes in response to a known expected peak-to-peak value of the next symbol to be transmitted. [0010]
  • By adapting the supply voltage to expected peak-to-peak values, the power dissipation will be reduced in the line driver. [0011]
    • BRIEF DESCRIPTION OF THE DRAWING
  • The invention will be described more in detail below with reference to the appended drawing, on which FIG. 1 schematically illustrates two successive symbols to be transmitted in an ADSL system, and FIG. 2 is a schematic block diagram of one end of an ADSL connection with an embodiment of an arrangement according to the invention. [0012]
    • DESCRIPTION OF THE INVENTION
  • FIG. 1 schematically illustrates two successive symbols S[0013] 1 and S2 to be transmitted in an ADSL system.
  • In a manner known per se, each symbol S[0014] 1 and S2, is preceded by a so-called cyclic prefix CP1 and CP2, respectively.
  • In ADSL systems, the symbol length is 246.3 μs, while the length of the cyclic prefix is 32 samples or about 15 μs as already mentioned. [0015]
  • In FIG. 1, the peak-to-peak value of the symbol S[0016] 1 is U1, while the peak-to-peak value of the symbol S2 equals U2, which in FIG. 1 is supposed to be a lower value than U1.
  • Today, the symbols S[0017] 1 and S2 illustrated in FIG. 1 are transmitted by a line driver having a constant supply voltage even if they actually do not require the same supply voltage in order to be transmitted without being clipped.
  • Thus, unnecessary power is consumed today in such line drivers. [0018]
  • In FIG. 2, an arrangement according to the invention for reducing the power dissipation in a line driver is schematically illustrated. [0019]
  • In FIG. 2, a [0020] digital signal processor 1 is connected with its digital input/output terminals to corresponding output/input terminals of an analog front end or line driver 2 connected to a transmission line 3 for transmitting and receiving data information in the form of symbols as illustrated in FIG. 1.
  • In a manner known per se, the [0021] line driver 2 comprises a digital-to-analog converter (not shown) for converting digital signals from the digital signal processor 1 into analog signals to be transmitted as symbols in accordance with FIG. 1, and an analog-to-digital converter (not shown) for converting analog symbols received into digital signals to the digital signal processor 1.
  • Also in a manner known per se, the [0022] digital signal processor 1 knows the peak value of the tones to be transmitted in each symbol.
  • Thus, the [0023] digital signal processor 1 has knowledge of the peak value U1 in the symbol S1 in FIG. 1 before it is transmitted to the line driver 2 as well as of the peak value U2 in the symbol S2 in FIG. 1.
  • With this knowledge, the [0024] digital signal processor 1 can select the most appropriate supply voltage to the driver 2 for each symbol.
  • An embodiment of an arrangement for enabling such a supply voltage selection is illustrated in FIG. 2. [0025]
  • In the embodiment in FIG. 2, the [0026] digital signal processor 1 is connected via a control bus 4 to a switch 5 which is adapted to apply different supply voltages SV1, SV2 . . . SVn to a supply voltage input terminal 6 of the driver 2 in response to different control signals from the digital signal processor 1 on the control bus 4.
  • It should be pointed out in this connection that the different supply voltages do not have to be fixed and be applied by means of a switch but can be supplied e.g. by a controllable DC/DC converter (not shown). [0027]
  • Anyhow, in accordance with the invention, the selection of the appropriate supply voltage to the [0028] driver 2 takes place during each cyclic prefix CP1, CP2, i.e. at times when no relevant information is transmitted.
  • Thus, during each cyclic prefix, an optimum supply voltage for the [0029] driver 2 for the next symbol to be transmitted can be selected without causing any disturbances.
  • By optimizing the supply voltage for each symbol, the total power dissipation of the [0030] driver 2 can be considerably reduced.

Claims (4)

1. An arrangement for reducing power dissipation in a line driver (2) connected to a transmission line (3) for transmitting multitone signals in the form of successive symbols (S1, S2) separated by cyclic prefixes (CP1, CP2), generated by a digital signal processor (1), characterized in that it comprises a controllable voltage supply (5) having an output terminal and a control input terminal, the output terminal of the controllable voltage supply (5) being connected to a supply voltage terminal (6) of the line driver (2) to supply a controllable supply voltage thereto, and the control input terminal of the controllable voltage supply (5) being connected to a control output terminal of the digital signal processor (1), the digital signal processor (1) being adapted to control the controllable voltage supply (5) during each cyclic prefix (CP1, CP2) to control the supply voltage to the line driver (2) in response to an expected peak-to-peak value of the next symbol to be transmitted.
2. The arrangement according to
claim 1
, characterized in that the controllable voltage supply (5) is connected to the digital signal processor (1) via a control bus (4).
3. The arrangement according to
claim 1
 or
2
, characterized in that the controllable voltage supply comprises a switch (5) which is adapted to apply different supply voltages (SV1, SV2 . . . SVn) to the line driver (2) in response to different expected peak-to-peak values of the symbols to be transmitted.
4. The arrangement according to
claim 1
 or
2
, characterized in that the controllable voltage supply comprises a DC/DC converter controlled by the digital signal processor (1).
US09/727,694 1999-12-17 2000-12-04 Arrangement for reducing power dissipation in a line driver Expired - Lifetime US6407578B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9904642-7 1999-12-17
SE9904642A SE517622C2 (en) 1999-12-17 1999-12-17 Device for reducing the power loss of a line driver
SE9904642 1999-12-17

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US20010004387A1 true US20010004387A1 (en) 2001-06-21
US6407578B2 US6407578B2 (en) 2002-06-18

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US (1) US6407578B2 (en)
EP (1) EP1243109B1 (en)
JP (1) JP2003517772A (en)
KR (1) KR100726210B1 (en)
CN (1) CN1180588C (en)
AT (1) ATE334541T1 (en)
AU (1) AU1428301A (en)
DE (1) DE60029632T2 (en)
HK (1) HK1055038A1 (en)
SE (1) SE517622C2 (en)
TW (1) TW466844B (en)
WO (1) WO2001045336A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004019486A1 (en) * 2002-08-21 2004-03-04 Siemens Aktiengesellschaft A power amplifier system
US20090285327A1 (en) * 2006-06-23 2009-11-19 Panasonic Corporation Radio transmitting apparatus, radio receiving apparatus, and pilot generating method
US7746921B1 (en) * 2005-10-11 2010-06-29 Thomas Robert Wik Resonant digital data transmission
US20100253420A1 (en) * 2009-04-07 2010-10-07 Futurewei Technologies, Inc. Power Efficiency of a Line Driver
US20100321115A1 (en) * 2009-06-17 2010-12-23 Futurewei Technologies, Inc. Class-G Line Driver Control Signal
US20150098845A1 (en) * 2012-05-08 2015-04-09 Sanden Corporation Fluid Machinery
US20170051739A1 (en) * 2014-02-28 2017-02-23 Fujitsu General Limited Rotary compressor

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10135993A1 (en) * 2001-07-24 2003-05-08 Siemens Ag Method for reducing the power loss in linear amplifiers and associated device
EP1458115A1 (en) * 2003-03-10 2004-09-15 Alcatel Attenuator for ADSL signals
US7863935B2 (en) * 2008-02-21 2011-01-04 Trendchip Technologies Corporation Line driver architecture for 10/100/1000 BASE-T Ethernet
TWI705672B (en) * 2018-05-02 2020-09-21 大陸商貴州濎通芯物聯技術有限公司 Orthogonal frequency division multiplex line driver system

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
JPH06334541A (en) * 1993-05-25 1994-12-02 Sony Corp Radio transmitter
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
US5781617A (en) * 1996-03-29 1998-07-14 Netspeed, Inc. Communication server apparatus using frequency multiplexing and method
US6028486A (en) * 1997-10-07 2000-02-22 Telefonaktiebolaget Lm Ericsson Method and apparatus for reducing power dissipation in multi-carrier amplifiers
US6163706A (en) * 1997-11-18 2000-12-19 Conexant Systems, Inc. Apparatus for and method of improving efficiency of transceivers in radio products
JP3541674B2 (en) * 1998-04-24 2004-07-14 日本ビクター株式会社 Multicarrier signal generation method and transmission device
CA2279477A1 (en) * 1999-07-30 2001-01-30 Robert Bisson Crest factor compensated driver

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004019486A1 (en) * 2002-08-21 2004-03-04 Siemens Aktiengesellschaft A power amplifier system
US20050242880A1 (en) * 2002-08-21 2005-11-03 John Domokos Power amplifier system
US7746921B1 (en) * 2005-10-11 2010-06-29 Thomas Robert Wik Resonant digital data transmission
US20090285327A1 (en) * 2006-06-23 2009-11-19 Panasonic Corporation Radio transmitting apparatus, radio receiving apparatus, and pilot generating method
US9155024B2 (en) * 2006-06-23 2015-10-06 Panasonic Intellectual Property Corporation Of America Radio transmitting apparatus, radio receiving apparatus, and pilot generating method
US20100253420A1 (en) * 2009-04-07 2010-10-07 Futurewei Technologies, Inc. Power Efficiency of a Line Driver
US8693676B2 (en) 2009-04-07 2014-04-08 Futurewei Technologies, Inc. Power efficiency of a line driver
US9036813B2 (en) 2009-04-07 2015-05-19 Futurewei Technologies, Inc. Power efficiency of a line driver
US20100321115A1 (en) * 2009-06-17 2010-12-23 Futurewei Technologies, Inc. Class-G Line Driver Control Signal
US8446219B2 (en) 2009-06-17 2013-05-21 Futurewei Technologies, Inc. Class-G line driver control signal
US20150098845A1 (en) * 2012-05-08 2015-04-09 Sanden Corporation Fluid Machinery
US20170051739A1 (en) * 2014-02-28 2017-02-23 Fujitsu General Limited Rotary compressor

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AU1428301A (en) 2001-06-25
HK1055038A1 (en) 2003-12-19
US6407578B2 (en) 2002-06-18
EP1243109B1 (en) 2006-07-26
WO2001045336A1 (en) 2001-06-21
CN1180588C (en) 2004-12-15
EP1243109A1 (en) 2002-09-25
SE517622C2 (en) 2002-06-25
SE9904642D0 (en) 1999-12-17
DE60029632T2 (en) 2007-07-26
ATE334541T1 (en) 2006-08-15
SE9904642L (en) 2001-06-18
TW466844B (en) 2001-12-01
JP2003517772A (en) 2003-05-27
KR20020064922A (en) 2002-08-10
KR100726210B1 (en) 2007-06-11
DE60029632D1 (en) 2006-09-07
CN1411648A (en) 2003-04-16

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