US20010003678A1 - Oxide plasma etching process with a controlled wineglass shape - Google Patents

Oxide plasma etching process with a controlled wineglass shape Download PDF

Info

Publication number
US20010003678A1
US20010003678A1 US09/121,190 US12119098A US2001003678A1 US 20010003678 A1 US20010003678 A1 US 20010003678A1 US 12119098 A US12119098 A US 12119098A US 2001003678 A1 US2001003678 A1 US 2001003678A1
Authority
US
United States
Prior art keywords
etching
etch
hole
dielectric layer
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/121,190
Other versions
US6355557B2 (en
Inventor
James A. Stinnett
Cynthia B. Brooks
Walter R. Merry
Jason Regis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/121,190 priority Critical patent/US6355557B2/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BROOKS, CYNTHIA B., REGIS, JASON, STINNETT, JAMES A., MERRY, WALTER R.
Publication of US20010003678A1 publication Critical patent/US20010003678A1/en
Application granted granted Critical
Publication of US6355557B2 publication Critical patent/US6355557B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Definitions

  • the invention relates generally to a plasma etching process.
  • it relates to a process for etching into silicon oxide an aperture having a complex shape.
  • each wiring level includes an inter-level insulating layer 10 interposed between a lower layer 12 and a metallic upper layer.
  • the insulating layer 10 is formed of silicon dioxide or related silica glasses, both hereinafter referred to as an oxide.
  • the lower layer 12 may be the silicon substrate in which is already formed various types of semiconductor devices that need to be contacted.
  • the lower layer 12 may be a lower wiring layer which is already formed into a lower interconnect pattern.
  • the upper metal layer 14 is eventually formed into its own interconnect wiring pattern.
  • the interconnect metal is usually aluminum or an aluminum alloy although its composition is not directly related to the present invention.
  • the deposition of the upper metal layer 14 includes deposition of the same metal into an aperture 16 preformed in the oxide layer 10 .
  • This invention is directed to the etching of that aperture 16 .
  • the aperture 16 is referred to as a contact hole, and extra care must be exercised to not degrade the semiconducting characteristics of the underlying layer 12 .
  • the aperture 16 is referred to as a via hole.
  • the via or contact holes 16 have been required to become narrower and more vertically anisotropic, that is, to have a high aspect ratio of depth to width.
  • a typical method uses a fluorocarbon or hydrofluorocarbon etching gas in an argon carrier gas and applies an RF bias to the pedestal supporting the wafer.
  • the RF bias creates a DC electrical self-bias in the plasma adjacent to the wafer, and the DC field accelerates the etching ions or an inactive carrier gas ions towards the wafer in a vertical flux pattern.
  • the resulting etching if properly controlled, is highly anisotropic with oxide holes 16 having aspect ratios of five or even more being attainable.
  • this anisotropic inter-level etch has at least two problems.
  • very highly anisotropic etching often requires the use of high-density plasma reactors, often using inductive coupling of RF energy into plasma source region of the etch reactor as well as the capacitive coupling of RF energy onto the pedestal to create the DC self-bias.
  • the recently developed high-density plasma reactors are expensive.
  • the filling of the metal layer 14 into a narrow and deep hole 16 becomes problematic. Sputter deposition of the metal tends to bridge the top of a rectangular hole 16 before it is filled, thus creating a void in the contact or via. Methods are available to fill such a narrow and deep hole, but again these methods are complex and often require expensive metal deposition equipment.
  • the contact or via needs to be narrow at its bottom but the spacing is more relaxed at its top.
  • the resolution required of wiring patterns decreases in the upper wiring layers.
  • a wine-glass etch pattern as illustrated in FIG. 1, has been developed.
  • the hole includes a highly anisotropic lower portion 18 (referred to as the stem) and a wider upper portion 20 (referred to as the bowl).
  • One way of forming the wine glass is to cover the oxide layer 10 with a patterned mask layer 22 having an mask aperture 24 generally conforming to the area of the stem 18 and the desired area of the contact to the substrate 10 .
  • a first etching step uses an isotropic etch which not only etches downwardly in the area beneath the mask aperture 24 but also etches sidewardly to undercut the mask layer.
  • the generally isotropic etch can be performed in a plasma reactor without significant RF biasing of the pedestal or with a remote plasma source (RPS). As the figure shows, the isotropic etch with RPS actually etches somewhat more laterally than vertically.
  • the lateral-to-vertical ratio depends on the density and dopant level of the material being etched. Less dense, highly doped materials etch with L/V ratios near or below 1.0 while dense, undoped films etch with L/V ratios ranging from 1.3 to 2.0.
  • the structure is anisotropically etched through the oxide layer 10 to the underlying layer 12 , as described above, to form the stem 18 underlying the mask aperture.
  • the metal layer 14 is then sputtered to fill the wineglass-shaped hole 16 .
  • the aspect ratio of the stem portion 18 of the hole 16 is significantly less than a substantially vertical hole 16 extending all the way from the surface of the oxide 10 , thus not requiring complex and expensive etch equipment or alternatively an etching chemistry requiring precise control in a commercial environment. Also, metal filling of the wine-glass hole 16 is also more easily accomplished, thus simplifying that step as well.
  • the depth of the bowl 20 should be maintained relatively large so as to promote metal filling of the narrow stem 18 .
  • the invention may be summarized as a three-step wine-glass etch process with a common mask.
  • an anisotropic etch is performed to a depth determining the vertical dimension of the bowl of the wine glass.
  • an isotropic etch is performed to achieve the desired lateral extent. The isotropic etch will further increase the depth of the bowl.
  • another anisotropic etch is performed to etch the stem of the wineglass down to the underlying layer.
  • FIG. 1 is a cross-sectional view of a wineglass contact or via hole through an oxide layer after the metal filling step.
  • FIG. 2 is a cross-sectional view of the process conventionally used in etching the bowl of the wineglass.
  • FIG. 3 is a process flow diagram for practicing one embodiment of the invention.
  • FIGS. 4, 5, 6 , and 7 are cross-sectional view illustrating the steps in processing the wineglass hole of the invention.
  • FIG. 8 is a cross-sectional view of a remote plasma-source (RPS) etch reactor usable with the invention.
  • RPS remote plasma-source
  • the invention allows the independent control of the lateral and vertical dimensions of the etching of the bowl in a wineglass etch.
  • the process summarized in the flow chart of FIG. 3, creates the structure sequentially developed in the cross-sectional views of FIGS. 4 through 7.
  • the photoresist layer 22 illustrated in the cross-sectional view of FIG. 4 is deposited on the oxide layer 10 and is photographically patterned to have an aperture 24 extending to the underlying oxide 10 in the area of the intended contact hole.
  • the size of the aperture 24 is generally of the same cross section as the wineglass stem that will extend to the substrate 12 .
  • a first, anisotropic etch step 28 of FIG. 3 is used to form a shallow hole 30 in the oxide layer 10 , illustrated in FIG. 5, not extending downwardly as far as the intended bottom of the bowl.
  • This is not an aggressive etch, and a capacitively coupled, magnetically enhanced etch reactor, such as the MXP + available from Applied Materials, Inc. of Santa Clara, Calif. can be used for this etch.
  • MXP + reactor the wafer rests on a cathode pedestal connected to an RF power supply, and the counter-electrode is grounded. Additionally, electromagnetic coils induce a nearly static horizontal magnetic field in the volume between the electrode.
  • This type of reactor is referred to as a magnetically enhanced reactive ion etcher (MERIE) and can be effectively used for anisotropic etching.
  • MXP + reactor the wafer rests on a cathode pedestal connected to an RF power supply, and the counter-electrode is grounded. Additionally, electromagnetic coils induce a nearly static
  • the process parameters presented in TABLE 1 were used in an MXP + reactor with the aperture 24 of the mask having a width of about 0.9 ⁇ m and with the thickness of the oxide layer 10 being about 0.4 ⁇ m, but in different applications the thickness may range up to 1.2 ⁇ m.
  • TABLE 1 Pressure 200 mTorr Cathode Power 700 W Magnetic Field 30 gauss Cathode Temperature 15° C. Wall Temperature 15° C. Helium Cooling 14 Torr Ar Flow 150 sccm CF 4 Flow 15 sccm CHF 3 Flow 45 sccm Etch Time 12 sec
  • a second, isotropic etch step 32 of FIG. 3 then enlarges the shallow hole 30 into a wider and deeper hole 36 shown in FIG. 6.
  • the isotropic etch forms undercuts 38 beneath the photomask 22 and also forms curved bottom corners 40 in the oxide layer 10 .
  • Bird's beaks 42 are likely to form at the interface between the oxide 10 and the photomask 22 .
  • the enlarged hole 36 forms the bowl of the wineglass shape.
  • the isotropic etch completes the formation of the bowl of the wineglass.
  • the extent of the isotropic etch particularly as determined by the isotropic etching period, determines the lateral dimension of the wineglass etch.
  • the isotropic etch also deepens the bowl by an amount determined by the period of the isotropic etch. That isotropically etched depth needs to be added to the anisotropically etched depth of the first step in determining the total depth. Nonetheless, the extents of the isotropic and anisotropic etches can be varied in combination for a desired lateral-to-vertical ratio.
  • a third, anisotropic etch 46 of FIG. 3 etches through the oxide layer 10 , as illustrated in FIG. 7, in an area mostly defined by the aperture 24 in the photomask 22 .
  • the etch forms an aperture 48 extending down to the underlying substrate 12 , and the etched volume corresponds to the stem of the wineglass shape.
  • the third etch may be the most demanding one since it may require the etching of a hole with a high aspect ratio, and further it is desirous that the etch be selective to the underlying material.
  • the large lateral extent of the bowl area 36 lessens the severity of the geometry of deep hole etching. Such etches are well known.
  • the third etch 46 can have the same conditions as the first etch 28 , as listed in TABLE 1. The same conditions apply to both etching a contact hole over silicon or etching a via hole over a metal. Using the same reactor for the first and third etch steps and an RPS reactor for the second etch step improves throughput since the two reactors are easily included on the same platform.
  • the isotropic etch can be accomplished by a variety of methods, even if the etching is restricted to the preferred plasma dry etching.
  • the MXP + chamber can be used for a nearly isotropic etching by using a non-polymer-former chemistry, such as the CF 4 +NF 3 +O 2 chemistry of TABLE 2.
  • a similar chemistry uses SF 6 in place of the NF 3 . In these two chemistries, any carbon left from the etching is oxidized by the O 2 to form CO 2 , which is then vented from the system. Chamber pressures can range from 300 mTorr to 3 Torr. For a more isotropic etch, typically no bias is applied to the pedestal, and no magnetic field is applied to the plasma.
  • MXP + would produce a tapered etch rather than a curved isotropic etch.
  • HDP inductively coupled high-density plasma
  • RPS remote plasma-source
  • An RPS etch chamber is illustrated in the schematic cross section of FIG. 8.
  • a vacuum chamber 60 contains a pedestal 62 having an electrostatic chuck on its upper surface for selectively clamping a wafer 64 .
  • An unillustrated vacuum pumping system pumps the chamber 60 through a throttle valve 70 .
  • Processing gas is admitted to an upper cavity 72 in the chamber 60 through a microwave applicator 74 .
  • the processing gas in the upper cavity is uniformly distributed to the processing area over the wafer 64 through a gas distribution plate 78 having a plurality of narrow holes 80 through it for passing the processing gas.
  • a magnetron 84 supplies microwave power in the gigahertz range through a microwave waveguide 86 to the applicator 74 .
  • An autotuner 88 on the waveguide 86 adjusts the microwave impedance for varying plasma conditions.
  • the microwave power applied to the applicator 74 excites into a plasma the processing gas flowing through the applicator 74 , and the excited gas flows through the gas distribution plate 78 to the processing area. Because of the distances involved, the plasma is mostly in the form of neutral radicals. In this chamber, there is no additional plasma generating equipment in the vacuum chamber 60 , and no bias is applied to the pedestal 62 . As a result, the excited gas plasma etching the wafer 64 does so without any directional acceleration across a plasma sheath, and the resulting etch is both soft and isotropic.
  • An RPS etcher is relatively inexpensive and is easy to operate and maintain so that a three-step, two-chamber etch is not that much more expensive than a single-chamber etch.
  • a two-step, single-chamber etch for the latter two steps according to the invention can be performed in an MXP + chamber by first setting the chamber process conditions to conditions favoring an isotropic etch by increasing the pressure, reducing the bias, and lowering the power. Then the chamber process conditions are set to conditions favoring anisotropic etching, such as using a chemistry similar to that of TABLE 1. It is also possible to add a remote plasma source to a capacitively or inductively coupled plasma reactor, e.g., the MXP + . The combination chamber can then be operated in either the isotropic RPS mode or the anisotropic local plasma mode or a combination of the two.
  • the pedestal bias and argon flow can be reduced from those values listed in TABLE 1, but still have finite values.
  • the flow polymer former CHF 3 can be increased. This approach is particularly applicable to L/V values of less than unity.
  • the etch conditions are optimized to produce side wall angles of greater than 85°, and preferably close to 90°, the ultimate in anisotropy. It is known that other conditions produce an etch of less anisotropy, for example, producing side walls angles of significantly less than 90°, say 60°. While such an etch is not isotropic, it combines the characteristic of a strongly anisotropic etch and an isotropic etch.
  • a strongly anisotropic etching profile may be defined as one producing a side wall angle of greater than 80°.
  • more than two processing conditions producing differing anisotropy may be used in forming the bowl, for example, three or more steps producing decreasing anisotropy in etching the oxide, so as to tailor the curve of the bowl as well as the overall L/V ratio.
  • the invention has been applied to an oxide layer, the invention can also be applied to other dielectric layers, such as carbon-based dielectrics which may be used for their low dielectric constants.
  • the invention provides additional control over the shape of a hole etched into an oxide layer, particularly in a wineglass etch for a contact or via. Nonetheless, the additional control is achieved with either the use of an additional low-cost chamber or by using the same plasma etch reactor under a number of different conditions.

Abstract

An oxide etching method, particularly applicable to forming through an oxide layer a wineglass shaped contact or via hole of controlled shape. The wineglass hole is particularly useful for eased metal hole filling. The bowl is etched by first etching an anisotropic hole through a mask aperture, and then isotropically etching through the same mask aperture. The relative periods of the anisotropic and isotropic etch determine the lateral-to-vertical dimensions of the bowl. The stem is then etched through the same mask aperture with a strongly anisotropic etch. The isotropic etch may be performed in the same chamber as the anisotropic etch or may advantageously be performed in a separate etch chamber having a remote plasma source.

Description

    FIELD OF THE INVENTION
  • The invention relates generally to a plasma etching process. In particular, it relates to a process for etching into silicon oxide an aperture having a complex shape. [0001]
  • BACKGROUND ART
  • The continuing development of silicon-based integrated circuits has integrated an ever increasing number of semiconductor devices on a single chip. The number is approaching tens of millions, and is still growing. This level of integration has been accomplished in part by ever more complex structures and processes. [0002]
  • One such structure is the inter-level via or contact. To electrically interconnect the tens of millions of devices requires a multi-layer wiring structure. In somewhat regularly arranged memories, two or more wiring layers are needed, while in the more irregularly arranged logic devices five or more wiring layers are currently needed. As illustrated in the cross-sectional view of FIG. 1, each wiring level includes an [0003] inter-level insulating layer 10 interposed between a lower layer 12 and a metallic upper layer. Typically, the insulating layer 10 is formed of silicon dioxide or related silica glasses, both hereinafter referred to as an oxide. The lower layer 12 may be the silicon substrate in which is already formed various types of semiconductor devices that need to be contacted. Alternatively, the lower layer 12 may be a lower wiring layer which is already formed into a lower interconnect pattern. The upper metal layer 14 is eventually formed into its own interconnect wiring pattern. The interconnect metal is usually aluminum or an aluminum alloy although its composition is not directly related to the present invention.
  • Usually, the deposition of the [0004] upper metal layer 14 includes deposition of the same metal into an aperture 16 preformed in the oxide layer 10. This invention is directed to the etching of that aperture 16. If the underlying layer is silicon or polysilicon, the aperture 16 is referred to as a contact hole, and extra care must be exercised to not degrade the semiconducting characteristics of the underlying layer 12. If the underlying layer is a metal or polysilicon interconnect, the aperture 16 is referred to as a via hole. As the level of integration has increased, the via or contact holes 16 have been required to become narrower and more vertically anisotropic, that is, to have a high aspect ratio of depth to width. Methods for forming highly anisotropic contact and via holes 16 in an oxide have been developed for use in a plasma reactor. A typical method uses a fluorocarbon or hydrofluorocarbon etching gas in an argon carrier gas and applies an RF bias to the pedestal supporting the wafer. The RF bias creates a DC electrical self-bias in the plasma adjacent to the wafer, and the DC field accelerates the etching ions or an inactive carrier gas ions towards the wafer in a vertical flux pattern. The resulting etching, if properly controlled, is highly anisotropic with oxide holes 16 having aspect ratios of five or even more being attainable.
  • However, this anisotropic inter-level etch has at least two problems. First, very highly anisotropic etching often requires the use of high-density plasma reactors, often using inductive coupling of RF energy into plasma source region of the etch reactor as well as the capacitive coupling of RF energy onto the pedestal to create the DC self-bias. The recently developed high-density plasma reactors are expensive. Secondly, the filling of the [0005] metal layer 14 into a narrow and deep hole 16 becomes problematic. Sputter deposition of the metal tends to bridge the top of a rectangular hole 16 before it is filled, thus creating a void in the contact or via. Methods are available to fill such a narrow and deep hole, but again these methods are complex and often require expensive metal deposition equipment.
  • In some structures, the contact or via needs to be narrow at its bottom but the spacing is more relaxed at its top. Typically, the resolution required of wiring patterns decreases in the upper wiring layers. To take advantage of these differing requirements, a wine-glass etch pattern, as illustrated in FIG. 1, has been developed. The hole includes a highly anisotropic lower portion [0006] 18 (referred to as the stem) and a wider upper portion 20 (referred to as the bowl).
  • One way of forming the wine glass, as partially illustrated in the cross-sectional view of FIG. 2, is to cover the [0007] oxide layer 10 with a patterned mask layer 22 having an mask aperture 24 generally conforming to the area of the stem 18 and the desired area of the contact to the substrate 10. A first etching step uses an isotropic etch which not only etches downwardly in the area beneath the mask aperture 24 but also etches sidewardly to undercut the mask layer. The generally isotropic etch can be performed in a plasma reactor without significant RF biasing of the pedestal or with a remote plasma source (RPS). As the figure shows, the isotropic etch with RPS actually etches somewhat more laterally than vertically. Typically, the lateral-to-vertical ratio (L/V) depends on the density and dopant level of the material being etched. Less dense, highly doped materials etch with L/V ratios near or below 1.0 while dense, undoped films etch with L/V ratios ranging from 1.3 to 2.0. After the desired depth of the bowl 20 has been etched in the oxide 10, the structure is anisotropically etched through the oxide layer 10 to the underlying layer 12, as described above, to form the stem 18 underlying the mask aperture. The metal layer 14 is then sputtered to fill the wineglass-shaped hole 16.
  • The aspect ratio of the [0008] stem portion 18 of the hole 16 is significantly less than a substantially vertical hole 16 extending all the way from the surface of the oxide 10, thus not requiring complex and expensive etch equipment or alternatively an etching chemistry requiring precise control in a commercial environment. Also, metal filling of the wine-glass hole 16 is also more easily accomplished, thus simplifying that step as well.
  • Nonetheless, standard wine-glass oxide etching has its problems. For a given size of [0009] mask aperture 24, there is only a limited range with the described isotropic etch to control the ratio of the vertical and horizontal dimensions of the bowl 20. The L/V ratio can be controlled with the RPS chamber by varying control parameters such as cathode temperature, the ratio of O2/CF4 (or other fluorine containing gas), and pressure. However, a typically attainable L/V range is limited to about ±20% with these control parameters. Furthermore, the parameters needed to reduce the L/V ratio substantially reduce the etch rate. Generally, in the conventional processes, the lateral dimension of the bowl 20 tends to be too large, particularly as the spacing between contacts continues to decrease. Nonetheless, the depth of the bowl 20 should be maintained relatively large so as to promote metal filling of the narrow stem 18. Thus, it is desired to reduce the ratio of lateral to vertical etching in the bowl etch. Furthermore, to optimize an integrated process of etching and filling, it is desired to be able to control the lateral-to-vertical ratio as well as to more finely control the shape of the bowl. Such control is not directly available in the processes of the prior art.
  • SUMMARY OF THE INVENTION
  • The invention may be summarized as a three-step wine-glass etch process with a common mask. In the first step, an anisotropic etch is performed to a depth determining the vertical dimension of the bowl of the wine glass. In the second step, an isotropic etch is performed to achieve the desired lateral extent. The isotropic etch will further increase the depth of the bowl. In the third step, another anisotropic etch is performed to etch the stem of the wineglass down to the underlying layer. [0010]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a wineglass contact or via hole through an oxide layer after the metal filling step. [0011]
  • FIG. 2 is a cross-sectional view of the process conventionally used in etching the bowl of the wineglass. [0012]
  • FIG. 3 is a process flow diagram for practicing one embodiment of the invention. [0013]
  • FIGS. 4, 5, [0014] 6, and 7 are cross-sectional view illustrating the steps in processing the wineglass hole of the invention.
  • FIG. 8 is a cross-sectional view of a remote plasma-source (RPS) etch reactor usable with the invention. [0015]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The invention allows the independent control of the lateral and vertical dimensions of the etching of the bowl in a wineglass etch. The process, summarized in the flow chart of FIG. 3, creates the structure sequentially developed in the cross-sectional views of FIGS. 4 through 7. [0016]
  • In a [0017] photomasking step 26 of FIG. 3, the photoresist layer 22 illustrated in the cross-sectional view of FIG. 4 is deposited on the oxide layer 10 and is photographically patterned to have an aperture 24 extending to the underlying oxide 10 in the area of the intended contact hole. The size of the aperture 24 is generally of the same cross section as the wineglass stem that will extend to the substrate 12.
  • A first, [0018] anisotropic etch step 28 of FIG. 3 is used to form a shallow hole 30 in the oxide layer 10, illustrated in FIG. 5, not extending downwardly as far as the intended bottom of the bowl. This is not an aggressive etch, and a capacitively coupled, magnetically enhanced etch reactor, such as the MXP+available from Applied Materials, Inc. of Santa Clara, Calif. can be used for this etch. In the MXP+reactor, the wafer rests on a cathode pedestal connected to an RF power supply, and the counter-electrode is grounded. Additionally, electromagnetic coils induce a nearly static horizontal magnetic field in the volume between the electrode. This type of reactor is referred to as a magnetically enhanced reactive ion etcher (MERIE) and can be effectively used for anisotropic etching.
  • In one example of the invention, the process parameters presented in TABLE 1 were used in an MXP[0019] +reactor with the aperture 24 of the mask having a width of about 0.9 μm and with the thickness of the oxide layer 10 being about 0.4 μm, but in different applications the thickness may range up to 1.2 μm.
    TABLE 1
    Pressure 200 mTorr
    Cathode Power 700 W
    Magnetic Field 30 gauss
    Cathode Temperature 15° C.
    Wall Temperature 15° C.
    Helium Cooling
    14 Torr
    Ar Flow 150 sccm
    CF4 Flow 15 sccm
    CHF3 Flow 45 sccm
    Etch Time
    12 sec
  • A second, [0020] isotropic etch step 32 of FIG. 3 then enlarges the shallow hole 30 into a wider and deeper hole 36 shown in FIG. 6. The isotropic etch forms undercuts 38 beneath the photomask 22 and also forms curved bottom corners 40 in the oxide layer 10. Bird's beaks 42 are likely to form at the interface between the oxide 10 and the photomask 22. The enlarged hole 36 forms the bowl of the wineglass shape.
  • In the example of the invention, the process parameters used in an RPS etch chamber, to be described later, are listed in TABLE 2. [0021]
    TABLE 2
    Pressure 2 Torr
    Power 1400 W
    Cathode Temperature 100° C.
    Wall Temperature 65° C.
    Helium Cooling 8 Torr
    CF4 Flow 824 sccm
    NF3 Flow 412 sccm
    O2 Flow 264 sccm
    Etch Time
    40 sec
  • The isotropic etch completes the formation of the bowl of the wineglass. The extent of the isotropic etch, particularly as determined by the isotropic etching period, determines the lateral dimension of the wineglass etch. The isotropic etch also deepens the bowl by an amount determined by the period of the isotropic etch. That isotropically etched depth needs to be added to the anisotropically etched depth of the first step in determining the total depth. Nonetheless, the extents of the isotropic and anisotropic etches can be varied in combination for a desired lateral-to-vertical ratio. [0022]
  • A third, [0023] anisotropic etch 46 of FIG. 3 etches through the oxide layer 10, as illustrated in FIG. 7, in an area mostly defined by the aperture 24 in the photomask 22. The etch forms an aperture 48 extending down to the underlying substrate 12, and the etched volume corresponds to the stem of the wineglass shape. The third etch may be the most demanding one since it may require the etching of a hole with a high aspect ratio, and further it is desirous that the etch be selective to the underlying material. However, the large lateral extent of the bowl area 36 lessens the severity of the geometry of deep hole etching. Such etches are well known. For example, the third etch 46 can have the same conditions as the first etch 28, as listed in TABLE 1. The same conditions apply to both etching a contact hole over silicon or etching a via hole over a metal. Using the same reactor for the first and third etch steps and an RPS reactor for the second etch step improves throughput since the two reactors are easily included on the same platform.
  • A series of experiments were performed varying the times of the anisotropic and isotropic etch times for forming the bowl. The resultant bowl shape was then measured using scanning electron micrographs. The total etch depth is the total from the first two etching steps, that is, the depth of the bowl. The shape is characterized by a mean L/V ratio for many etched holes, where L is the maximum lateral extent of the undercut on one side of the bowl (averaged over several holes) and V is the vertical extent. The results are presented in TABLE 3 [0024]
    TABLE 3
    MXP+ RPS
    Etch Etch Anisotropic Total
    Time Time Etch Depth Etch Depth
    (s) (s) (nm) (nm) L/V
    14 81 100 514.3 1.68
    26 63 190 507.4 0.81
    34 51 250 491.2 0.50
    20 72 146.7 518.1 1.28
    23 67 168.6 509.3 1.12
    23 67 168.6 521.1 1.20
  • These results show that varying the relative times of the anisotropic and isotropic etches allows substantial control of the wineglass shape. If the etch depth data is calculated as a ratio of the anisotropic etch depth to the total etch depth, it is found that this ratio varies nearly linearly with the observed L/V ratio. [0025]
  • The isotropic etch can be accomplished by a variety of methods, even if the etching is restricted to the preferred plasma dry etching. The MXP[0026] +chamber can be used for a nearly isotropic etching by using a non-polymer-former chemistry, such as the CF4+NF3+O2 chemistry of TABLE 2. A similar chemistry uses SF6 in place of the NF3. In these two chemistries, any carbon left from the etching is oxidized by the O2 to form CO2, which is then vented from the system. Chamber pressures can range from 300 mTorr to 3 Torr. For a more isotropic etch, typically no bias is applied to the pedestal, and no magnetic field is applied to the plasma. It is noted that the MXP+ would produce a tapered etch rather than a curved isotropic etch. Similarly, recently developed inductively coupled high-density plasma (HDP) reactors can be used for the plasma etch by emphasizing the source plasma. An advantage of using the MXP+ or HDP reactors, is that the same reactor can be used for two or all three of the etching steps.
  • However, we have found that an effective isotropic etcher is a remote plasma-source (RPS) etcher, which is used prior to the anisotropic etch in the MXP[0027] + reactor. An RPS etch chamber is illustrated in the schematic cross section of FIG. 8. A vacuum chamber 60 contains a pedestal 62 having an electrostatic chuck on its upper surface for selectively clamping a wafer 64. An unillustrated vacuum pumping system pumps the chamber 60 through a throttle valve 70. Processing gas is admitted to an upper cavity 72 in the chamber 60 through a microwave applicator 74. The processing gas in the upper cavity is uniformly distributed to the processing area over the wafer 64 through a gas distribution plate 78 having a plurality of narrow holes 80 through it for passing the processing gas.
  • A [0028] magnetron 84 supplies microwave power in the gigahertz range through a microwave waveguide 86 to the applicator 74. An autotuner 88 on the waveguide 86 adjusts the microwave impedance for varying plasma conditions. The microwave power applied to the applicator 74 excites into a plasma the processing gas flowing through the applicator 74, and the excited gas flows through the gas distribution plate 78 to the processing area. Because of the distances involved, the plasma is mostly in the form of neutral radicals. In this chamber, there is no additional plasma generating equipment in the vacuum chamber 60, and no bias is applied to the pedestal 62. As a result, the excited gas plasma etching the wafer 64 does so without any directional acceleration across a plasma sheath, and the resulting etch is both soft and isotropic.
  • An RPS etcher is relatively inexpensive and is easy to operate and maintain so that a three-step, two-chamber etch is not that much more expensive than a single-chamber etch. A two-step, single-chamber etch for the latter two steps according to the invention can be performed in an MXP[0029] + chamber by first setting the chamber process conditions to conditions favoring an isotropic etch by increasing the pressure, reducing the bias, and lowering the power. Then the chamber process conditions are set to conditions favoring anisotropic etching, such as using a chemistry similar to that of TABLE 1. It is also possible to add a remote plasma source to a capacitively or inductively coupled plasma reactor, e.g., the MXP+. The combination chamber can then be operated in either the isotropic RPS mode or the anisotropic local plasma mode or a combination of the two.
  • It is also possible to perform the etching of a tailored bowl shape by a single etch step that is intermediate an isotropic and a strongly anisotropic etch. For example, the pedestal bias and argon flow can be reduced from those values listed in TABLE 1, but still have finite values. The flow polymer former CHF[0030] 3 can be increased. This approach is particularly applicable to L/V values of less than unity. For many etch and via etches, the etch conditions are optimized to produce side wall angles of greater than 85°, and preferably close to 90°, the ultimate in anisotropy. It is known that other conditions produce an etch of less anisotropy, for example, producing side walls angles of significantly less than 90°, say 60°. While such an etch is not isotropic, it combines the characteristic of a strongly anisotropic etch and an isotropic etch. A strongly anisotropic etching profile may be defined as one producing a side wall angle of greater than 80°.
  • Furthermore, more than two processing conditions producing differing anisotropy may be used in forming the bowl, for example, three or more steps producing decreasing anisotropy in etching the oxide, so as to tailor the curve of the bowl as well as the overall L/V ratio. [0031]
  • Although the invention has been applied to an oxide layer, the invention can also be applied to other dielectric layers, such as carbon-based dielectrics which may be used for their low dielectric constants. [0032]
  • It is thus seen that the invention provides additional control over the shape of a hole etched into an oxide layer, particularly in a wineglass etch for a contact or via. Nonetheless, the additional control is achieved with either the use of an additional low-cost chamber or by using the same plasma etch reactor under a number of different conditions. [0033]

Claims (15)

What is claimed is:
1. A method of etching a hole in dielectric layer having a mask formed thereover with a hole therethrough, comprising the steps of:
a first step of plasma etching said dielectric layer through said mask aperture in an anisotropic etching process;
a second step, after said first step, of plasma etching said dielectric layer through said mask aperture in an isotropic etching process producing less anisotropy than said first step; and
a third step, after said second step, of plasma etching said dielectric layer through said mask aperture in an anisotropic etching process.
2. The method of
claim 1
, wherein said dielectric layer overlies a substrate to be electrically contacted through said hole, and said third step etches through said dielectric layer.
3. The method of
claim 1
, wherein said first and third step includes RF biasing a pedestal holding said substrate more strongly than in said second step.
4. The method of
claim 3
, wherein said second step includes exciting a processing gas into a plasma with a remote plasma source.
5. The method of
claim 4
, wherein said dielectric layer comprises an oxide layer.
6. The method of
claim 5
, wherein a first processing gas used in said first step comprises a fluorocarbon gas and argon and a second processing gas used in said second step comprises a fluorocarbon gas and oxygen.
7. The method of
claim 6
, wherein said second processing gas additionally comprises NF3.
8. The method of
claim 1
, wherein said dielectric layer comprises an oxide layer.
9. The method of
claim 8
, wherein said first step is performed with a fluorocarbon chemistry and wherein said second step includes a flow of oxygen.
10. The method of
claim 1
, wherein said first and second step are performed in a same plasma reaction chamber.
11. A method of etching a hole through a dielectric layer in a substrate, comprising the steps of:
a first etching step including RF biasing a pedestal supporting said substrate within a plasma reaction chamber, flowing a first etching gas into said chamber, and exciting a plasma within said chamber, wherein processing conditions in said first step produce a etching profile of said hole intermediate an isotropic etch and a strongly anisotropic etch to produce a first hole portion having a top wider than a bottom thereof; and
a second etching step performed subsequent to said first step including a strongly anisotropic etch of said hole through said oxide layer.
12. The method of
claim 11
, wherein said etching profile of the first step has sidewall angles of less than 80°.
13. The method of
claim 12
, wherein said strongly anisotropic etch produces sidewall angles of greater than 85°.
14. The method of
claim 11
, wherein said dielectric layer comprises an oxide layer.
15. The method of
claim 14
, wherein a processing gas used in said first step comprises a fluorocarbon gas and argon.
US09/121,190 1998-07-22 1998-07-22 Oxide plasma etching process with a controlled wineglass shape Expired - Lifetime US6355557B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/121,190 US6355557B2 (en) 1998-07-22 1998-07-22 Oxide plasma etching process with a controlled wineglass shape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/121,190 US6355557B2 (en) 1998-07-22 1998-07-22 Oxide plasma etching process with a controlled wineglass shape

Publications (2)

Publication Number Publication Date
US20010003678A1 true US20010003678A1 (en) 2001-06-14
US6355557B2 US6355557B2 (en) 2002-03-12

Family

ID=22395139

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/121,190 Expired - Lifetime US6355557B2 (en) 1998-07-22 1998-07-22 Oxide plasma etching process with a controlled wineglass shape

Country Status (1)

Country Link
US (1) US6355557B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050178333A1 (en) * 2004-02-18 2005-08-18 Asm Japan K.K. System and method of CVD chamber cleaning
US20060157351A1 (en) * 2005-01-14 2006-07-20 Nitto Denko Corporation Method of manufacturing printed circuit board
US20080067570A1 (en) * 2005-12-13 2008-03-20 Sony Corporation Display apparatus
US20090221146A1 (en) * 2008-02-29 2009-09-03 Elpida Memory, Inc. Nonvolatile memory device and manufacturing method for the same
US20090239033A1 (en) * 2002-06-05 2009-09-24 Panaconic Corporation Diaphragm and device for measuring cellular potential using the same, manufacturing method of the diaphragm
CN102117775A (en) * 2009-12-30 2011-07-06 北大方正集团有限公司 Filling method and device for contact hole of complementary metal oxide semiconductor
CN104377161A (en) * 2013-08-14 2015-02-25 北大方正集团有限公司 Method for manufacturing through hole structure
FR3027453A1 (en) * 2014-10-20 2016-04-22 Commissariat Energie Atomique RESISTIVE DEVICE FOR MEMORY OR LOGIC CIRCUIT AND METHOD FOR MANUFACTURING SUCH A DEVICE
US20160222557A1 (en) * 2013-10-02 2016-08-04 Carl Freudenberg Kg Fabric sheet with hig thermal stability
CN107664884A (en) * 2016-07-29 2018-02-06 株式会社日本显示器 Electronic equipment and its manufacture method

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335292B1 (en) * 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
KR100457844B1 (en) * 2002-08-27 2004-11-18 삼성전자주식회사 Method Of Etching Semiconductor Device
US7049034B2 (en) * 2003-09-09 2006-05-23 Photronics, Inc. Photomask having an internal substantially transparent etch stop layer
US6933084B2 (en) * 2003-03-18 2005-08-23 Photronics, Inc. Alternating aperture phase shift photomask having light absorption layer
JP2004342938A (en) * 2003-05-16 2004-12-02 Renesas Technology Corp Semiconductor device
US20060051681A1 (en) * 2004-09-08 2006-03-09 Phototronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Conecticut Method of repairing a photomask having an internal etch stop layer
US7456097B1 (en) * 2004-11-30 2008-11-25 National Semiconductor Corporation System and method for faceting via top corners to improve metal fill
KR100831572B1 (en) * 2005-12-29 2008-05-21 동부일렉트로닉스 주식회사 Method of forming metal line for semiconductor device
US7709367B2 (en) * 2006-06-30 2010-05-04 Hynix Semiconductor Inc. Method for fabricating storage node contact in semiconductor device
US7446036B1 (en) * 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
CN102642806A (en) * 2012-04-28 2012-08-22 上海先进半导体制造股份有限公司 Method for manufacturing semiconductor multi-step structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
US4865685A (en) * 1987-11-03 1989-09-12 North Carolina State University Dry etching of silicon carbide
US6068784A (en) * 1989-10-03 2000-05-30 Applied Materials, Inc. Process used in an RF coupled plasma reactor
US5021920A (en) * 1990-03-30 1991-06-04 Texas Instruments Incorporated Multilevel integrated circuit capacitor and method of fabrication
US5180689A (en) * 1991-09-10 1993-01-19 Taiwan Semiconductor Manufacturing Company Tapered opening sidewall with multi-step etching process
US5399237A (en) * 1994-01-27 1995-03-21 Applied Materials, Inc. Etching titanium nitride using carbon-fluoride and carbon-oxide gas
US6015761A (en) * 1996-06-26 2000-01-18 Applied Materials, Inc. Microwave-activated etching of dielectric layers
US5746884A (en) * 1996-08-13 1998-05-05 Advanced Micro Devices, Inc. Fluted via formation for superior metal step coverage
US5779807A (en) * 1996-10-29 1998-07-14 Applied Materials, Inc. Method and apparatus for removing particulates from semiconductor substrates in plasma processing chambers
US5882424A (en) * 1997-01-21 1999-03-16 Applied Materials, Inc. Plasma cleaning of a CVD or etch reactor using a low or mixed frequency excitation field
US5965035A (en) * 1997-10-23 1999-10-12 Applied Materials, Inc. Self aligned contact etch using difluoromethane and trifluoromethane

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8202439B2 (en) * 2002-06-05 2012-06-19 Panasonic Corporation Diaphragm and device for measuring cellular potential using the same, manufacturing method of the diaphragm
US20090239033A1 (en) * 2002-06-05 2009-09-24 Panaconic Corporation Diaphragm and device for measuring cellular potential using the same, manufacturing method of the diaphragm
US20050178333A1 (en) * 2004-02-18 2005-08-18 Asm Japan K.K. System and method of CVD chamber cleaning
US20060157351A1 (en) * 2005-01-14 2006-07-20 Nitto Denko Corporation Method of manufacturing printed circuit board
US7476328B2 (en) * 2005-01-14 2009-01-13 Nitto Denko Corporation Method of manufacturing printed circuit board
US20080067570A1 (en) * 2005-12-13 2008-03-20 Sony Corporation Display apparatus
US8111340B2 (en) * 2005-12-13 2012-02-07 Sony Corporation Display apparatus
US20090221146A1 (en) * 2008-02-29 2009-09-03 Elpida Memory, Inc. Nonvolatile memory device and manufacturing method for the same
CN102117775A (en) * 2009-12-30 2011-07-06 北大方正集团有限公司 Filling method and device for contact hole of complementary metal oxide semiconductor
CN104377161A (en) * 2013-08-14 2015-02-25 北大方正集团有限公司 Method for manufacturing through hole structure
US20160222557A1 (en) * 2013-10-02 2016-08-04 Carl Freudenberg Kg Fabric sheet with hig thermal stability
FR3027453A1 (en) * 2014-10-20 2016-04-22 Commissariat Energie Atomique RESISTIVE DEVICE FOR MEMORY OR LOGIC CIRCUIT AND METHOD FOR MANUFACTURING SUCH A DEVICE
WO2016062613A1 (en) * 2014-10-20 2016-04-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing a resistive device for a memory or logic circuit
US10056266B2 (en) 2014-10-20 2018-08-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing a resistive device for a memory or logic circuit
CN107664884A (en) * 2016-07-29 2018-02-06 株式会社日本显示器 Electronic equipment and its manufacture method

Also Published As

Publication number Publication date
US6355557B2 (en) 2002-03-12

Similar Documents

Publication Publication Date Title
US6355557B2 (en) Oxide plasma etching process with a controlled wineglass shape
US6583065B1 (en) Sidewall polymer forming gas additives for etching processes
US6039851A (en) Reactive sputter faceting of silicon dioxide to enhance gap fill of spaces between metal lines
US6867141B2 (en) Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma
US6306772B1 (en) Deep trench bottle-shaped etching using Cl2 gas
US6620737B2 (en) Plasma etching method
JP3213803B2 (en) Method for forming slope contact hole in semiconductor using high-density plasma etching equipment
CN100521111C (en) Plasma etching method
KR20010042106A (en) Techniques for forming trenches in a silicon layer of a substrate in a high density plasma processing system
KR20030087637A (en) Method for etching organic insulating film and dual damasene process
US20040077178A1 (en) Method for laterally etching a semiconductor structure
JP3331979B2 (en) Semiconductor etching method
US6117764A (en) Use of a plasma source to form a layer during the formation of a semiconductor device
US20070212888A1 (en) Silicon Substrate Etching Method
US6653237B2 (en) High resist-selectivity etch for silicon trench etch applications
JPH08288256A (en) Trench etching method
JPH08195380A (en) Method of forming contact hole
US6468603B1 (en) Plasma film forming method utilizing varying bias electric power
US7294578B1 (en) Use of a plasma source to form a layer during the formation of a semiconductor device
JP5171091B2 (en) Plasma processing method
JP4260352B2 (en) Manufacturing method of semiconductor device
KR20010112878A (en) Method for fabricating a semiconductor device
JPH09162162A (en) Production of semiconductor device
JP3854019B2 (en) Manufacturing method of semiconductor device
JPH0750292A (en) Taper etching method

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STINNETT, JAMES A.;BROOKS, CYNTHIA B.;MERRY, WALTER R.;AND OTHERS;REEL/FRAME:009341/0347;SIGNING DATES FROM 19980714 TO 19980722

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12