US12512834B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
US12512834B2
US12512834B2 US17/736,514 US202217736514A US12512834B2 US 12512834 B2 US12512834 B2 US 12512834B2 US 202217736514 A US202217736514 A US 202217736514A US 12512834 B2 US12512834 B2 US 12512834B2
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power supply
voltage
driving circuit
side driving
circuit
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US20230137944A1 (en
Inventor
Yo Habu
Akihisa Yamamoto
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/785—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/327—Means for protecting converters other than automatic disconnection against abnormal temperatures
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Definitions

  • the present disclosure relates to a semiconductor device that generates a power supply voltage for a driving circuit that drives a switching device.
  • a driving circuit that drives a switching device such as an IGBT is used.
  • a power supply voltage for an N-side driving circuit is generated by a transformer and a power supply voltage for a P-side driving circuit is generated by a bootstrap circuit (see, for example, Japanese Patent Laid-Open No. 2013-191989 (FIG. 1)).
  • the present disclosure has been made in order to solve the problems described above and an object of the present disclosure is to obtain a semiconductor device that can reduce the mounting area in size and reduce the cost.
  • a semiconductor device includes: a P-side driving circuit and an N-side driving circuit respectively driving a P-side switching device and an N-side switching device which are connected to configure a half bridge; and a N-side power supply generation circuit generating a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device.
  • the power supply generation circuit generates a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device. Accordingly, it is possible to generate the power supply voltage for the N-side driving circuit without using a transformer having a large area. Therefore, it is possible to reduce a mounting area and reduce cost.
  • FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment.
  • FIG. 2 is a diagram illustrating a configuration example of a power supply generation circuit.
  • FIG. 3 is a diagram illustrating a semiconductor device according to a second embodiment.
  • FIG. 4 is a diagram illustrating a semiconductor device according to a third embodiment.
  • FIG. 5 is a time chart of voltages of the units of the semiconductor device according to the third embodiment.
  • FIG. 6 is a diagram illustrating a semiconductor device according to a fourth embodiment.
  • FIG. 7 is a diagram illustrating a modification 1 of the semiconductor device according to the fourth embodiment.
  • FIG. 8 is a diagram illustrating a modification 2 of the semiconductor device according to the fourth embodiment.
  • FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment.
  • the semiconductor device is a three-phase inverter.
  • P-side switching devices S P1 , S P2 , and S P3 and N-side switching devices S N1 , S N2 , and S N3 are connected to configure a half bridge. That is, a collector of the P-side switching device S P1 is connected to a P terminal, an emitter of the P-side switching device S P1 and a collector of the N-side switching device S N1 are connected to each other, and an emitter of the N-side switching device S N1 is connected to the GND.
  • the other switching devices are connected in the same manner.
  • the P-side switching devices S P1 , S P2 , and Spa and the N-side switching devices S N1 , S N2 , and S N3 are IGBTs (Insulated Gate Bipolar Transistors) but may be other power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Note that “P side” means a high side of the half bridge and “N side” means a low side of the half bridge.
  • P-side driving circuits DC P1 , DC P2 , and DC P3 respectively drive the P-side switching devices S P1 , S P2 , and S P3 .
  • N-side driving circuits DC N1 , DC N2 , and DC N3 respectively drive the N-side switching devices S N1 , S N2 , and S N3 .
  • a memory control unit 1 sends control signals respectively to the P-side driving circuits DC P1 , DC P2 , and DC P3 and the N-side driving circuits DC N1 , DC N2 , and DC N3 via photocouplers 2 .
  • a P voltage applied to a P terminal is power supply voltages for the P-side switching devices S P1 , S P2 , and S P3 .
  • a power supply IC 3 Since a voltage higher than the P voltage is necessary for gate driving for the P-side switching devices S P1 , S P2 , and S P3 , power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 cannot be generated from the P voltage. Therefore, a power supply IC 3 generates, with a transformer 4 , the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 .
  • the power supply voltage for the P-side driving circuit DC P1 is a voltage VB 1 -VS 1 based on an emitter voltage VS 1 of the P-side switching device S P1 .
  • the power supply voltage for the P-side driving circuit DC P2 is a voltage VB 2 -VS 2 .
  • the power supply voltage for the P-side driving circuit DC P3 is a voltage VB 3 -VS 3 .
  • N-side power supply generation circuits PG N1 , PG N2 , and PG N3 respectively generate power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 from the P voltage without using a transformer.
  • the N-side driving circuit DC N1 and the N-side power supply generation circuit PG N1 are integrated in an N-side gate driver GD N1 of the same chip or the same package.
  • the N-side driving circuit DC N2 and the N-side power supply generation circuit PG N2 are integrated in an N-side gate driver GD N2 .
  • the N-side driving circuit DC N3 and the N-side power supply generation circuit PG N3 are integrated in an N-side gate driver GD N3 .
  • the N-side gate drivers GD N1 , GD N2 , and GD N3 are integrated circuits. Power supply generation circuits are not provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 .
  • the P-side driving circuits DC P1 , DC P2 , and DC P3 are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 .
  • the P-side switching devices S P1 , S P2 , and S P3 , the N-side switching devices S N1 , S N2 , and S N3 , the P-side gate drivers GD P1 , GD P2 , and GD P3 , the N-side gate drivers GD N1 , GD N2 , and GD N3 , an MCU 1 , the power supply IC 3 , the transformer 4 , and the like are mounted on a substrate.
  • FIG. 2 is a diagram illustrating a configuration example of a power supply generation circuit.
  • the power supply generation circuit corresponds to the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 .
  • Resistors R 1 and R 2 are connected in series between a P terminal and a grounding point.
  • a gate of a high withstand voltage NMOS 5 is connected to a connection point of the resistors R 1 and R 2 , a drain of the high withstand voltage NMOS 5 is connected to the P terminal, and a source of the high withstand voltage NMOS 5 is connected to a constant current circuit 6 .
  • the constant current circuit 6 outputs an electric current to a Vcc terminal.
  • the Vcc terminal is an output terminal of the power supply generation circuit.
  • a Vcc monitor circuit 7 monitors a voltage value of the Vcc terminal and controls ON and OFF of the constant current circuit 6 .
  • the high withstand voltage NMOS 5 may be externally attached without being incorporated in the gate driver.
  • the N-side power supply generation circuits PG N1 , PG N2 and PG N3 generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 from the P voltage using the constant current circuit 6 without using a transformer.
  • the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 from the P voltage. Accordingly, it is possible to generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 without using a transformer having a large area. As a result, it is possible to reduce the number of times of power supply generation by the transformer 4 from six to three. Therefore, it is possible to reduce a mounting area and reduce cost.
  • the N-side driving circuits DC N1 , DC N2 , and DC N3 and the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 can be respectively integrated into the same chips or the same packages. This is advantageous for a reduction in size.
  • the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 in the P-side gate drivers GD P1 , GD P2 , and GD P3 can also generate a power supply voltage for the photocouplers 2 connected to the P-side gate drivers GD P1 , GD P2 , and GD P3 .
  • FIG. 3 is a diagram illustrating a semiconductor device according to a second embodiment.
  • the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 are generated by the transformer 4 .
  • P-side power supply generation circuits PG P1 , PG P2 , and PG P3 are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 .
  • the P-side power supply generation circuits PG P1 , PG P2 , and PG P3 have the configuration illustrated in FIG. 2 .
  • the P-side power supply generation circuits PG P1 , PG P2 , and PG P3 respectively generate the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 using the constant current circuit 6 without using a transformer.
  • the P-side driving circuit DC P1 and the P-side power supply generation circuit PG P1 are integrated in the P-side gate driver GD P1 of the same chip or the same package.
  • the P-side driving circuit DC P2 and the P-side power supply generation circuit PG P2 are integrated in the P-side gate driver GD P2 .
  • the P-side driving circuit DC P3 and the P-side power supply generation circuit PG P3 are integrated in the P-side gate driver GD P3 .
  • the P-side driving circuits DC P1 , DC P2 , and DC P3 need a power supply voltage higher than the P voltage. Therefore, the power supply IC 3 generates, with the transformer 4 , a P′ voltage higher than the P voltage.
  • the P-side power supply generation circuits PG P1 , PG P2 , and PG P3 respectively generate power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 from the P′ voltage.
  • the number of times of power supply generation by the transformer 4 is three in the first embodiment, in this embodiment, the number of times of power supply generation by the transformer 4 can be reduced to one. Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment.
  • FIG. 4 is a diagram illustrating a semiconductor device according to a third embodiment.
  • the P-side power supply generation circuits PG P1 , PG P2 , and PG P3 are respectively provided in the P-side gate drivers GD P1 , GD P2 , and GD P3 .
  • the P-side power supply generation circuits PG P1 , PG P2 , and PG P3 generate power supply voltages for the P-side driving circuit DC P1 , DC P2 , and DC P3 from the P voltage.
  • FIG. 5 is a time chart of voltages of the units of the semiconductor device according to the third embodiment.
  • P represents a voltage at the P terminal
  • Vcc 1 represents a power supply voltage for the N-side driving circuit DC N1
  • LO 1 represents an output voltage of the N-side driving circuit DC N1
  • VS 1 represents an emitter voltage of the P-side switching device S P1
  • VB 1 -VS 1 represents a power supply voltage for the P-side driving circuit DC P1 .
  • the P-side power supply generation circuit PG P1 generates the power supply voltage VB 1 -VS 1 for the P-side driving circuit DC P1 .
  • the P-side power supply generation circuit PG P1 can generate the power supply voltage VB 1 -VS 1 for the P-side driving circuit DC P1 from the P voltage.
  • Power supply voltages VB 2 -VS 2 and VB 3 -VS 3 for the P-side driving circuits DC P2 and DC P3 are generated by the same method.
  • FIG. 6 is a diagram illustrating a semiconductor device according to a fourth embodiment.
  • the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 are respectively provided in the N-side gate drivers GD N1 , GD N2 , and GD N3 and respectively generate power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 from the P voltage.
  • bootstrap circuits BS 1 , BS 2 , and BS 3 respectively boost output voltages of the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 to generate power supply voltages for the P-side driving circuit DC P1 , DC P2 , and DC P3 .
  • the bootstrap circuit BS 1 includes a bootstrap diode D 1 and a bootstrap capacitor C 1 .
  • An anode of the bootstrap diode D 1 is connected to an output terminal of the N-side power supply generation circuit PG N1 and a cathode of the bootstrap diode D 1 is connected to a power supply terminal of the P-side driving circuit DC P1 .
  • One end of the bootstrap capacitor C 1 is connected to an emitter of the P-side switching device S P1 and the other end of the bootstrap capacitor C 1 is connected to a power supply terminal of the P-side driving circuit DC P1 .
  • the bootstrap circuit BS 2 includes a bootstrap diode D 2 and a bootstrap capacitor C 2 .
  • the bootstrap circuit BS 3 includes a bootstrap diode D 3 and a bootstrap capacitor C 3 .
  • the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 generate the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 from the P voltage. Therefore, a transformer for generating the power supply voltages for the N-side driving circuits DC N1 , DC N2 , and DC N3 can be omitted.
  • the bootstrap circuits BS 1 , BS 2 , and BS 3 respectively boost the output voltages of the N-side power supply generation circuits PG N1 , PG N2 , and PG N3 to generate the power supply voltages for the P-side driving circuits DC P1 , DC P2 , and DC P3 .
  • the transformer 4 in the first embodiment can be omitted.
  • a mounting area of the bootstrap circuits BS 1 , BS 2 , and BS 3 is smaller than a mounting area of the transformer 4 . Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment.
  • FIG. 7 is a diagram illustrating a modification 1 of the semiconductor device according to the fourth embodiment.
  • the P-side driving circuit DC P1 and the N-side driving circuit DC N1 are formed on one chip to configure a gate driver GD 1 .
  • the P-side driving circuit DC P1 and the N-side driving circuit DC N1 are formed on different chips, low-voltage internal power supplies that generate IC internal voltages from a power supply, power supply voltage drop protection circuits that detect a voltage drop of the power supply and interrupt a gate driving operation, and the like are necessary in the driving circuits.
  • the P-side driving circuit DC P1 and the N-side driving circuit DC N1 are HVICs (High Voltage ICs).
  • FIG. 8 is a diagram illustrating a modification 2 of the semiconductor device according to the fourth embodiment.
  • the bootstrap diodes D 1 , D 2 , and D 3 are respectively incorporated in the gate drivers GD 1 , GD 2 , and GD 3 . Consequently, it is possible to further reduce a substrate area.
  • the P-side switching devices S P1 , S P2 , and S P3 and N-side switching devices S N1 , S N2 , and S N3 are not limited to devices formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon.
  • the wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond.
  • a semiconductor chip formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized.
  • the use of such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip is incorporated. Further, since the semiconductor chip has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor device. Further, since the semiconductor chip has a low power loss and a high efficiency, a highly efficient semiconductor device can be achieved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)
  • Logic Circuits (AREA)
  • Inverter Devices (AREA)

Abstract

A semiconductor device includes: a P-side driving circuit and an N-side driving circuit respectively driving a P-side switching device and an N-side switching device which are connected to configure a half bridge; and a N-side power supply generation circuit generating a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device.

Description

BACKGROUND OF THE INVENTION Field
The present disclosure relates to a semiconductor device that generates a power supply voltage for a driving circuit that drives a switching device.
Background
In an inverter, a driving circuit that drives a switching device such as an IGBT is used. In a semiconductor device of relate art, a power supply voltage for an N-side driving circuit is generated by a transformer and a power supply voltage for a P-side driving circuit is generated by a bootstrap circuit (see, for example, Japanese Patent Laid-Open No. 2013-191989 (FIG. 1)).
SUMMARY
In the semiconductor device of the related art, since the transformer and the bootstrap diode are necessary, a mounting area on a substrate increases in size and cost increases.
The present disclosure has been made in order to solve the problems described above and an object of the present disclosure is to obtain a semiconductor device that can reduce the mounting area in size and reduce the cost.
A semiconductor device according to the present disclosure includes: a P-side driving circuit and an N-side driving circuit respectively driving a P-side switching device and an N-side switching device which are connected to configure a half bridge; and a N-side power supply generation circuit generating a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device.
In the present disclosure, the power supply generation circuit generates a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device. Accordingly, it is possible to generate the power supply voltage for the N-side driving circuit without using a transformer having a large area. Therefore, it is possible to reduce a mounting area and reduce cost.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment.
FIG. 2 is a diagram illustrating a configuration example of a power supply generation circuit.
FIG. 3 is a diagram illustrating a semiconductor device according to a second embodiment.
FIG. 4 is a diagram illustrating a semiconductor device according to a third embodiment.
FIG. 5 is a time chart of voltages of the units of the semiconductor device according to the third embodiment.
FIG. 6 is a diagram illustrating a semiconductor device according to a fourth embodiment.
FIG. 7 is a diagram illustrating a modification 1 of the semiconductor device according to the fourth embodiment.
FIG. 8 is a diagram illustrating a modification 2 of the semiconductor device according to the fourth embodiment.
 DESCRIPTION OF EMBODIMENTS
A semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
First Embodiment
FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment. The semiconductor device is a three-phase inverter. P-side switching devices SP1, SP2, and SP3 and N-side switching devices SN1, SN2, and SN3 are connected to configure a half bridge. That is, a collector of the P-side switching device SP1 is connected to a P terminal, an emitter of the P-side switching device SP1 and a collector of the N-side switching device SN1 are connected to each other, and an emitter of the N-side switching device SN1 is connected to the GND. The other switching devices are connected in the same manner. The P-side switching devices SP1, SP2, and Spa and the N-side switching devices SN1, SN2, and SN3 are IGBTs (Insulated Gate Bipolar Transistors) but may be other power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Note that “P side” means a high side of the half bridge and “N side” means a low side of the half bridge.
P-side driving circuits DCP1, DCP2, and DCP3 respectively drive the P-side switching devices SP1, SP2, and SP3. N-side driving circuits DCN1, DCN2, and DCN3 respectively drive the N-side switching devices SN1, SN2, and SN3. A memory control unit 1 sends control signals respectively to the P-side driving circuits DCP1, DCP2, and DCP3 and the N-side driving circuits DCN1, DCN2, and DCN3 via photocouplers 2. A P voltage applied to a P terminal is power supply voltages for the P-side switching devices SP1, SP2, and SP3.
Since a voltage higher than the P voltage is necessary for gate driving for the P-side switching devices SP1, SP2, and SP3, power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3 cannot be generated from the P voltage. Therefore, a power supply IC 3 generates, with a transformer 4, the power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3. The power supply voltage for the P-side driving circuit DCP1 is a voltage VB1-VS1 based on an emitter voltage VS1 of the P-side switching device SP1. Similarly, the power supply voltage for the P-side driving circuit DCP2 is a voltage VB2-VS2. The power supply voltage for the P-side driving circuit DCP3 is a voltage VB3-VS3.
N-side power supply generation circuits PGN1, PGN2, and PGN3 respectively generate power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 from the P voltage without using a transformer. The N-side driving circuit DCN1 and the N-side power supply generation circuit PGN1 are integrated in an N-side gate driver GDN1 of the same chip or the same package. Similarly, the N-side driving circuit DCN2 and the N-side power supply generation circuit PGN2 are integrated in an N-side gate driver GDN2. The N-side driving circuit DCN3 and the N-side power supply generation circuit PGN3 are integrated in an N-side gate driver GDN3. The N-side gate drivers GDN1, GDN2, and GDN3 are integrated circuits. Power supply generation circuits are not provided in the P-side gate drivers GDP1, GDP2, and GDP3. The P-side driving circuits DCP1, DCP2, and DCP3 are respectively provided in the P-side gate drivers GDP1, GDP2, and GDP3.
The P-side switching devices SP1, SP2, and SP3, the N-side switching devices SN1, SN2, and SN3, the P-side gate drivers GDP1, GDP2, and GDP3, the N-side gate drivers GDN1, GDN2, and GDN3, an MCU 1, the power supply IC 3, the transformer 4, and the like are mounted on a substrate.
FIG. 2 is a diagram illustrating a configuration example of a power supply generation circuit. The power supply generation circuit corresponds to the N-side power supply generation circuits PGN1, PGN2, and PGN3. Resistors R1 and R2 are connected in series between a P terminal and a grounding point. A gate of a high withstand voltage NMOS 5 is connected to a connection point of the resistors R1 and R2, a drain of the high withstand voltage NMOS 5 is connected to the P terminal, and a source of the high withstand voltage NMOS 5 is connected to a constant current circuit 6. The constant current circuit 6 outputs an electric current to a Vcc terminal. The Vcc terminal is an output terminal of the power supply generation circuit. A Vcc monitor circuit 7 monitors a voltage value of the Vcc terminal and controls ON and OFF of the constant current circuit 6. In order to reduce heat generation of a gate driver, the high withstand voltage NMOS 5 may be externally attached without being incorporated in the gate driver.
When the P voltage is applied, a volage is applied to the gate of the high withstand voltage NMOS 5 and the high withstand voltage NMOS 5 is turned on. Consequently, an electric current flows from the P terminal to the drain and the source of the high withstand voltage NMOS 5. The electric current flows into the Vcc terminal via the constant current circuit 6. When a voltage at the Vcc terminal rises to a desired voltage, the Vcc monitor circuit 7 turns off the constant current circuit 6. Consequently, the voltage at the Vcc terminal is prevented from rising to exceed the desired voltage. When the voltage at the Vcc terminal drops, the Vcc monitor circuit 7 turns on the constant current circuit 6. In this way, the N-side power supply generation circuits PGN1, PGN2 and PGN3 generate the power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 from the P voltage using the constant current circuit 6 without using a transformer.
As explained above, in this embodiment, the N-side power supply generation circuits PGN1, PGN2, and PGN3 generate the power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 from the P voltage. Accordingly, it is possible to generate the power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 without using a transformer having a large area. As a result, it is possible to reduce the number of times of power supply generation by the transformer 4 from six to three. Therefore, it is possible to reduce a mounting area and reduce cost. The N-side driving circuits DCN1, DCN2, and DCN3 and the N-side power supply generation circuits PGN1, PGN2, and PGN3 can be respectively integrated into the same chips or the same packages. This is advantageous for a reduction in size. Note that the N-side power supply generation circuits PGN1, PGN2, and PGN3 in the P-side gate drivers GDP1, GDP2, and GDP3 can also generate a power supply voltage for the photocouplers 2 connected to the P-side gate drivers GDP1, GDP2, and GDP3.
Second Embodiment
FIG. 3 is a diagram illustrating a semiconductor device according to a second embodiment. In the first embodiment, the power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3 are generated by the transformer 4. In contrast, in this embodiment, P-side power supply generation circuits PGP1, PGP2, and PGP3 are respectively provided in the P-side gate drivers GDP1, GDP2, and GDP3. The P-side power supply generation circuits PGP1, PGP2, and PGP3 have the configuration illustrated in FIG. 2 . The P-side power supply generation circuits PGP1, PGP2, and PGP3 respectively generate the power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3 using the constant current circuit 6 without using a transformer. The P-side driving circuit DCP1 and the P-side power supply generation circuit PGP1 are integrated in the P-side gate driver GDP1 of the same chip or the same package. Similarly, the P-side driving circuit DCP2 and the P-side power supply generation circuit PGP2 are integrated in the P-side gate driver GDP2. The P-side driving circuit DCP3 and the P-side power supply generation circuit PGP3 are integrated in the P-side gate driver GDP3.
For gate driving of the P-side switching devices SP1, SP2, and SP3, the P-side driving circuits DCP1, DCP2, and DCP3 need a power supply voltage higher than the P voltage. Therefore, the power supply IC 3 generates, with the transformer 4, a P′ voltage higher than the P voltage. The P-side power supply generation circuits PGP1, PGP2, and PGP3 respectively generate power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3 from the P′ voltage. Consequently, whereas the number of times of power supply generation by the transformer 4 is three in the first embodiment, in this embodiment, the number of times of power supply generation by the transformer 4 can be reduced to one. Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment.
Third Embodiment
FIG. 4 is a diagram illustrating a semiconductor device according to a third embodiment. In this embodiment, the P-side power supply generation circuits PGP1, PGP2, and PGP3 are respectively provided in the P-side gate drivers GDP1, GDP2, and GDP3. The P-side power supply generation circuits PGP1, PGP2, and PGP3 generate power supply voltages for the P-side driving circuit DCP1, DCP2, and DCP3 from the P voltage.
FIG. 5 is a time chart of voltages of the units of the semiconductor device according to the third embodiment. P represents a voltage at the P terminal, Vcc1 represents a power supply voltage for the N-side driving circuit DCN1, LO1 represents an output voltage of the N-side driving circuit DCN1, VS1 represents an emitter voltage of the P-side switching device SP1, and VB1-VS1 represents a power supply voltage for the P-side driving circuit DCP1.
For example, in the case of P-GND=600V and VS1-GND=600V, when the VB1-VS1=15V is generated, VB1-GND=615V. Therefore, P<VB1 and the power supply voltage VB1-VS1 for the P-side driving circuit DCP1 cannot be generated from the P voltage.
Therefore, in this embodiment, at an initial start time of the semiconductor device, after the N-side driving circuit DCN1 changes the output voltage LO1 to high to turn on the N-side switching device SN1, the P-side power supply generation circuit PGP1 generates the power supply voltage VB1-VS1 for the P-side driving circuit DCP1.
When the N-side switching device SN1 is turned on, VS1-GND=0V. Therefore, since VB1-GND=15V, P>VB1. Accordingly, the P-side power supply generation circuit PGP1 can generate the power supply voltage VB1-VS1 for the P-side driving circuit DCP1 from the P voltage. Power supply voltages VB2-VS2 and VB3-VS3 for the P-side driving circuits DCP2 and DCP3 are generated by the same method.
Consequently, since power supply generation by a transformer is unnecessary, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment. Note that, if the power supply voltages VB1-VS1, VB2-VS2, and VB3-VS3 for the P-side driving circuits DCP1, DCP2, and DCP3 can be generated at the initial start time, thereafter, it is possible to cause the P-side driving circuits DCP1, DCP2, and DCP3 to operate without hindering original ON and OFF operations of the switching devices.
Fourth Embodiment
FIG. 6 is a diagram illustrating a semiconductor device according to a fourth embodiment. As in the first embodiment, the N-side power supply generation circuits PGN1, PGN2, and PGN3 are respectively provided in the N-side gate drivers GDN1, GDN2, and GDN3 and respectively generate power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 from the P voltage. Whereas the N-side power supply generation circuits PGN1, PGN2, and PGN3 generate, with the transformer 4, the power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3 in the first embodiment, in this embodiment, bootstrap circuits BS1, BS2, and BS3 respectively boost output voltages of the N-side power supply generation circuits PGN1, PGN2, and PGN3 to generate power supply voltages for the P-side driving circuit DCP1, DCP2, and DCP3. The bootstrap circuit BS1 includes a bootstrap diode D1 and a bootstrap capacitor C1. An anode of the bootstrap diode D1 is connected to an output terminal of the N-side power supply generation circuit PGN1 and a cathode of the bootstrap diode D1 is connected to a power supply terminal of the P-side driving circuit DCP1. One end of the bootstrap capacitor C1 is connected to an emitter of the P-side switching device SP1 and the other end of the bootstrap capacitor C1 is connected to a power supply terminal of the P-side driving circuit DCP1. Similarly, the bootstrap circuit BS2 includes a bootstrap diode D2 and a bootstrap capacitor C2. The bootstrap circuit BS3 includes a bootstrap diode D3 and a bootstrap capacitor C3.
In this embodiment, the N-side power supply generation circuits PGN1, PGN2, and PGN3 generate the power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 from the P voltage. Therefore, a transformer for generating the power supply voltages for the N-side driving circuits DCN1, DCN2, and DCN3 can be omitted. The bootstrap circuits BS1, BS2, and BS3 respectively boost the output voltages of the N-side power supply generation circuits PGN1, PGN2, and PGN3 to generate the power supply voltages for the P-side driving circuits DCP1, DCP2, and DCP3. Therefore, the transformer 4 in the first embodiment can be omitted. A mounting area of the bootstrap circuits BS1, BS2, and BS3 is smaller than a mounting area of the transformer 4. Accordingly, it is possible to further reduce the mounting area and reduce the cost than in the first embodiment.
FIG. 7 is a diagram illustrating a modification 1 of the semiconductor device according to the fourth embodiment. The P-side driving circuit DCP1 and the N-side driving circuit DCN1 are formed on one chip to configure a gate driver GD1. When the P-side driving circuit DCP1 and the N-side driving circuit DCN1 are formed on different chips, low-voltage internal power supplies that generate IC internal voltages from a power supply, power supply voltage drop protection circuits that detect a voltage drop of the power supply and interrupt a gate driving operation, and the like are necessary in the driving circuits. In contrast, by forming the P-side driving circuit DCP1 and the N-side driving circuit DCN1 on the one chip, a low voltage internal power supply, a power supply voltage drop protection circuit, and the like can be shared. Total chip cost can be reduced. Similarly, the P-side driving circuit DCP2 and the N-side driving circuit DCN2 configure a gate driver GD2. The P-side driving circuit DCP3 and the N-side driving circuit DCN3 configure a gate driver GD3. The gate drivers GD1, GD2, and GD3 are HVICs (High Voltage ICs).
FIG. 8 is a diagram illustrating a modification 2 of the semiconductor device according to the fourth embodiment. The bootstrap diodes D1, D2, and D3 are respectively incorporated in the gate drivers GD1, GD2, and GD3. Consequently, it is possible to further reduce a substrate area. The P-side switching devices SP1, SP2, and SP3 and N-side switching devices SN1, SN2, and SN3 are not limited to devices formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A semiconductor chip formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip is incorporated. Further, since the semiconductor chip has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor device. Further, since the semiconductor chip has a low power loss and a high efficiency, a highly efficient semiconductor device can be achieved.
Obviously many modifications and variations of the present disclosure are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
The entire disclosure of Japanese Patent Application No. 2021-180384, filed on Nov. 4, 2021 including specification, claims, drawings and summary, on which the convention priority of the present application is based, is incorporated herein by reference in its entirety.

Claims (2)

The invention claimed is:
1. A semiconductor device comprising:
a P-side driving circuit and an N-side driving circuit respectively driving a P-side switching device and an N-side switching device which are connected to configure a half bridge;
an N-side power supply generation circuit generating a power supply voltage for the N-side driving circuit from a power supply voltage for the P-side switching device;
a transformer generating a voltage higher than the power supply voltage for the P-side switching device; and
a P-side power supply generation circuit generating a power supply voltage for the P-side driving circuit from the voltage generated by the transformer.
2. The semiconductor device according to claim 1, wherein the power supply voltage for the P-side driving circuit is higher than the power supply voltage for the P-side switching device.
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