US12226873B2 - System and method for processing silicon wafers - Google Patents
System and method for processing silicon wafers Download PDFInfo
- Publication number
- US12226873B2 US12226873B2 US17/724,503 US202217724503A US12226873B2 US 12226873 B2 US12226873 B2 US 12226873B2 US 202217724503 A US202217724503 A US 202217724503A US 12226873 B2 US12226873 B2 US 12226873B2
- Authority
- US
- United States
- Prior art keywords
- wafer
- waviness
- parameter
- profile
- waviness parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000012545 processing Methods 0.000 title claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 10
- 239000010703 silicon Substances 0.000 title claims abstract description 10
- 235000012431 wafers Nutrition 0.000 title claims description 167
- 238000005520 cutting process Methods 0.000 claims abstract description 26
- 238000005498 polishing Methods 0.000 claims description 6
- 238000012423 maintenance Methods 0.000 claims description 5
- 238000012935 Averaging Methods 0.000 claims description 3
- 238000005259 measurement Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 238000003908 quality control method Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 238000004422 calculation algorithm Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000007717 exclusion Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 235000002595 Solanum tuberosum Nutrition 0.000 description 1
- 244000061456 Solanum tuberosum Species 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012067 mathematical method Methods 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005329 nanolithography Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000012800 visualization Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/30—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring roughness or irregularity of surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
- B24B49/02—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
- B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
- B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
- B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
- B28D5/0064—Devices for the automatic drive or the program control of the machines
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/04—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools
- B28D5/045—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools by cutting with wires or closed-loop blades
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B2210/00—Aspects not specifically covered by any group under G01B, e.g. of wheel alignment, caliper-like sensors
- G01B2210/56—Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
Definitions
- the present invention relates to systems and methods for processing semiconductor wafers.
- Semiconductor wafers are commonly used in a variety of applications, including in the fabrication of circuits and solar cells. Due to the ubiquitous use of integrated circuits in electrical and electromechanical devices, production of high quality semiconductor wafers is increasingly important for optimum product quality and performance. This is especially true when constraints in the semiconductor industry, such as supply chain constraints, material shortages, high demand, and other local or global economic forces, require semiconductors to be manufactured as efficiently with minimal margin for error.
- waves with a longer wavelength can be flattened on a chuck when their amplitude is relatively high, whereas waves with short wavelength can only be flattened when waves amplitude is very small.
- waves with spatial wavelength of 100 mm could be flattened with amplitude up to about 2 mm; for waves with wavelength of 10 mm, the threshold amplitude of the wafers was calculated as 0.2 microns; and with wavelength of 1 mm, the threshold was found to be just about 0.5 nm.
- shape features are not sinusoidal and can have any shape. Therefore, sharpness of the peaks, or curvature of their shape near the apex of the peak or valley, is more appropriate to characterize their impact on device yields.
- Wafers have irregularities in shape due to inherent imperfections in wafer manufacturing processes, and wafer shape is one of the key parameters of silicon wafers. Wafer shape is defined as geometry variation of the medial plane of the wafer in a free state [“SEMI M49-0312 Guide for specifying geometry measurement systems for silicon wafers for the 130 nm to 22 nm technology generations,” (2012); Semiconductor Equipment and Materials International; http://www.semi.org]. Wafer shape may have impact on yields in a device fabrication line.
- One type of wafer irregularity referred to as waviness, is a measure of variations in thickness of a wafer or variations in the wafer surface's height. Waviness represents irregularities in the wafer's shape with spatial frequencies which fall between local geometry and bowing/warping. Wavy shape features are formed during sawing of silicon ingots and survive through grinding and/or polishing.
- Wafer shape can be a critical parameter for process steps which require the wafer be flattened by a vacuum, electrostatic chuck, or a semi-flexible chuck.
- Process steps in device manufacturing which use wafer chucking, and thus may be affected by waviness, include photolithography and chemical-mechanical planarization/polishing (CMP). Wafer bonding, arguably, could also see impact from waviness of the wafer.
- a silicon wafer may, within a limited range, plastically deform and adhere to the shape of the chuck under the clamping pressure.
- shape deviations do not lend themselves to flattening under clamping pressure, some parts of the exposed area may be out of focus, or a lithography scanner may have difficulties exposing a die correctly.
- CMP is a touch-polishing process which can be utilized to remove the layer of oxide deposited on top of the nitride layer.
- a possible mechanism of failure at CMP caused by waviness was discussed by K. Turner [“Role of process-induced wafer geometry changes in advanced semiconductor manufacturing”, presentation on Jul. 9, 2014 at Semicon West 2014 conference, San Francisco, CA, 2014]. If a wafer has a significant waviness, either oxide will not be completely removed in wafer valleys, or nitride will be over-polished at the wafer's high spots. In addition, depth of shallow trench isolation wells can become variable.
- Wafer waviness can lead to a variable nitride thickness after CMP and a variable Shallow Trench Isolation (STI) depth.
- STI Shallow Trench Isolation
- Wafer surface height represents the thickness of a wafer at a particular location within the wafer.
- Bow is a parameter representing the height difference of the median surface at a center of a wafer compared to the height of a plane intersecting three median surface points about the edge of the wafer.
- Warp is similar to bow, but instead compares the median surface of the entire wafer rather than only at the center of the wafer.
- Present techniques also utilize thickness measurements to provide a curvature profile of the wafer by taking the second derivative of a data curve representing thickness measurements along a radius of the wafer.
- Patent WO 2021/084939 calculates a first or second derivative of the wafer shape and characterizes waviness as a maximum differential value within pre-defined areas of the wafer (cut-in area, center of the wafer, and cut-out area). Separate limits for the derivative of the shape can be set for these three areas for grading the wafers.
- the first of the two patents are sensitive to the height of the waviness features, but not sensitive to the “sharpness”, or “curvature” of the peaks and valleys at their apexes.
- the second patent is sensitive to the “sharpness” of the features, but does not take into account their amplitude.
- the present disclosure provides a method for processing silicon wafers, the method comprising cutting an ingot to form a wafer, extracting from measured shape data a cross-sectional profile, the cross-sectional profile passing through the center of the wafer and being aligned with a cutting direction of an ingot, interpolating the shape data with a fixed and pre-determined step size, fitting a first second-degree polynomial to the cross-sectional profile, determining a residual profile by subtracting the polynomial from the cross-sectional profile, fitting a second second-degree polynomial to the residual profile using a sliding window of pre-determined width to determine a position, height, and curvature of each peak and valley of the residual profile, determining a waviness parameter based on the position, height, and curvature of each peak and valley of the residual profile, and further processing the wafer based on a comparison of the waviness parameter to a predetermined waviness threshold.
- FIG. 1 depicts a graphical representation of a wafer profile and a corresponding fit according to an embodiment of the invention
- FIG. 2 depicts a graphical representation of a residual profile according to an embodiment of the invention.
- FIG. 3 depicts a two-dimensional map of a wafer according to an embodiment of the invention.
- Embodiments of the present invention provide different methods of processing wafers based on data processing from those known in the prior art.
- parabolic fit to the linear cross-sectional profile of the wafer is determined to eliminate the bowl-like shape caused by strain from the wafer's backside layer.
- parabolic fit within a moving window is used to identify and quantify peaks and valleys.
- Embodiments of the present invention provide important advantages over prior art systems and methods. For example, disclosed embodiments provide waviness measurements which are sensitive to both height and sharpness of a wafer. Disclosed embodiments combine contributions from all features on the wafer in a single dimensionless parameter.
- Metrology tools manufacturers have recognized that there is a correlation between a typical amplitude of shape features on the wafers and their spatial wavelength.
- a whole range of wafer geometry metrics has been developed.
- bow and warp metrics are sensitive to shape features with wavelengths similar to the radius of the wafer.
- Bow and warp metrics have relatively high amplitude, from several microns to tens and even over hundred microns, and have relatively large spatial wavelengths approximately in the range of tens to hundreds of centimeters.
- Local geometry metrics e.g., site flatness quality requirements (SFQR) characterize features with the size on the scale of several centimeters, but amplitude of those features is much less than the amplitude of bow and warp features and can be as low as a few microns.
- SQR site flatness quality requirements
- Nanotopography characterizes even shorter spatial wavelengths (around 1-2 cm in size or less) with even smaller amplitudes. Finally, even finer features are captured by the roughness metric which starts from millimeter size features with very small amplitude and goes down into the microns range. Due to the way how local geometry, NT, and roughness are computed, they, strictly speaking, are flatness metrics rather than shape metrics. Yet, in theory, one can apply NT and local geometry metrics to wafer shape data.
- the area in the middle of the range of spatial wavelengths is what is characterized as “waviness” throughout the present disclosure, and is not covered by the commercially available metrology tools.
- the warp metric can detect oscillations in shape in the “waviness” spatial frequency range. However, as amplitude of waviness features is typically lower than amplitude of warp features, rejection limits appropriate for bow and warp will be too high for waviness and cannot be used to reject non-compliant wafers. Bow and warp metrics do not have the ability to distinguish shape features based on their spatial wavelength.
- Embodiments of the present invention develop a metrology to characterize and quantify waviness in wafer shape.
- the metrology for characterization of waviness includes dimensionless parameters which take into account both amplitude of peaks and valleys, and sharpness of valley shapes.
- Waviness, and the parameters used to quantify waviness can be used for screening wafers for defects and/or quality control.
- Wafer waviness is often caused by multi-wire wafer sawing, a process in which ingot segments are cut into individual wafers by thin wires. Specifically, wafer height variations are typically introduced in an oscillating manner orthogonal to the extent of the cutting wires. The lateral movement or wandering of the wires as they proceed through an ingot causes these wave-like variations in cutting position. Because a cutting wire tends to wander sideways, wires cutting ingots tend to wander along the entire ingot that is being cut, thus producing wave-like variations that extend across the whole wafer.
- the amplitude of wavy features is measured in microns and is not visible to the human eye. Waves of such small amplitude create only very weak signal in bow and warp metrics. This signal is usually very small compared to typical bow and warp rejection limits and cannot be used to identify and screen out such wafers.
- Waviness can be characterized mathematically as the sum of absolute values of products of heights and curvatures of all peaks and valleys detected in a wafer.
- WavPar 1000 ⁇ i
- WavPar 1000 ⁇ i
- WavPar 1000 ⁇ i
- the waviness parameter is dimensionless. A larger number of waves in the wafer, a higher amplitude of waves, or sharper, and narrower peaks and valleys all lead to a higher value of the waviness parameter.
- the coefficient of 1000 was introduced to bring WavPar values into an easy-to-read range, typically over 1.
- the starting point of the assessment of waviness is to extract a linear scan along the cutting direction from the shape measurement.
- Some embodiments described in the present disclosure use data measured on 200 mm tools, although the same method can be equally applied to measurements done on tools using 300 mm technology.
- Both sizes of tools are designed to measure geometry of the wafer using either capacitive or optical methods. Both tools can calculate dimensions of a wafer's surface shape.
- the cutting direction during wire-cutting of the wafer can be determined relative to a notch in the wafer. The cutting direction is determined for each production lot from data recorded in a production database when a particular ingot segment was mounted for slicing.
- the spatial resolution of a wafer scan may be determined by a scanner's measurement mode.
- data is interpolated in a linear scan to a predefined step size which can be any number. In one embodiment, it is a 1 mm step.
- Silicon wafers especially in 200 mm technology, oftentimes have a bowl-like shape.
- This shape is created primarily by stress from backside polysilicon and low temperature oxide (LTO) layers, but can also be impacted by stress from the epitaxial layer.
- LTO backside polysilicon and low temperature oxide
- the bowl-like shape of wafer reduced or eliminated in order to improve detection of peaks and valleys related to waviness. This is accomplished by fitting the shape profile of the wafer with a second order polynomial, such as a parabola. The parabolic fit is then subtracted from the raw linear shape profile (“shape curve”), leaving behind what are referred to herein as “residuals”.
- FIG. 1 depicts a profile 10 of a wafer and a corresponding parabolic fit 12 .
- the profile 10 is understood to be exemplary only, as all wafers will have individually determinable profiles that may vary and have differing profiles, and therefore different corresponding parabolic fits.
- the profile 10 represents a profile of a surface of a wafer measured in a cutting direction in which the wafer was cut from an ingot.
- the profile 10 has a very pronounced wavy feature caused by multi-wire sawing, as shown by the oscillating profile 10 in the vertical axis.
- the parabolic fit 12 is a second degree polynomial calculated based on the individual data points that make up the profile 10 .
- FIG. 2 depicts a residual 20 , which represents data points correlating to the difference between the profile 10 of the exemplary wafer of FIG. 1 and the parabolic fit 12 .
- the residual 20 is calculated by subtracting the parabolic fit 12 from the profile 10 .
- Subsequent steps in assessing waviness require identifying peaks and valleys of the residual 20 .
- Coefficient a of this parabolic equation is the measure of curvature of the peak. Both the amplitude of the peak and its position/height can also be easily determined from this formula:
- FIG. 2 provides an illustration of a sliding window 22 that is exemplary only and captures only a window that has already progressed from the leftmost part of residuals 20 to the center of residuals 20 .
- a parabolic fit is done using data points within this sliding window 22 .
- the window should be sufficiently narrow to enable the algorithm to separate individual peaks and valleys and achieve a good quality of fit.
- a variety of window widths may provide adequate results.
- the width of the sliding window 22 is set to 20 mm. The criterion for selection of the width of sliding window 22 is based on the ability of an algorithm to separate wafers with a significant waviness from wafers with low waviness.
- the sliding window 22 moves or “slides” one data point at a time along residual 20 . For example, if interpolation was done with a step size of 1 mm, the sliding window 22 moves 1 mm at a time.
- Peaks and valleys of the residual may be identified by a software algorithm based on detection of the peaks and valleys in multiple adjacent positions of the sliding window 22 as it moves.
- the software algorithm separates peaks and valleys with amplitude over a predetermined threshold to help eliminate noise.
- the curvatures and amplitudes for each peak are averaged by the software algorithm.
- the respective height 24 of each peak and valley relative to the horizontal axis is determined. Because the horizontal axis corresponds to a wafer having perfect flatness with no variation in height, the respective height 24 of each peak and valley corresponds to wafer shape defects which, if removed, would create a flat wafer.
- the Waviness Parameter formula is used to calculate a total contribution of all peaks and valleys to the Waviness Parameter. For example, the wafer represented by the residual 20 of FIG. 2 would have approximately two peaks and two valleys, resulting in a WavPar that is the sum of four components.
- wafers of varying shape will have variable numbers of peaks and valleys in varying patterns.
- the formulas and methods described above result in a WavPar value that is the sum of identified peaks and valleys representing height variations in the wafer, thus providing advantageous insight into the shape of the wafer over traditional wafer metrics.
- the waviness analysis calculates a linear shape profile from a two-dimensional shape map of the wafer.
- Such embodiments enable exclusion of data points within a certain radius from the center of the wafer (approximately 40 to 45 mm, but up to the radius of the wafer).
- This method may be particularly useful, for example, in 200 mm technology, where older generation metrology tools are equipped with a small diameter chuck to hold the wafer during measurement.
- the wafer is initially chucked in the center, scanned using capacitance probes from the wafer edge to the edge of the chuck. Then the wafer is re-chucked closer to the edge, and the center area is scanned.
- Wafer chucking even on a small chuck, leads to some degree of deformation of a wafer's shape, as the wafer is partly flattened in the chuck area.
- Older generation tool software attempts to stitch wafer maps collected with the two chucking locations. Since wafer shape was distorted by chucking in the two chucking locations, there is no perfect overlap between these two maps. The process of stitching the maps may create artifacts in the wafer shape, for example because a circular area in the chuck area does not smoothly follow the area outside of the chuck, and can, in rare cases, even lead to false peaks in wafer waviness profiles. Removal of data points from the center of the wafer, from a circle in the middle with radius equal or greater than the chuck size, enables determination of a cleaner linear “shape profile” without such artifacts.
- a first step to obtaining a cleaner linear shape profile described above is to fit the three-dimensional shape of the wafer with a paraboloid (a three-dimensional surface obtained by a rotating parabola).
- This fit enables removal of shape variations of the wafer, for example bowl-like or potato-chip-like shapes of the wafer. Subtraction of the fitted paraboloid from measured wafer shape yields two-dimensional residuals.
- a second step is to exclude data points within a pre-defined radius in the center of the wafer. This enables exclusion of areas with potential artifacts in measured data.
- FIG. 3 shows an exemplary two-dimensional map 30 of a wafer profile 32 having a center area 34 .
- Linear shape profiles are calculated by averaging data points 38 along vertical lines 36 within the wafer profile 32 for each x-axis value rounded to a predefined step size.
- the vertical lines 36 and corresponding data points 38 provide a schematic visualization of data point averaging to eliminate artifacts in or near the wafer center area 34 .
- the x-axis represents the cutting direction during wafer cutting and the y-axis represents a direction of extent of cutting wires.
- An analysis of waviness at the end of a wafering process can be used to reject wafers with waviness which exceeds a pre-defined rejection limit determined based on customer needs and sensitivity. Measurements of waviness after multi-wire slicing enables one to implement wafer screening after multi-wire sawing in order to reject wafers which are unlikely to pass end of line inspection early in the process. Additionally, post-multi-wire sawing waviness data can be utilized to monitor performance of the multi-wire saws and make adjustments to sawing process as needed. Post-cutting processes, such as grinding, polishing, and/or epitaxy can also be conducted based on waviness parameter determinations.
- post-cutting processes may only be implemented for wafers that do not comport within a predetermined threshold of acceptable waviness.
- the degree number of post-processing techniques and/or the degree of post-processing techniques may also be determined based on the determined waviness parameter. In each instance, the waviness parameter determination may thus enhance both quality control processes and the quality of an individual wafer itself.
- the waviness parameter of one wafer can be used to predict the waviness of other wafers, thereby enabling efficient quality control decisions regarding production lots. For example, a determined waviness parameter can be used to predict the waviness of other wafers that would be produced by the same ingot and/or set of multi-wires used in the cutting process. Then, depending on the predicted waviness parameter, the wafers may need to be sorted and or post-processed in different manners depending on the predicted waviness parameter. In this manner, predicted waviness parameters that are within quality control limits can allow for efficient production of wafers without time- and resource-consuming measurements processes for independently determining the waviness of each wafer.
- the waviness parameter enables feedback for performance for multi-wire saws and/or other equipment.
- a baseline waviness parameter may be established by statistical means (e.g. an average or median of historical waviness parameters). Then, the waviness parameter associated with a particular set of multi-wires may be compared to the baseline waviness parameter. Such a comparison would enable quick determination of whether the multi-wires (or other equipment) are operating within acceptable tolerances. Equipment maintenance decisions can then be made based on the comparison of a waviness parameter to the baseline waviness parameter.
- the recitation of “at least one of A, B and C” should be interpreted as one or more of a group of elements consisting of A, B and C, and should not be interpreted as requiring at least one of each of the listed elements A, B and C, regardless of whether A, B and C are related as categories or otherwise.
- the recitation of “A, B and/or C” or “at least one of A, B or C” should be interpreted as including any singular entity from the listed elements, e.g., A, any subset from the listed elements, e.g., A and B, or the entire list of elements A, B and C.
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
Abstract
Description
WavPar=1000×Σi|Heighti×Curvaturei|
y=ax 2 +bx+c
-
- Peak position, P:
-
- and peak/valley height, H:
H=aP 2 +bP+c
- and peak/valley height, H:
a(x 2 +y 2)+bz+c=0
or, in the more general case of a hyperbolic paraboloid (which can form a shape similar to shape of a potato chip),
ax 2+by2 +cz+d=0
Claims (19)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/724,503 US12226873B2 (en) | 2022-04-20 | 2022-04-20 | System and method for processing silicon wafers |
| TW112113305A TWI859807B (en) | 2022-04-20 | 2023-04-10 | Method for processing silicon wafers |
| JP2024561943A JP2025514079A (en) | 2022-04-20 | 2023-04-18 | Systems and methods for processing silicon wafers - Patents.com |
| PCT/EP2023/060035 WO2023203035A1 (en) | 2022-04-20 | 2023-04-18 | System and method for processing silicon wafers |
| CN202380034966.4A CN119110892A (en) | 2022-04-20 | 2023-04-18 | System and method for processing silicon wafers |
| KR1020247038174A KR20250006147A (en) | 2022-04-20 | 2023-04-18 | Systems and methods for processing silicon wafers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/724,503 US12226873B2 (en) | 2022-04-20 | 2022-04-20 | System and method for processing silicon wafers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20230339069A1 US20230339069A1 (en) | 2023-10-26 |
| US12226873B2 true US12226873B2 (en) | 2025-02-18 |
Family
ID=86286140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US17/724,503 Active 2043-06-30 US12226873B2 (en) | 2022-04-20 | 2022-04-20 | System and method for processing silicon wafers |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US12226873B2 (en) |
| JP (1) | JP2025514079A (en) |
| KR (1) | KR20250006147A (en) |
| CN (1) | CN119110892A (en) |
| TW (1) | TWI859807B (en) |
| WO (1) | WO2023203035A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7172951B2 (en) * | 2019-10-31 | 2022-11-16 | 信越半導体株式会社 | Semiconductor wafer evaluation method, semiconductor wafer sorting method, and device manufacturing method |
| DE102024115228A1 (en) * | 2024-05-31 | 2025-12-04 | HELLA GmbH & Co. KGaA | Method for determining the waviness of a component's surface and surface measuring device for carrying out such a method |
| CN118431103B (en) * | 2024-07-05 | 2024-10-22 | 西安奕斯伟材料科技股份有限公司 | Wafer and method, device, equipment and medium for predicting surface nano morphology of wafer |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291415A (en) | 1991-12-13 | 1994-03-01 | Hughes Aircraft Company | Method to determine tool paths for thinning and correcting errors in thickness profiles of films |
| US6057170A (en) * | 1999-03-05 | 2000-05-02 | Memc Electronic Materials, Inc. | Method of measuring waviness in silicon wafers |
| US6613591B1 (en) * | 2002-03-07 | 2003-09-02 | Memc Electronic Materials, Inc. | Method of estimating post-polishing waviness characteristics of a semiconductor wafer |
| WO2006018961A1 (en) | 2004-08-17 | 2006-02-23 | Shin-Etsu Handotai Co., Ltd. | Method of measuring semiconductor wafer, method of supervising production process therefor and process for producing semiconductor wafer |
| US20120178346A1 (en) | 2011-01-12 | 2012-07-12 | Siltronic Ag | Method for cooling a workpiece made of semiconductor material during wire sawing |
| US20130333682A1 (en) * | 2012-06-14 | 2013-12-19 | Siltronic Ag | Method for simultaneously slicing a multiplicity of wafers from a cylindrical workpiece |
| US20140117380A1 (en) * | 2012-10-26 | 2014-05-01 | Dow Corning Corporation | Flat sic semiconductor substrate |
| US20190333775A1 (en) * | 2015-11-26 | 2019-10-31 | Sumco Corporation | Wafer polishing method |
| TW202010995A (en) | 2018-07-26 | 2020-03-16 | 荷蘭商Asml荷蘭公司 | Method for determining an etch profile of a layer of a wafer for a simulation system |
| WO2021084939A1 (en) | 2019-10-31 | 2021-05-06 | 信越半導体株式会社 | Semiconductor wafer evaluation method, semiconductor wafer sorting method, and device manufacturing method |
| US11348844B2 (en) * | 2018-07-20 | 2022-05-31 | Denso Corporation | Semiconductor wafer including silicon carbide wafer and method for manufacturing silicon carbide semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5074845B2 (en) * | 2007-07-23 | 2012-11-14 | Sumco Techxiv株式会社 | Semiconductor wafer grinding method and semiconductor wafer processing method |
| JP6443520B1 (en) * | 2017-10-02 | 2018-12-26 | 株式会社Sumco | Semiconductor wafer evaluation method and semiconductor wafer manufacturing method using the method |
-
2022
- 2022-04-20 US US17/724,503 patent/US12226873B2/en active Active
-
2023
- 2023-04-10 TW TW112113305A patent/TWI859807B/en active
- 2023-04-18 KR KR1020247038174A patent/KR20250006147A/en active Pending
- 2023-04-18 CN CN202380034966.4A patent/CN119110892A/en active Pending
- 2023-04-18 JP JP2024561943A patent/JP2025514079A/en active Pending
- 2023-04-18 WO PCT/EP2023/060035 patent/WO2023203035A1/en not_active Ceased
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291415A (en) | 1991-12-13 | 1994-03-01 | Hughes Aircraft Company | Method to determine tool paths for thinning and correcting errors in thickness profiles of films |
| US6057170A (en) * | 1999-03-05 | 2000-05-02 | Memc Electronic Materials, Inc. | Method of measuring waviness in silicon wafers |
| US6613591B1 (en) * | 2002-03-07 | 2003-09-02 | Memc Electronic Materials, Inc. | Method of estimating post-polishing waviness characteristics of a semiconductor wafer |
| WO2003077309A2 (en) | 2002-03-07 | 2003-09-18 | Memc Electronic Materials, Inc. | Method of predicting post-polishing waviness characteristics of a semiconductor wafer |
| WO2006018961A1 (en) | 2004-08-17 | 2006-02-23 | Shin-Etsu Handotai Co., Ltd. | Method of measuring semiconductor wafer, method of supervising production process therefor and process for producing semiconductor wafer |
| US20120178346A1 (en) | 2011-01-12 | 2012-07-12 | Siltronic Ag | Method for cooling a workpiece made of semiconductor material during wire sawing |
| US20130333682A1 (en) * | 2012-06-14 | 2013-12-19 | Siltronic Ag | Method for simultaneously slicing a multiplicity of wafers from a cylindrical workpiece |
| US20140117380A1 (en) * | 2012-10-26 | 2014-05-01 | Dow Corning Corporation | Flat sic semiconductor substrate |
| US20190333775A1 (en) * | 2015-11-26 | 2019-10-31 | Sumco Corporation | Wafer polishing method |
| US11348844B2 (en) * | 2018-07-20 | 2022-05-31 | Denso Corporation | Semiconductor wafer including silicon carbide wafer and method for manufacturing silicon carbide semiconductor device |
| TW202010995A (en) | 2018-07-26 | 2020-03-16 | 荷蘭商Asml荷蘭公司 | Method for determining an etch profile of a layer of a wafer for a simulation system |
| US20210150116A1 (en) | 2018-07-26 | 2021-05-20 | Asml Netherlands B.V. | Method for determining an etch profile of a layer of a wafer for a simulation system |
| WO2021084939A1 (en) | 2019-10-31 | 2021-05-06 | 信越半導体株式会社 | Semiconductor wafer evaluation method, semiconductor wafer sorting method, and device manufacturing method |
| US20240128130A1 (en) * | 2019-10-31 | 2024-04-18 | Shin-Etsu Handotai Co., Ltd. | Method for evaluating semiconductor wafer, method for selecting semiconductor wafer and method for fabricating device |
Non-Patent Citations (2)
| Title |
|---|
| A. Nutsch, et al., Determination of Flatness on Patterned Wafer Surfaces Using Wave-front Sensing Methods, Ninth International Symposium on Laser Metrology, Sep. 2008, pp. 1-12 , vol. 7155, Fraunhofer IISB, Germany, Imaging Optic, France. |
| Van Wingerden et al., Optical profiler for low-reflectance ultrasmooth Surfaces, Optical Engineering, Nov. 1992, pp. 2450-2457, vol. 31, No. 11, Bellingham, WA, US. |
Also Published As
| Publication number | Publication date |
|---|---|
| US20230339069A1 (en) | 2023-10-26 |
| KR20250006147A (en) | 2025-01-10 |
| TWI859807B (en) | 2024-10-21 |
| WO2023203035A1 (en) | 2023-10-26 |
| JP2025514079A (en) | 2025-05-02 |
| TW202342254A (en) | 2023-11-01 |
| CN119110892A (en) | 2024-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12226873B2 (en) | System and method for processing silicon wafers | |
| JP6312370B2 (en) | System and method for detecting, classifying and quantifying wafer surface features with a wafer geometry metrology tool | |
| JP6265608B2 (en) | Advanced site-based nanotopography system and method for wafer surface metrology | |
| CN104428882B (en) | Evaluation method and production method for semiconductor wafers | |
| JP4464033B2 (en) | Semiconductor wafer shape evaluation method and shape evaluation apparatus | |
| CN114631171B (en) | Semiconductor wafer evaluation method, semiconductor wafer sorting method, and device manufacturing method | |
| JP6443520B1 (en) | Semiconductor wafer evaluation method and semiconductor wafer manufacturing method using the method | |
| CN111912379A (en) | Method for inspecting processing quality of processed surface of wafer and cutting quality of cutting surface | |
| EP4388579B1 (en) | Systems and methods for processing semiconductor wafers using front-end processed wafer geometry metrics | |
| EP4276890A1 (en) | System and method for processing silicon wafers | |
| JP4420023B2 (en) | Semiconductor wafer measurement method, manufacturing process management method, and semiconductor wafer manufacturing method | |
| US20030170920A1 (en) | Method of estimating post-polishing waviness characteristics of a semiconductor wafer | |
| KR20220164489A (en) | Shape measurement method and polishing method of DIC defect of silicon wafer | |
| JP3982336B2 (en) | Semiconductor wafer processing method and plasma etching apparatus | |
| CN117981065A (en) | Evaluation method and evaluation system for processed modified layer | |
| JP2006294774A (en) | Semiconductor wafer evaluation method and evaluation apparatus, and semiconductor wafer manufacturing method | |
| KR102921482B1 (en) | Evaluation method of semiconductor wafers, selection method of semiconductor wafers, and manufacturing method of devices | |
| KR102896814B1 (en) | Double-sided polishing device and double-sided polishing method for work | |
| WO2024057773A1 (en) | Debris determination method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| AS | Assignment |
Owner name: SILTRONIC CORPORATION, OREGON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ISTRATOV, ANDREI;WU, TOM;ZAHNWEH, KATHARINA;SIGNING DATES FROM 20220425 TO 20220426;REEL/FRAME:059803/0282 |
|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
| STCF | Information on status: patent grant |
Free format text: PATENTED CASE |