US12224335B2 - Semiconductor device and fabrication method thereof - Google Patents

Semiconductor device and fabrication method thereof Download PDF

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US12224335B2
US12224335B2 US17/867,640 US202217867640A US12224335B2 US 12224335 B2 US12224335 B2 US 12224335B2 US 202217867640 A US202217867640 A US 202217867640A US 12224335 B2 US12224335 B2 US 12224335B2
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conductivity type
spacer
heavily doped
doped region
substrate
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Ching-Chung Yang
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United Microelectronics Corp
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    • H01L29/6656—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/01306—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H01L29/66492—
    • H01L29/7833—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H10P30/22—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H10P30/204—
    • H10P30/21—

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor device and a fabrication method thereof.
  • the chip size is getting smaller and smaller, and the width of the spacer next to the gate is also shrinking. This affects the performance of the medium-voltage devices, exacerbates the gate-induced drain leakage (GIDL) effect, and increases the leakage current (IoT) variation.
  • GIDL gate-induced drain leakage
  • IoT leakage current
  • One aspect of the invention provides a semiconductor device including a substrate of a first conductivity type; a first heavily doped region of a second conductivity type in the substrate; a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.
  • the hard mask layer comprises a silicon nitride layer.
  • the silicon nitride layer has a thickness of about 200 angstroms.
  • the hard mask layer further comprises a silicon oxide layer.
  • the silicon oxide layer has a thickness of about 700 angstroms.
  • the gate is a polysilicon gate.
  • the spacer comprises a silicon nitride spacer.
  • the spacer further comprises a silicon oxide spacer.
  • the semiconductor device further includes a well of the first conductivity type in the substrate; a first drift region of the second conductivity type disposed in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
  • the first conductivity type is P type and the second conductivity type is N type.
  • a substrate of a first conductivity type is provided.
  • a first heavily doped region of a second conductivity type is formed in the substrate.
  • a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region is formed in the substrate.
  • a channel region is formed in the substrate and between the first heavily doped region and the second heavily doped region.
  • a gate is formed on the channel region.
  • a hard mask layer is formed to cover a top surface and a sidewall of the gate.
  • a spacer is formed on a sidewall of the hard mask layer.
  • the hard mask layer comprises a silicon nitride layer.
  • the silicon nitride layer has a thickness of about 200 angstroms.
  • the hard mask layer further comprises a silicon oxide layer.
  • the silicon oxide layer has a thickness of about 700 angstroms.
  • the gate is a polysilicon gate.
  • the spacer comprises a silicon nitride spacer.
  • the spacer further comprises a silicon oxide spacer.
  • the method further includes the steps of forming a well of the first conductivity type in the substrate; forming a first drift region of the second conductivity type in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and forming a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
  • the first conductivity type is P type and the second conductivity type is N type.
  • FIG. 1 to FIG. 6 are schematic diagrams illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 to FIG. 6 are schematic diagrams of a method for fabricating a semiconductor device 10 according to an embodiment of the present invention.
  • the semiconductor device 10 may be a semiconductor medium-voltage device, for example, a medium-voltage device operated under a voltage range of 6-12V.
  • NMOS transistors for example, those skilled in the art should understand that the present invention can also be applied to PMOS transistors.
  • a substrate 100 having a first conductivity type such as, but not limited to, a silicon substrate is first provided.
  • the first conductivity type may be a P type.
  • a deep well 102 of the second conductivity type for example, a deep N-type well, may be optionally formed in the substrate 100 .
  • a well 104 of the first conductivity type for example, a P-type well, may be formed in the deep well 102 .
  • a first drift region 106 with the second conductivity type and a second drift region 108 with the second conductivity type can be formed in the well 104 .
  • the second conductivity type is N-type.
  • the first drift region 106 and the second drift region 108 may be N-type drift regions.
  • a channel region CH is defined between the first drift region 106 and the second drift region 108 .
  • a gate dielectric layer 110 and a polysilicon layer 120 are sequentially formed on the substrate 100 .
  • the gate dielectric layer 110 may be a silicon oxide layer.
  • the gate 120 a has a width W 1 .
  • the hard mask layer 130 is formed on the substrate 100 to cover the top surface S 1 and the sidewall S 2 of the gate 120 a .
  • the hard mask layer 130 may include a silicon nitride layer 132 .
  • the thickness of the silicon nitride layer 132 is about 200 angstroms.
  • the hard mask layer 130 may further include a silicon oxide layer 134 .
  • the thickness of the silicon oxide layer 134 is about 700 angstroms.
  • a photoresist pattern PR is formed on the hard mask layer 130 , which is located directly above the gate 120 a .
  • the photoresist pattern PR has a width W 2 .
  • the width W 2 of the photoresist pattern PR is greater than the width W 1 of the gate 120 a .
  • both sides of the photoresist pattern PR extend beyond the two sides of the gate 120 a by the width t, which may range between 0.05-0.09 m.
  • an etching process is then performed to remove the hard mask layer 130 not covered by the photoresist pattern PR, so that the remaining hard mask layer 130 a including the remaining silicon nitride layer 132 a and the remaining hard mask layer 130 a covers the top surface S 1 and the sidewall S 2 of the gate 120 a .
  • the hard mask layer 130 a has sidewalls S 3 .
  • the sidewalls S 3 of the hard mask layer 130 a may be vertical sidewalls.
  • the spacer SP may include a silicon nitride spacer. According to an embodiment of the present invention, the spacer SP may further include a silicon oxide spacer.
  • an ion implantation process is performed to form a first heavily doped region 106 a and a second heavily doped region 108 a with a second conductivity type in the substrate 100 .
  • the first heavily doped region 106 a is disposed in the first drift region 106 and adjacent to the spacer SP.
  • the second heavily doped region 108 a is disposed within the second drift region 108 and adjacent to the spacer SP.
  • the first heavily doped region 106 a is spaced apart from the second heavily doped region 108 a.
  • the semiconductor device 10 includes a substrate 100 having a first conductivity type (e.g., P-type); a first heavily doped region 106 a located in the substrate 100 and having a second conductivity type (e.g., N-type); a second heavily doped region 108 a , located in the substrate 100 , separated from the first heavily doped region 106 a and having the second conductivity type (e.g., N-type); a channel region CH, located in the substrate 100 between the first heavily doped region 106 a and the second heavily doped region 108 a ; a gate 120 a , disposed on the channel region CH; a hard mask layer 130 a , covering the top surface S 1 and sidewall S 2 of the gate 120 a ; and spacers SP, disposed on the sidewalls S 3 of the hard mask layer 130 a.
  • a first conductivity type e.g., P-type
  • a first heavily doped region 106 a located in the substrate 100 and having a second conduct
  • the hard mask layer 130 a includes a silicon nitride layer 132 a .
  • the thickness of the silicon nitride layer 132 a is 200 angstroms.
  • the hard mask layer 130 a further includes a silicon oxide layer 134 a .
  • the thickness of the silicon oxide layer 134 a is 700 angstroms.
  • the gate 120 a may be a polysilicon gate.
  • the spacer SP may include a silicon nitride spacer.
  • the spacer SP further includes a silicon oxide spacer.
  • the semiconductor device 10 further includes: a well 104 in the substrate 100 and having a first conductivity type (e.g., P-type); a first drift region 106 disposed in the well 104 and having a second conductivity type conductivity type (e.g., N-type), wherein the first heavily doped region 106 a is disposed in the first drift region 106 and adjacent to the spacer SP.
  • a second drift region 108 is disposed in the well 104 and has the second conductivity type (e.g., N-type). The second heavily doped region 108 a is disposed within the second drift region 108 and adjacent to the spacer SP.
  • One feature of the present invention is that the top surface S 1 and the sidewall S 2 of the gate 120 a are covered with the hard mask layer 130 a , and then the spacer SP is formed on the sidewall S 3 of the hard mask layer 130 a .

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Abstract

A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to the field of semiconductor technology, in particular to a semiconductor device and a fabrication method thereof.
2. Description of the Prior Art
As the semiconductor manufacturing process evolves, the chip size is getting smaller and smaller, and the width of the spacer next to the gate is also shrinking. This affects the performance of the medium-voltage devices, exacerbates the gate-induced drain leakage (GIDL) effect, and increases the leakage current (IoT) variation.
Therefore, there is still a need in the technical field for an improved semiconductor medium-voltage device and a manufacturing method, which can solve the GIDL effect caused by the shrinking of the device size.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide an improved semiconductor device and a method of fabricating the same in order to solve the above-mentioned prior art deficiencies or shortcomings.
One aspect of the invention provides a semiconductor device including a substrate of a first conductivity type; a first heavily doped region of a second conductivity type in the substrate; a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.
According to some embodiments, the hard mask layer comprises a silicon nitride layer.
According to some embodiments, the silicon nitride layer has a thickness of about 200 angstroms.
According to some embodiments, the hard mask layer further comprises a silicon oxide layer.
According to some embodiments, the silicon oxide layer has a thickness of about 700 angstroms.
According to some embodiments, the gate is a polysilicon gate.
According to some embodiments, the spacer comprises a silicon nitride spacer.
According to some embodiments, the spacer further comprises a silicon oxide spacer.
According to some embodiments, the semiconductor device further includes a well of the first conductivity type in the substrate; a first drift region of the second conductivity type disposed in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
According to some embodiments, the first conductivity type is P type and the second conductivity type is N type.
Another aspect of the invention provides a method of fabricating a semiconductor device. A substrate of a first conductivity type is provided. A first heavily doped region of a second conductivity type is formed in the substrate. A second heavily doped region of the second conductivity type spaced apart from the first heavily doped region is formed in the substrate. A channel region is formed in the substrate and between the first heavily doped region and the second heavily doped region. A gate is formed on the channel region. A hard mask layer is formed to cover a top surface and a sidewall of the gate. A spacer is formed on a sidewall of the hard mask layer.
According to some embodiments, the hard mask layer comprises a silicon nitride layer.
According to some embodiments, the silicon nitride layer has a thickness of about 200 angstroms.
According to some embodiments, the hard mask layer further comprises a silicon oxide layer.
According to some embodiments, the silicon oxide layer has a thickness of about 700 angstroms.
According to some embodiments, the gate is a polysilicon gate.
According to some embodiments, the spacer comprises a silicon nitride spacer.
According to some embodiments, the spacer further comprises a silicon oxide spacer.
According to some embodiments, the method further includes the steps of forming a well of the first conductivity type in the substrate; forming a first drift region of the second conductivity type in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and forming a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
According to some embodiments, the first conductivity type is P type and the second conductivity type is N type.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 to FIG. 6 are schematic diagrams illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
 DETAILED DESCRIPTION
In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.
Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.
Please refer to FIG. 1 to FIG. 6 , which are schematic diagrams of a method for fabricating a semiconductor device 10 according to an embodiment of the present invention. According to an embodiment of the present invention, the semiconductor device 10 may be a semiconductor medium-voltage device, for example, a medium-voltage device operated under a voltage range of 6-12V. Although the following embodiments are described by taking NMOS transistors as an example, those skilled in the art should understand that the present invention can also be applied to PMOS transistors.
As shown in FIG. 1 , a substrate 100 having a first conductivity type, such as, but not limited to, a silicon substrate is first provided. According to an embodiment of the present invention, for example, the first conductivity type may be a P type. According to an embodiment of the present invention, a deep well 102 of the second conductivity type, for example, a deep N-type well, may be optionally formed in the substrate 100. According to an embodiment of the present invention, a well 104 of the first conductivity type, for example, a P-type well, may be formed in the deep well 102.
Next, a first drift region 106 with the second conductivity type and a second drift region 108 with the second conductivity type can be formed in the well 104. For example, the second conductivity type is N-type. The first drift region 106 and the second drift region 108 may be N-type drift regions. According to an embodiment of the present invention, a channel region CH is defined between the first drift region 106 and the second drift region 108. Next, a gate dielectric layer 110 and a polysilicon layer 120 are sequentially formed on the substrate 100. According to an embodiment of the present invention, for example, the gate dielectric layer 110 may be a silicon oxide layer.
As shown in FIG. 2 , next, a photolithography process and an etching process are performed to pattern the polysilicon layer 120 to form a polysilicon gate 120 a on the channel region CH. According to an embodiment of the present invention, the gate 120 a has a width W1.
As shown in FIG. 3 , next, a hard mask layer 130 is formed on the substrate 100 to cover the top surface S1 and the sidewall S2 of the gate 120 a. According to an embodiment of the present invention, the hard mask layer 130 may include a silicon nitride layer 132. According to an embodiment of the present invention, for example, the thickness of the silicon nitride layer 132 is about 200 angstroms. According to an embodiment of the present invention, the hard mask layer 130 may further include a silicon oxide layer 134. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 134 is about 700 angstroms.
As shown in FIG. 4 , next, a photoresist pattern PR is formed on the hard mask layer 130, which is located directly above the gate 120 a. According to an embodiment of the present invention, the photoresist pattern PR has a width W2. The width W2 of the photoresist pattern PR is greater than the width W1 of the gate 120 a. According to an embodiment of the present invention, both sides of the photoresist pattern PR extend beyond the two sides of the gate 120 a by the width t, which may range between 0.05-0.09 m.
As shown in FIG. 5 , an etching process is then performed to remove the hard mask layer 130 not covered by the photoresist pattern PR, so that the remaining hard mask layer 130 a including the remaining silicon nitride layer 132 a and the remaining hard mask layer 130 a covers the top surface S1 and the sidewall S2 of the gate 120 a. According to an embodiment of the present invention, the hard mask layer 130 a has sidewalls S3. According to an embodiment of the present invention, the sidewalls S3 of the hard mask layer 130 a may be vertical sidewalls.
As shown in FIG. 6 , next, spacers SP are formed on the two opposite sidewalls S3 of the hard mask layer 130 a. According to an embodiment of the present invention, the spacer SP may include a silicon nitride spacer. According to an embodiment of the present invention, the spacer SP may further include a silicon oxide spacer. Next, an ion implantation process is performed to form a first heavily doped region 106 a and a second heavily doped region 108 a with a second conductivity type in the substrate 100. The first heavily doped region 106 a is disposed in the first drift region 106 and adjacent to the spacer SP. The second heavily doped region 108 a is disposed within the second drift region 108 and adjacent to the spacer SP. The first heavily doped region 106 a is spaced apart from the second heavily doped region 108 a.
Structurally, as shown in FIG. 6 , the semiconductor device 10 includes a substrate 100 having a first conductivity type (e.g., P-type); a first heavily doped region 106 a located in the substrate 100 and having a second conductivity type (e.g., N-type); a second heavily doped region 108 a, located in the substrate 100, separated from the first heavily doped region 106 a and having the second conductivity type (e.g., N-type); a channel region CH, located in the substrate 100 between the first heavily doped region 106 a and the second heavily doped region 108 a; a gate 120 a, disposed on the channel region CH; a hard mask layer 130 a, covering the top surface S1 and sidewall S2 of the gate 120 a; and spacers SP, disposed on the sidewalls S3 of the hard mask layer 130 a.
According to an embodiment of the present invention, the hard mask layer 130 a includes a silicon nitride layer 132 a. According to an embodiment of the present invention, for example, the thickness of the silicon nitride layer 132 a is 200 angstroms. According to an embodiment of the present invention, the hard mask layer 130 a further includes a silicon oxide layer 134 a. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 134 a is 700 angstroms.
According to an embodiment of the present invention, the gate 120 a may be a polysilicon gate. According to an embodiment of the present invention, the spacer SP may include a silicon nitride spacer. According to an embodiment of the present invention, the spacer SP further includes a silicon oxide spacer.
According to an embodiment of the present invention, the semiconductor device 10 further includes: a well 104 in the substrate 100 and having a first conductivity type (e.g., P-type); a first drift region 106 disposed in the well 104 and having a second conductivity type conductivity type (e.g., N-type), wherein the first heavily doped region 106 a is disposed in the first drift region 106 and adjacent to the spacer SP. A second drift region 108 is disposed in the well 104 and has the second conductivity type (e.g., N-type). The second heavily doped region 108 a is disposed within the second drift region 108 and adjacent to the spacer SP.
One feature of the present invention is that the top surface S1 and the sidewall S2 of the gate 120 a are covered with the hard mask layer 130 a, and then the spacer SP is formed on the sidewall S3 of the hard mask layer 130 a. By providing such configuration, the leakage current problem and the GIDL effect caused by the shrinking of the device size and the thinning of the thickness of the spacer SP can be effectively solved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

What is claimed is:
1. A semiconductor device, comprising:
a substrate of a first conductivity type;
a first heavily doped region of a second conductivity type in the substrate;
a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, located in the substrate;
a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
a gate disposed on the channel region;
a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer; and
a spacer disposed on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.
2. The semiconductor device according to claim 1, wherein the silicon nitride lower layer has a thickness of about 200 angstroms.
3. The semiconductor device according to claim 1, wherein the silicon oxide upper layer has a thickness of about 700 angstroms.
4. The semiconductor device according to claim 1, wherein the spacer comprises a silicon nitride spacer.
5. The semiconductor device according to claim 4, wherein the spacer further comprises a silicon oxide spacer.
6. The semiconductor device according to claim 1 further comprising:
a well of the first conductivity type in the substrate;
a first drift region of the second conductivity type disposed in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and
a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
7. The semiconductor device according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type.
8. A method of fabricating a semiconductor device, comprising:
providing a substrate of a first conductivity type;
forming a first heavily doped region of a second conductivity type in the substrate;
forming a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, in the substrate;
forming a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
forming a gate on the channel region;
forming a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer; and
forming a spacer on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.
9. The method according to claim 8, wherein the silicon nitride lower layer has a thickness of about 200 angstroms.
10. The method according to claim 8, wherein the silicon oxide upper layer has a thickness of about 700 angstroms.
11. The method according to claim 8, wherein the spacer comprises a silicon nitride spacer.
12. The method according to claim 11, wherein the spacer further comprises a silicon oxide spacer.
13. The method according to claim 8 further comprising:
forming a well of the first conductivity type in the substrate;
forming a first drift region of the second conductivity type in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and
forming a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.
14. The method according to claim 8, wherein the first conductivity type is P type and the second conductivity type is N type.
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US20140264588A1 (en) * 2013-03-14 2014-09-18 Taiwan Semiconductor Manufacturing Co. Ltd. Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide
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