US11605563B2 - Semiconductor device with non-conformal gate dielectric layers - Google Patents

Semiconductor device with non-conformal gate dielectric layers Download PDF

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US11605563B2
US11605563B2 US17/233,098 US202117233098A US11605563B2 US 11605563 B2 US11605563 B2 US 11605563B2 US 202117233098 A US202117233098 A US 202117233098A US 11605563 B2 US11605563 B2 US 11605563B2
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layer
gate dielectric
dielectric layer
semiconductor
thickness
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US20220336609A1 (en
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Yung-Hsiang Chan
Wen-Hung Huang
Shan-Mei Liao
Kuei-Lun Lin
Jian-Hao Chen
Kuo-Feng Yu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US17/233,098 priority Critical patent/US11605563B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAN, YUNG-HSIANG, HUANG, WEN-HUNG, CHEN, Jian-hao, LIAO, Shan-mei, LIN, KUEI-LUN, YU, KUO-FENG
Priority to TW111107300A priority patent/TW202243252A/zh
Priority to CN202210286222.9A priority patent/CN114975262A/zh
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Priority to US18/182,959 priority patent/US11908745B2/en
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • GAA devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs).
  • GAA devices include a plurality of channel layers stacked together to form the transistor channels which are engaged by a gate structure.
  • the GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be aggressively scaled down while maintaining gate control and mitigating SCEs.
  • CMOS complementary metal-oxide-semiconductor
  • SCEs short-channel effects
  • FIG. 1 is a flow chart of an example method for fabricating an embodiment of a device of the present disclosure according to some embodiments of the present disclosure.
  • FIGS. 2 A and 3 A are top views of embodiments of devices of the present disclosure constructed at various fabrication stages according to some embodiments of the present disclosure.
  • FIGS. 2 B and 3 B are cross sectional views of embodiments of devices of the present disclosure along the line A-A′ in FIGS. 2 A and 3 A , respectively, according to some embodiments of the present disclosure.
  • FIGS. 2 C and 3 C are cross sectional views of an embodiment of a device of the present disclosure along the line B-B′ in FIGS. 2 A and 3 A , respectively, according to some embodiments of the present disclosure.
  • FIGS. 2 D, 3 D, 4 , 5 , 7 , 8 , 9 , 10 , 11 , and 12 are cross sectional views of an embodiment of a device of the present disclosure along the line C-C′ in FIGS. 2 A and 3 A , constructed at various fabrication stages according to some embodiments of the present disclosure.
  • FIGS. 6 A- 6 D are schematic views illustrating an example reaction implemented in an embodiment of the present disclosure.
  • FIG. 13 illustrates certain parameters of the process according to some embodiments of the present disclosure.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • the present disclosure is generally related to ICs and semiconductor devices and methods of forming the same. More particularly, the present disclosure is related to gate-all-around (GAA) devices capable of providing multiple threshold voltages (V t ).
  • GAA device includes any device that has its gate structure, or portions thereof, formed around all-sides of a channel region (e.g. surrounding a portion of a channel region). In some instances, a GAA device may also be referred to as a quad-gate device where the channel region has four sides and the gate structure is formed on all four sides.
  • the channel region of a GAA device may include one or more semiconductor layers, each of which may be in one of many different shapes, such as wire (or nanowire), sheet (or nanosheet), bar (or nano-bar), and/or other suitable shapes.
  • the channel region of a GAA device may have multiple horizontal semiconductor layers (such as nanowires, nanosheets, or nano-bars) (hereinafter collectively referred to as “nanochannels”) vertically spaced, making the GAA device a stacked horizontal GAA device.
  • the GAA devices presented herein may be a complementary metal-oxide-semiconductor (CMOS) GAA device, a p-type metal-oxide-semiconductor (pMOS) GAA device, or an n-type metal-oxide-semiconductor (nMOS) GAA device. Further, the GAA devices may have one or more channel regions associated with a single, contiguous gate structure, or multiple gate structures.
  • CMOS complementary metal-oxide-semiconductor
  • pMOS p-type metal-oxide-semiconductor
  • nMOS n-type metal-oxide-semiconductor
  • Multi-threshold voltage (or multi-V t ) devices have been implemented to optimize delays, reduce power consumption, and achieve other performance enhancements.
  • Multi-V t devices may be formed by using dipole engineering and/or patterned work function metal (WFM) layers. Such engineering and/or patterning have been shown to sometimes damage gate dielectric layers. In the context of GAA devices where gate dielectric layers are of extremely small thicknesses, tolerance to such damages may be low. In other words, such damages may lead to unacceptable degradation to the reliability and/or performance of the device. Moreover, in some instances, the topmost channel layer beneath the gate dielectric layer may also be damaged, further degrading the device functionality. Accordingly, the present disclosure provides methods that mitigate such damages thereby improving device reliability and functionality.
  • FIG. 1 is a flow chart of an example method for fabricating an embodiment of a GAA device of the present disclosure according to some embodiments of the present disclosure, where details for the block 108 is further illustrated.
  • FIGS. 2 A and 3 A are top views of an embodiment of a GAA device of the present disclosure constructed at various fabrication stages according to some embodiments of the present disclosure.
  • FIGS. 2 B, 3 B and 2 C, 3 C are cross sectional views of an embodiment of a GAA device of the present disclosure along the lines A-A′ and B-B′, of FIGS. 2 A and 3 A , respectively, according to some embodiments of the present disclosure.
  • FIGS. 2 D, 3 D, and 4 - 12 are cross sectional views of an embodiment of a GAA device of the present disclosure along the line C-C′ of FIGS. 2 A and 3 A at different fabrication stages, according to some embodiments of the present disclosure.
  • the GAA device 200 (or simply referred to as the device 200 ) includes a substrate 201 .
  • the substrate 201 contains a semiconductor material, such as bulk silicon (Si).
  • a semiconductor material such as bulk silicon (Si).
  • germanium (Ge) in a crystalline structure may also be included in the substrate 201 .
  • the substrate 201 may also include a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), or combinations thereof.
  • the substrate 201 may also include a semiconductor-on-insulator substrate, such as Si-on-insulator (SOI), SiGe-on-insulator (SGOI), Ge-on-insulator (GOI) substrates. Portions of the substrate 201 may be doped, such as the doped portions 205 .
  • the doped portions 205 may be doped with p-type dopants, such as boron (B) or boron fluoride (BF 3 ), or doped with n-type dopants, such as phosphorus (P) or arsenic (As).
  • the doped portions 205 may also be doped with combinations of p-type and n-type dopants.
  • the doped portions 205 may be formed directly on the substrate 201 , in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure.
  • a stack of semiconductor layers 220 and 222 are formed over the substrate 201 in an interleaving or alternating fashion, extending vertically (e.g. along the Z-direction) from the substrate 201 .
  • a semiconductor layer 222 is disposed over the substrate 201
  • a semiconductor layer 220 is disposed over the semiconductor layer 222
  • another semiconductor layer 222 is disposed over the semiconductor layer 220 , so on and so forth.
  • the semiconductor layers 220 may contain two (2) to ten (10) layers of semiconductor layers 220 , alternating with two (2) to ten (10) layers of semiconductor layers 222 in the stack.
  • the material compositions of the semiconductor layers 220 and 222 are configured such that they have an etching selectivity in a subsequent etching process.
  • the semiconductor layers 220 contain silicon germanium (SiGe), while the semiconductor layers 222 contain silicon (Si).
  • the semiconductor layers 222 contain SiGe, while the semiconductor layers 220 contain Si.
  • the semiconductor layers 220 each has a substantially uniform thickness, referred to as the thickness 308
  • the semiconductor layers 222 each has a substantially uniform thickness, referred to as the thickness 318 .
  • the thicknesses 308 and 318 may be chosen based on fabrication and/or device performance considerations for device 200 .
  • thickness 318 may be configured to define a desired distance (or gap) between adjacent channels of device 200 (e.g., between semiconductor layers 220 ); thickness 308 may be configured to achieve desired thickness of channels of device 200 . Both thickness 308 and thickness 318 may be configured to achieve desired performance of device 200 .
  • thickness 308 and thickness 318 are about 1 nm to about 10 nm. If the thickness 308 and thickness 318 are too small, such as less than about 1 nm, there may be insufficient dimension to form device features therein, or the formed device feature may be too narrow to have proper functionality. If the thickness 308 and thickness 318 are too large, such as greater than about 10 nm, the device features may unnecessarily occupy valuable chip spaces without substantial improvements to device performances.
  • the stack of semiconductor layers 220 and 222 are patterned into a plurality of fin structures, for example, into fin structures (or fins) 130 a and 130 b .
  • Each of the fins 130 a and 130 b includes a stack of the semiconductor layers 220 and 222 disposed in an alternating manner with respect to one another.
  • the fins 130 a and 130 b each extends lengthwise horizontally in a Y-direction and are separated from each other horizontally in an X-direction.
  • the fins may each have a lateral width along the X-direction, referred to as the width 350 .
  • the X-direction and the Y-direction are horizontal directions that are perpendicular to each other, and that the Z-direction is a vertical direction that is orthogonal (or normal) to a horizontal XY plane defined by the X-direction and the Y-direction.
  • the semiconductor substrate may have its top surface aligned in parallel to the XY plane.
  • the fins 130 a and 130 b may be patterned by any suitable method.
  • the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
  • double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
  • a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process.
  • the sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins.
  • the patterning may utilize multiple etching processes which may include a dry etching and/or wet etching.
  • the regions in which the fins are formed will be used to form active devices through subsequent processing, and are thus referred to as active regions.
  • fin 130 a is formed in the active region 202 a
  • the fin 130 b is formed in the active region 202 b . Both fins 130 a and 130 b are formed over the doped portions 205 .
  • the active regions 202 a and 202 b are configured to form transistors with different threshold voltages (V t ).
  • the active regions 202 a and 202 b are configured to form transistors of different types, such as n-type transistors and p-type transistors.
  • the fins 130 a and 130 b may each have a lateral width 350 along the X-direction.
  • the width 350 may be about 5 nm to about 100 nm, such as 6 nm to about 20 nm.
  • the device 200 includes isolation features 203 , which may be shallow trench isolation (STI) features.
  • the formation of the isolation features 203 includes etching trenches into the substrate 201 between the active regions and filling the trenches with one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof.
  • Any appropriate methods such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a plasma-enhanced CVD (PECVD) process, a plasma-enhanced ALD (PEALD) process, and/or combinations thereof may be used for depositing the isolation features 203 .
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • PECVD plasma-enhanced CVD
  • PEALD plasma-enhanced ALD
  • the isolation features 203 may have a multi-layer structure such as a thermal oxide liner layer over the substrate 201 and a filling layer (e.g., silicon nitride or silicon oxide) over the thermal oxide liner layer.
  • the isolation features 203 may be formed using any other traditional isolation technologies.
  • the fins 130 a and 130 b are located above the top surface of the isolation features 203 and the top surface of the doped portions 205 .
  • the device 200 further includes dummy gate structures 210 .
  • the dummy gate structures 210 are formed over a portion of each of the fins 130 a and 130 b , and over the isolation features 203 in between the fins 130 a and 130 b .
  • the dummy gate structures 210 may be configured to extend lengthwise in parallel to each other, for example, each along the X-direction.
  • the dummy gate structures each wraps around the top surface and side surfaces of each of the fins.
  • the dummy gate structures 210 may include polysilicon.
  • the dummy gate structures 210 also include one or more mask layers, which are used to pattern the dummy gate electrode layers.
  • the dummy gate structures 210 may undergo a gate replacement process through subsequent processing to form metal gates, such as a high-k metal gate, as discussed in greater detail below.
  • the dummy gate structures 210 may be formed by a procedure including deposition, lithography patterning, and etching processes.
  • the deposition processes may include CVD, ALD, PVD, other suitable methods, and/or combinations thereof.
  • the device 200 includes gate spacers 240 on the sidewalls of the dummy gate structures 210 .
  • the gate spacers 240 may include silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon doped oxide, nitrogen doped oxide, porous oxide, or combinations thereof.
  • the gate spacers 240 may include a single layer or a multi-layer structure. In some embodiments, the gate spacers 240 may have thicknesses in the range of a few nanometers (nm).
  • the gate spacers 240 may be formed by depositing a spacer layer (containing the dielectric material) over the dummy gate structures 210 , followed by an anisotropic etching process to remove portions of the spacer layer from the top surfaces of the dummy gate structures 210 . After the etching process, portions of the spacer layer on the sidewall surfaces of the dummy gate structures 210 substantially remain and become the gate spacers 240 .
  • the anisotropic etching process is a dry (e.g. plasma) etching process.
  • the formation of the gate spacers 240 may also involve chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable methods.
  • the gate spacers 240 are formed over the top layer of the semiconductor layers 220 and 222 . Accordingly, the gate spacers 240 may also be interchangeably referred to as the top spacers 240 . In some examples, one or more material layers (not shown) may also be formed between the dummy gate structures 210 and the corresponding top spacers. The one or more material layers may include an interfacial layer and/or a high-k dielectric layer.
  • the device further includes inner spacers 250 between end portions of vertically adjacent semiconductor layers 220 .
  • the inner spacers 250 may include a dielectric material, for example, a dielectric material selected from SiO 2 , SiON, SiOC, SiOCN, or combinations thereof.
  • portions of the fins 130 a , 130 b not covered by the dummy gate structures 210 or the gate spacers 240 are recessed to form source/drain trenches.
  • the semiconductor layers 222 are laterally recessed to form gaps between end portions of the vertically adjacent semiconductor layers 220 .
  • the dielectric material may then be deposited into the gaps, and etched back to remove any excess materials in the source/drain trenches, thereby forming the inner spacers 250 .
  • the device 200 further includes epitaxial source/drain features 208 formed in the source/drain trenches and on both ends of the semiconductor layers 220 .
  • a source/drain feature is a source electrode
  • the other source/drain feature is a drain electrode.
  • Each of the semiconductor layers 220 connects two epitaxial source/drain features 208 .
  • a portion of the semiconductor layers 220 may constitute a portion of a transistor channel. Multiple processes including etching and growth processes may be employed to grow the epitaxial source/drain features 208 .
  • the epitaxial source/drain features 208 have top surfaces that extend higher than the top surface of the topmost semiconductor layer 220 .
  • the epitaxial source/drain features 208 may alternatively have top surfaces that are about even with the top surface of the topmost semiconductor layer 220 .
  • the epitaxial source/drain features 208 may merge together, for example, along the X-direction, to provide a larger lateral width than an individual epitaxial feature.
  • the epitaxial source/drain features 208 are not merged.
  • the epitaxial source/drain features 208 may include any suitable semiconductor materials.
  • the epitaxial source/drain features 208 is an n-type GAA device, and therefore may include Si, SiC, or combinations thereof.
  • the epitaxial source/drain features 208 in a p-type GAA device may include Si, SiGe, Ge, SiGeC, or combinations thereof.
  • the source/drain features 208 may be doped in-situ or ex-situ.
  • the epitaxially grown Si source/drain features may be doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features; and the epitaxially grown SiGe source/drain features may be doped with boron.
  • One or more annealing processes may be performed to activate the dopants in the epitaxial source/drain features 208 .
  • the annealing processes may comprise rapid thermal annealing (RTA) and/or laser annealing processes.
  • the device 200 also includes an interlayer dielectric (ILD) layer 214 formed over the epitaxial source/drain features 208 .
  • the ILD layer 214 may also be formed in between the adjacent gates 210 along the Y-direction, and in between the source/drain features 208 along the X-direction.
  • the ILD layer 214 may include a dielectric material, such as a high-k material, a low-k material, or an extreme low-k material.
  • the ILD layer 214 may include SiO 2 , SiOC, SiON, or combinations thereof.
  • the ILD layer 214 may include a single layer or multiple layers, and may be formed by a suitable technique, such as CVD, ALD, and/or spin-on techniques.
  • a CMP process may be performed to remove excessive ILD layer 214 and planarize the top surface of the ILD layer 214 .
  • the ILD layer 214 provides electrical isolation between the various components of the device 200 .
  • the dummy gate structures 210 are selectively removed through any suitable lithography and etching processes, thereby forming the gate trenches 153 .
  • the lithography process may include forming a photoresist layer (resist), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element, which exposes a region including the dummy gate structures 210 . Then, the dummy gate structures 210 are selectively etched through the masking element.
  • the top spacers 240 may be used as the masking element or a part thereof.
  • the dummy gate structures 210 may include polysilicon, the top spacers 240 and the inner spacers 250 may include dielectric materials, and the semiconductor layers 220 includes a semiconductor material. Therefore, an etch selectivity may be achieved by selecting appropriate etching chemicals, such that the dummy gate structures 210 may be removed without substantially affecting the other components of the device 100 . Subsequently, the remaining portions of the semiconductor layers 222 are selectively removed without substantially affecting the semiconductor layers 220 . As a result, openings 157 are formed between the vertically adjacent semiconductor layers 220 . The openings 157 and the gate trenches 153 collectively expose each of the semiconductor layers 220 circumferentially around the Y-direction.
  • the portion of the doped regions 205 beneath the semiconductor layers 220 are also exposed in the openings 157 . Because the etching operations do not substantially affect the semiconductor layers 220 , the semiconductor layers 220 maintain the thickness 308 , and the openings 157 may have a height corresponding to the thickness 318 (or interchangeably referred to as the height 318 ).
  • FIGS. 4 - 11 illustrate an example method for forming a gate structure in place of the dummy gate structures 210 .
  • a dielectric layer 223 is formed over the surfaces of semiconductor layers 220 exposed in the openings 157 and the gate trenches 153 , as well as the substrate 201 exposed in the opening 157 .
  • This dielectric layer 223 may be an interfacial layer.
  • the dielectric layer 223 includes an oxide, such as a silicon dioxide. Any suitable methods may be used to form the dielectric layer 223 , such as ALD, CVD, or other deposition methods.
  • the dielectric layer 223 may also be formed by an oxidation process, such as thermal oxidation or chemical oxidation.
  • the interfacial layer 223 improves the adhesion between the semiconductor substrate and the subsequently formed gate dielectric layers.
  • the dielectric layer 223 has a substantially uniform thickness around each semiconductor layers 220 and over the semiconductor substrate 201 .
  • the bottommost semiconductor layer 220 e.g.
  • the semiconductor layer closest to the semiconductor substrate 201 is also referred to as the semiconductor layers 220 A; the semiconductor layer 220 immediately above the semiconductor layer 220 A is referred to as the semiconductor layer 220 B; and the topmost semiconductor layer 220 is referred to as the semiconductor layer 220 C.
  • the portion of the dielectric layer 223 on the top surface of the semiconductor layer 220 A has an average thickness 350 A; the portion of the dielectric layer 223 on the bottom surface of the semiconductor layer 220 A has an average thickness 352 A.
  • the average thickness 350 A is substantially similar to the average thickness 352 A.
  • the portion of dielectric layer 223 on the top surface of the semiconductor layer 220 B has an average thickness 350 B; the portion of the dielectric layer 223 on the bottom surface of the semiconductor layer 220 B has an average thickness 352 B.
  • the average thickness 350 B is substantially similar to the average thickness 352 B.
  • the portion of dielectric layer 223 on the top surface of the semiconductor layer 220 C has an average thickness 350 C; the portion of the dielectric layer 223 on the bottom surface of the semiconductor layer 220 C has an average thickness 352 C.
  • the average thickness 350 C is substantially similar to the average thickness 352 C.
  • the dielectric layer 223 over the substrate 201 has an average thickness 350 S.
  • the average thickness 350 A, 350 B, 350 C, and 350 S are substantially similar to each other. Accordingly, the thicknesses 352 A, 352 B, and 352 C are also substantially similar to each other.
  • gate dielectric layer 228 is formed around the dielectric layers 223 .
  • the gate dielectric layers 228 at least partially fill the trenches 153 and the openings 157 .
  • the gate dielectric layers 228 may be formed around the dielectric layers 223 over each of the semiconductor layers 220 , such that they wrap around the semiconductor layers 220 in 360 degrees. Additionally, the gate dielectric layers 228 also directly contact vertical sidewalls of the inner spacers 250 and of the top spacers 240 .
  • the gate dielectric layer 228 may be a high-k dielectric layer.
  • the gate dielectric layers 228 may contain a dielectric material having a dielectric constant greater than a dielectric constant of SiO 2 , which is approximately 3.9.
  • the gate dielectric layers 228 may include hafnium oxide (HfO 2 ), which has a dielectric constant in a range from about 18 to about 40.
  • the gate dielectric layers 228 may include ZrO 2 , Y 2 O 3 , La 2 O 5 , Gd 2 O 5 , TiO 2 , Ta 2 O 5 , HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, SrTiO, or combinations thereof.
  • the formation of the gate dielectric layers 228 may be by any suitable processes, such as CVD, PVD, ALD, or combinations thereof.
  • the gate dielectric layers 228 may be formed conformally on the device 100 .
  • portions of the dielectric layers 228 on a top surface of a semiconductor layer 220 may have the same thickness as the portions of the dielectric layers 228 on a bottom surface of the semiconductor layer 220 .
  • portions of the dielectric layers 228 surrounding a topmost semiconductor layer 220 may have the same thickness as the portions of the dielectric layer 228 surrounding the bottommost semiconductor layer 220 .
  • all portions of the gate dielectric layer 228 may be similarly thin.
  • Such thin gate dielectric layers 228 may be particularly prone to damages in dry and wet etching operations.
  • the dry etching, the wet etching, or combinations thereof may cause losses to the gate dielectric layers 228 . Accordingly, some of those originally thin portions of the gate dielectric layer 228 on top surfaces of the higher semiconductor layers 220 may sustain damages unacceptable to maintain satisfactory device performances.
  • asymmetric (or non-conformal) dielectric layers 228 are provided, such that the portions on top surfaces of higher semiconductor layers 220 have greater thicknesses, which better sustains any potential damages; while portions on bottom surfaces of lower semiconductor layers 220 have smaller thicknesses which allows for further scaling down of the device.
  • the gate dielectric layer 228 is not conformal.
  • the design of the gate dielectric layer may be dependent upon the type of applications for the device 200 .
  • the device 200 may be a standard device; while in some other embodiments, the device 200 may be an ultra-low threshold voltage device. Different types of devices may require different gate dielectric layer thicknesses.
  • the device 200 is an ultra-low threshold voltage device.
  • the portion of gate dielectric layer 228 on the dielectric layer 223 (over the top surface of the semiconductor layer 220 B) has an average thickness 360 B; the portion of the gate dielectric layer 228 on the dielectric layer 223 (over the bottom surface of the semiconductor layer 220 B) has an average thickness 362 B.
  • the average thickness 360 B is greater than the average thickness 362 B.
  • a ratio of the average thickness 360 B to the average thickness 362 B may be about 1:0.95 to about 1:0.99, for example, about 1:0.96 to about 1:0.98.
  • a difference between the average thickness 360 B and the average thickness 362 B may be about 0.1 ⁇ to about 0.7 ⁇ , such as about 0.3 ⁇ to about 0.5 ⁇ .
  • the portion of gate dielectric layer 228 on the dielectric layer 223 (over the top surface of the semiconductor layer 220 C) has an average thickness 360 C; the portion of the gate dielectric layer 228 on the dielectric layer 223 (over the bottom surface of the semiconductor layer 220 C) has an average thickness 362 C.
  • the average thickness 360 C is greater than the average thickness 362 C.
  • a ratio of the average thickness 360 C to the average thickness 362 C may be about 1:0.96 to about 1:0.99, for example, about 1:0.97 to about 1:0.98.
  • a difference between the average thickness 360 C and the average thickness 362 C may be about 0.2 ⁇ to about 0.8 ⁇ , such as about 0.4 ⁇ to about 0.6 ⁇ . If the difference is too small, the benefit associated with the asymmetric design (e.g. mitigate the effect of etching on the integrity of the gate dielectric layer 228 ) may be lost or partially lost; if the difference is too large, the benefit of the extra thickness (e.g. on top of the semiconductor layers 220 ) may not justify their chip footprint.
  • the portion of gate dielectric layer 228 on the dielectric layer 223 over the top surface of the semiconductor substrate 201 has an average thickness 360 S.
  • the average thickness 360 A is less than the average thickness 360 B; and the average thickness 360 B is less than the average thickness 360 C.
  • a difference ⁇ (B ⁇ A) between the 360 B and the average thickness 360 A is about 0.2 ⁇ to about 0.8 ⁇ , such as about 0.4 ⁇ to about 0.6 ⁇ .
  • a difference ⁇ (C ⁇ B) between the 360 C and the average thickness 360 B is about 0.2 ⁇ to about 0.8 ⁇ , such as about 0.4 ⁇ to about 0.6 ⁇ .
  • the average thickness 362 B is less than the average thickness 362 C.
  • a difference ⁇ ′(C ⁇ B) between the 362 C and the average thickness 362 B is about 0.2 ⁇ to about 0.8 ⁇ , such as about 0.4 ⁇ to about 0.6 ⁇ . If the difference is too small, the benefit associated with the asymmetric design (e.g. mitigate the effect of etching on the integrity of the gate dielectric layer 228 ) may be lost or partially lost; if the difference is too large, the benefit of the extra thickness (e.g. around higher semiconductor layers 220 ) may not justify their chip footprint.
  • the device 200 is a standard nanosheet device.
  • a ratio of the average thickness of the portion of the gate dielectric layer 228 above a semiconductor layer 220 to the average thickness of the portion below the semiconductor layer 220 may be about 0.80 to about 0.99.
  • the portion of the gate dielectric layer 228 on the top surface of the dielectric layer 223 (over the semiconductor layer 220 A) has an average thickness 360 A; the portion of the gate dielectric layer 228 on the bottom surface of the dielectric layer 223 (below the semiconductor layer 220 A) has an average thickness 362 A.
  • the average thickness 360 A is greater than the average thickness 362 A.
  • a ratio of the average thickness 360 A to the average thickness 362 A may be about 1:0.96 to about 1:0.99, for example, about 1:0.97 to about 1:0.99.
  • a difference between the average thickness 360 A and the average thickness 362 A may be about 0.1 ⁇ to about 0.5 ⁇ , for example, about 0.2 ⁇ to about 0.4 ⁇ .
  • the portion of gate dielectric layer 228 on the dielectric layer 223 (over the top surface of the semiconductor layer 220 C) has an average thickness 360 C; the portion of the gate dielectric layer 228 on the dielectric layer 223 (over the bottom surface of the semiconductor layer 220 C) has an average thickness 362 C.
  • the average thickness 360 C is greater than the average thickness 362 C.
  • a ratio of the average thickness 360 C to the average thickness 362 C may be about 1:0.82 to about 1:0.98, for example, about 1:0.89 to about 1:0.91.
  • a difference between the average thickness 360 C and the average thickness 362 C may be about 1.2 ⁇ to about 2.2 ⁇ , such as about 1.5 ⁇ to about 1.9 ⁇ . If the difference is too small, the benefit associated with the asymmetric design (e.g. mitigate the effect of etching on the integrity of the gate dielectric layer 228 ) may be lost or partially lost; if the difference is too large, the benefit of the extra thickness (e.g. on top of the semiconductor layers 220 ) may not justify their chip footprint.
  • the portion of gate dielectric layer 228 on the dielectric layer 223 over the top surface of the semiconductor substrate 201 has an average thickness 360 S.
  • the average thickness 360 S is less than the average thickness 360 A.
  • a difference ⁇ (A ⁇ S) between the 360 S and the average thickness 360 A is about 0.5 ⁇ to about 1.1 ⁇ , such as about 0.7 ⁇ to about 0.9 ⁇ .
  • the average thickness 360 B is less than the average thickness 360 C.
  • a difference ⁇ (C ⁇ B) between the 360 C and the average thickness 360 B is about 1 ⁇ to about 2.5 ⁇ , such as about 1.6 ⁇ to about 2.0 ⁇ .
  • the thicknesses 362 A is less than the average thickness 362 B; and the average thickness 362 B is less than the average thickness 362 C.
  • a difference ⁇ ′(C ⁇ B) between the 362 C and the average thickness 362 B and the difference ⁇ ′(B ⁇ A) between the 362 B and the average thickness 362 A is about 0.1 ⁇ to about 0.5 ⁇ , such as about 0.1 ⁇ to about 0.3 ⁇ . If the difference is too small, the benefit associated with the asymmetric design (e.g. mitigate the effect of etching on the integrity of the gate dielectric layer 228 ) may be lost or partially lost; if the difference is too large, the benefit of the extra thickness (e.g. around higher semiconductor layers 220 ) may not justify their chip footprint.
  • portions of the gate dielectric layers 228 on sidewall surfaces of the semiconductor layers 220 similarly have non-uniform thicknesses.
  • a top section i.e. the section further away from the substrate
  • a bottom section i.e. the section closer to the substrate.
  • the asymmetric (or non-conformal) gate dielectric layers 228 may be formed by any suitable methods.
  • FIGS. 6 A- 6 D illustrate expanded cross sections views of a portion of one of the semiconductor layers 220 along with the dielectric layer 223 formed thereupon.
  • FIGS. 6 A- 6 D illustrate the layer 223 being vertically above the semiconductor layer 220
  • the processes described in FIGS. 6 A- 6 D occur not only adjacent the top surface of the semiconductor layers 220 , but also similarly adjacent the bottom surfaces and sidewall surfaces of the semiconductor layers 220 .
  • similar processes occur on the exposed top, bottom, and sidewall surfaces of the dielectric layers 223 wrapping around the semiconductor layers 220 .
  • reactions on these different surfaces have different rates and/or efficiencies, which leads to the different thicknesses of the gate dielectric layers 228 in different areas.
  • the dielectric layer 223 includes an oxide material, such as silicon oxide.
  • the dielectric layer 223 may include hydroxy (—OH) functional groups on the exposed surfaces (which may be a top surface, a bottom surface, or sidewall surfaces of the dielectric layer 223 ).
  • the hydroxy groups may have their oxygen atoms attached to a silicon atom of the dielectric layer 223 and may have the hydrogen atoms pointing away from the respective silicon atom and therefore pointing away from the semiconductor layers 220 .
  • these hydroxy groups may function as the anchoring points for subsequently formed gate dielectric layer 228 , such that the adhesion between the gate dielectric layer 228 and the dielectric layer 223 is improved. Referring to block 1080 of FIG.
  • a precursor to the gate dielectric layers 228 (“precursor A”) is introduced in the process 402 into the processing chamber.
  • the precursor A may include a metal atom and ligand atoms and may be denoted as ML n .
  • the metal atom is a tetravalent metal and is chemically bonded with four ligands (L).
  • the precursor A may be zirconium chloride (ZrCl 4 ), hafnium chloride (HfCl 4 ), tetrakis(ethylmethylamido)hafnium (TEMAHf), silicon chloride (SiCl 4 ), other zirconium halides, other hafnium halides, other silicon halides, other amino-hafnium complexes, other metal halides, other amine complexes of transition metals, or combinations thereof.
  • the processing environment is configured to allow for, or to induce, a reaction between the precursor A and the dielectric layer 223 .
  • the metal atom of precursor A may interact with the hydroxy groups on the exposed surfaces of the dielectric layer 223 .
  • the metal atom and the oxygen atom of the hydroxy group may interact with each other to form chemical bonds (such as a covalent chemical bond) between them.
  • M—O chemical bonds are formed on the surfaces of the dielectric layers 223 .
  • the ligand atom forms another chemical bond with the hydrogen atom of the hydroxy group, such as a H—L bond. Accordingly, the L ligands are detached from the surfaces of the dielectric layer 223 .
  • the process 402 is configured to be a pulsed process with a pulse duration of t 1 . In some embodiments, the pulse time is about 0.75 s to about 3 s. If the pulse time is too short, there may be insufficient precursor available to react with; if the pulse time is too long, the cost may outweigh any benefit achieved.
  • process 404 purges excess amount of the precursor A along with byproduct H-L from the processing chamber.
  • the process 404 is configured to be a pulsed process with a pulse duration of t 2 .
  • the pulse time is about 0.75 s to about 10 s.
  • a ratio of the pulse duration t 2 for the process 404 to the pulse duration t 1 for the process 402 is about 0.2:1 to about 1.6:1.
  • a ratio of the pulse duration t 2 for the process 404 to the pulse duration t 1 for the process 402 is about 0.7:1 to about 1.1:1.
  • the precursor A may be desorbed from the surface such that insufficient precursor A remain for subsequent reactions. If the pulse time t 2 is too small, such as less than about 0.75 s, or if the ratio of the pulse duration t 2 to the pulse duration t 1 is too small, impurities may remain at the conclusion of the process. Accordingly, at the conclusion of the process 404 , the dielectric layers 223 are modified to include metal atoms M.
  • the surfaces of the dielectric layers 223 may include metal atoms attached to the oxygen atoms of the dielectric layers 223 , along with dangling ligands L pointing away from the surface of the dielectric layers 223 .
  • the metal atoms and the ligands L attached to the dielectric layers 223 become part of the gate dielectric layers 228 .
  • majority (such as greater than about 80%) of the surface of the dielectric layers 223 is covered by the precursor A (or the M-L groups).
  • some hydroxy groups remain on the surfaces. Meanwhile, byproducts H-L are substantially removed during the process 404 .
  • precursor B another precursor to the gate dielectric layers 228 (“precursor B”) is introduced in the process 406 into the processing chamber.
  • the processing environment is configured to allow for, or to induce a reaction, between the M-L functional groups on the surfaces of the dielectric layers 223 (or as part of the initial layer of the dielectric layer 228 ) and the precursor B.
  • the precursor B may include trimethylamine (TMA), water (H 2 O), oxygen (O 2 ), ozone (O 3 ), other suitable precursors, or combinations thereof.
  • the reaction forms additional metal-oxygen (M-)) chemical bonds (e.g., in addition to the M-O chemical bonds formed between the metal atoms and the oxygen atoms of the dielectric layer 223 ).
  • the reaction forms metal-nitrogen (M-N) chemical bonds.
  • the interaction may be a metathesis reaction, where the precursor B replaces the ligand L to bond with the metal atom M.
  • the interaction may be a hydrolysis reaction or an aminolysis reaction.
  • the interaction may be an oxidation reaction.
  • the interaction may include one or more of the metathesis reaction, the hydrolysis reaction, the aminolysis reaction, the oxidation reaction.
  • the metal atom M was attached to multiple L ligands.
  • the process 406 causes the M atom to be attached to multiple O or N atoms.
  • the formed product becomes a portion of the gate dielectric layer 228 .
  • byproducts including the ligand L detach from the surfaces.
  • the M-O or M-N bonds are stronger than the M-L bonds, which provides the driving force for the reaction to proceed.
  • the reactions are equilibrium in nature. In such embodiments, the presence of accumulating byproducts, such as those incorporating the L ligands, may impede the completion of the reaction. Therefore, as the byproducts buildup, the reaction rate may decrease.
  • the process 406 is configured to be a pulsed process with a pulse duration of t 3 .
  • the pulse time t 3 is about 0.3 s to about 15 s.
  • FIG. 13 illustrates some parameters implemented herein. As seen in FIG. 13 , a ratio of the pulse time t 3 to the pulse time t 1 according to embodiments of the present disclosure may be about 0.65 to about 1.6.
  • the pulse time duration t 3 is too long, such as greater than about 15 s, or if the ratio of the pulse time t 3 to the pulse time t 1 is too large, such as greater than about 1.6, oxidation (or re-oxidation) to the substrate may occur and cause device performance degradations. If the pulse time duration t 3 is too short, such as less than about 0.3 s, or if the ratio of the pulse time t 3 to the pulse time t 1 is too small, such as less than about 0.65, impurities may remain following the reaction. In some other approaches not implementing embodiments of methods of the present disclosure, the ratio may be about 0.2 to about 0.6.
  • the thicknesses of the gate dielectric layers 228 above and below the semiconductor layers 220 may be much more similar to one another. Accordingly, the benefits of the asymmetric configuration of the gate dielectric layer 228 , with respect to the maintaining the integrities of the gate dielectric layer 228 , may be lost. If the ratio is too large, such as greater than about 1.6:1, any benefit achieved may be offset by the greater processing cost. It has been observed by implementing the ratios described here, the portion of the gate dielectric layer 228 above the semiconductor layer 220 C may have a thickness that is greater than the portions of the gate dielectric layer 228 above the lower semiconductor layers 220 B or 220 A by about 1 ⁇ to about 4 ⁇ , such as about 2 ⁇ to about 3 ⁇ .
  • the process 408 is configured to be a pulsed process with a pulse duration of t 4 .
  • the pulse time t 4 is about 0.75 s to about 10 s.
  • a ratio of the pulse duration t 4 for the process 408 to the pulse duration t 1 for the process 402 is about 0.2:1 to about 1:1.
  • a ratio of the pulse duration t 4 for the process 408 to the pulse duration t 1 for the process 402 is about 0.5:1 to about 0.8:1. If the pulse time t 4 is too long, such as greater than about 10 s, or if the ratio of the pulse duration t 4 to the pulse duration t 1 is too large, the precursor A or B may be desorbed such that insufficient reactants are available to form the gate dielectric layer 228 . If the pulse time t 4 is too short, such as greater than about 0.75 s, or if the ratio of the pulse duration t 4 to the pulse duration t 1 is too small, impurities may remain at the conclusion of the reaction.
  • the portion of the gate dielectric layer 228 above the semiconductor layer 220 C may have a thickness that is greater than the portions of the gate dielectric layer 228 above the lower semiconductor layers 220 B or 220 A by about 1 ⁇ to about 5 ⁇ , such as about 2 ⁇ to about 4 ⁇ .
  • the ratio may be greater than about 1:1, such as between about 1.05:1 to about 1.6:1.
  • the gate dielectric layers 228 may have substantially similar thicknesses both above and below the semiconductor layers 220 .
  • one layer of gate dielectric material that forms a portion of the gate dielectric layer 228 is formed.
  • the gate dielectric material similar to the dielectric layer 223 , also includes hydroxy groups.
  • the gate dielectric material may serve the function of the dielectric layer 223 in a subsequent deposition and/or growth cycle.
  • the processes 402 - 408 described above with respect to the FIGS. 6 A- 6 D may be repeated.
  • a second layer of the gate dielectric material may be formed over and wrapping the first layer.
  • the process 402 of the second cycle introduces the precursor A such that the precursor A diffuses into areas adjacent the gate dielectric layer 228 , and interacts with the hydroxy groups thereon to form a second layer of the gate dielectric material.
  • Subsequent processes 404 - 408 are substantially similar to those already described above. Each cycle will produce a layer (or sublayer) of gate dielectric material which has a greater thickness on top of the semiconductor layers 220 than on bottom of the semiconductor layers 220 . When the desired thickness profile is reached, the formation of the gate dielectric layer 228 is completed, where the gate dielectric layer 228 has the desired asymmetric profile.
  • capping layer 230 is formed over and wrapping the gate dielectric layers 228 around each of the semiconductor layers 220 .
  • the capping layer 230 is configured to have a substantially uniform thickness.
  • a thickness of the capping layer 230 throughout its profile (such as on top surface, bottom surface, and on sidewall surfaces of the gate dielectric layers 228 ) is average thickness 364 .
  • the average thickness 364 is about 1 nm to about 3 nm.
  • Exemplary materials for the capping layer 230 include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), and/or tantalum silicon nitride (TaSiN).
  • Any suitable depositions may be used, such as ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, other deposition process, or combinations thereof.
  • the processing parameters may be tuned to achieve the capping layer 230 with a desired thickness.
  • a protecting layer 260 such as a bottom anti-reflective coating (BARC) layer is formed over the substrate 201 .
  • the protecting layer 260 may provide for absorption of radiation incident to the substrate during photolithography processes, including exposure of an overlying photoresist layer.
  • the protecting layer 260 formed on the substrate may include one or more sublayers. In some embodiments, the protecting layer 260 may be about 60 nanometers (nm) to about 80 nm in thickness.
  • the protecting layer 260 may be formed by one or more spin-on deposition processes that may be followed by one or more bake processes.
  • the protecting layer 260 is baked at an elevated temperature, for example, at a temperature of about 200° C. to about 230° C.
  • the baking operation removes solvent molecules within the BARC and causes densification therein.
  • a material layer 262 such as a low-temperature oxide layer is formed over the protecting layer 260 .
  • a patterned photoresist layer 264 is formed on the material layer 262 .
  • the photoresist layer 264 are patterned to define device regions in which the transistors have the same threshold voltages.
  • the patterned photoresist layer 264 is formed to cover the device region 202 b while leaving the device region 202 a . Accordingly, transistors in the device region 202 a may have a first threshold voltage, and the device region 202 b may have a second threshold voltage that is different from the first threshold voltage. This enables the fabrication of multi-V t devices.
  • the photoresist layer 264 may be positive-tone or negative-tone resist.
  • the photoresist is chemical amplified photoresist (CAR).
  • the photoresist may include a polymer, a photoacid generator (PAG), which provides the solubility change to the developer, a solvent, and/or other suitable compositions.
  • the photoresist may be formed by processes such as coating (e.g., spin-on coating) and soft baking.
  • a dry etching operation removes the portion of material layer 262 and the protecting layer 260 in the region 202 a not covered by the photoresist layer 264 .
  • the dry etching operation may implement any suitable dry etching methods.
  • the material layer 262 and the protecting layer 260 are etched with a reactive ion etch (RIE) process, using the patterned photoresist layer 264 as the etch mask.
  • RIE reactive ion etch
  • the dry etch process may be implemented using an etchant gas that includes a fluorine-containing etchant gas (e.g., NF 3 , CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), an oxygen-containing gas (e.g., O 2 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , SiCl 4 , and/or BCl 3 ), a nitrogen-containing gas (e.g., N 2 ), a bromine-containing gas (e.g., HBr and/or CHBr 3 ), an iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof.
  • a fluorine-containing etchant gas e.g., NF 3 , CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6
  • an oxygen-containing gas e.
  • the dry etch process removes the protecting layer 260 from above, between, and on sidewall surfaces of the semiconductor layers 220 in the device regions 202 a , thereby exposing the surfaces of the capping layers 230 .
  • the bombardment of the dry etching operation causes intermixing between the capping layer 230 and the gate dielectric layer 228 . Meanwhile, the material layer 262 and the protecting layer 260 in the device regions 202 b are substantially preserved. Following the dry etching process, the patterned photoresist 264 is removed.
  • the wet etching operation may be an over-etching process.
  • the wet etching operation may implement an over-etching process using tris-borate-ethylene diamine tetraacetic acid (TBE) as the etching reactant at a concentration of about 20% to about 30%.
  • TBE tris-borate-ethylene diamine tetraacetic acid
  • the wet etching operation is configured to substantially remove all the material layer 262 without substantially affecting the protecting layer 260 in the device region 202 b or the capping layer 230 in the device region 202 a .
  • the capping layer 230 around the semiconductor layers 220 in the device region 202 a are vertically spaced away from each other.
  • the capping layer 230 is selectively removed in the device region 202 a .
  • the capping layer 230 is removed in a wet etching operation.
  • the wet etching operation is configured to remove only the capping layer 230 without significantly affecting the gate dielectric layer 228 in the device region.
  • parameters of the wet etching operation may be selected to achieve an etching rate of the capping layer 230 that is about 10 to 20 times higher than the etching rate of the gate dielectric layer 228 in the same operation.
  • the wet etching operation implements a hydrogen fluoride (HF) etching solution at a concentration of about 1% to about 10%.
  • HF hydrogen fluoride
  • the etching selectivity may not be perfect, particularly because the intermixing between the capping layer 230 and the gate dielectric layer 228 . Therefore, the gate dielectric layer 228 may still be etched, albeit to a significantly smaller extent than the capping layer 230 . Given the very small initial thickness of the gate dielectric layer 228 in advanced technology nodes, such small amount of damage still asserts significant effects. In approaches not implementing methods of the present disclosure, such defects may cause degradations to the device performances, or even device failures.
  • the present disclosure recognizes that different portions of the gate dielectric layers 228 are subject to different amount of damage during the etching operations.
  • the etching reactant approaches the gate dielectric layers 228 from above the device 200 .
  • the etching reactant diffuses from areas around sidewalls of the semiconductor layers 220 and above the isolation structure 203 into the spacing 157 between vertically adjacent semiconductor layers.
  • the gate dielectric layer 228 wrapping around the top semiconductor layer 220 are subject to more etching than the gate dielectric layer 228 over that wrapping around the lower semiconductor layers 220 .
  • those wrapping around the lower semiconductor layers 220 may be subject to more etching than those covering the semiconductor substrate 220 S.
  • the gate dielectric layers 228 on the top surface of each of the semiconductor layers 220 are subject to more etching as compared to the portion of the gate dielectric layer 228 on the bottom surface of the same semiconductor layer 220 .
  • this particular portion of the gate dielectric layer 228 may be able to maintain substantial amount of its performance characteristics given the increased thickness in this particular region, the performance gains therefore can be received.
  • the protecting layer 260 in the device region 202 b is removed, such as by a suitable ashing process.
  • the ashing process may include an oxygen-containing plasma.
  • the capping layer 230 becomes exposed in the device region 202 b .
  • the gate dielectric layer 228 is exposed in the device region 202 a and covered under the capping layer 230 in the device region 202 b .
  • work function metals may be formed selectively in the device region 202 a , on and wrapping the gate dielectric layer 228 .
  • the WFM layer 248 may include any suitable materials, such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), or combinations thereof.
  • TiN titanium nitride
  • TaN tantalum nitride
  • TiAl titanium aluminum nitride
  • TaAlN titanium aluminum nitride
  • TaAlN tantalum aluminide
  • TaAlN tantalum aluminum nitride
  • TaAlC tantalum aluminum carbide
  • TaCN tantalum carbonitride
  • the WFM layer 248 may be formed using any suitable methods, such as ALD, CVD, PVD, other suitable methods, or combinations thereof.
  • the WFM layer 248 is formed on and directly contacting the gate dielectric layer 228 in the device region 202 a .
  • the asymmetric profile of the gate dielectric layer 228 of this present disclosure ensures the gate dielectric layer 228 interfaces between the WFM layer 248 and the interfacial layer 223 throughout without defects.
  • the gate dielectric layer 228 may have been severely damaged during the dry and/or etching operations, such that the WFM layer 248 may directly contact the dielectric layer 223 or in some instances directly contact the semiconductor layers 220 in certain areas, leading to performance degradations or failures.
  • the WFM layer 248 is formed over the capping layer 230 in the device region 202 b , such that the WFM layer 248 is spaced apart from the gate dielectric layer 228 .
  • the WFM layer 248 and the capping layer 230 may be removed to expose the underlying gate dielectric layer 228 , when another WFM layer is formed thereon to form a transistor having a different threshold voltage.
  • the asymmetric profile of the gate dielectric layer 228 in the device region 202 b , also ensures its integrity, similar to that in the device region 202 a.
  • the same process may be implemented to form device having different types of transistors, such as n-type transistors adjacent to p-type transistors.
  • the device regions 202 a and 202 b may each be a device region with a different dopant type.
  • the processes may be otherwise similar to those described above with respect to the FIGS. 1 - 12 .
  • the process described above with respect to FIGS. 8 - 12 are repeated to fabricate devices having more than two threshold voltages (for each of the n-type and/or p-type devices).
  • method 100 may proceed to form additional layers and features to complete the fabrication of the device 200 .
  • additional layers and features may be formed after the WFM layers for all device regions are properly formed.
  • bulk metal layers may be deposited to complete the formation of the gate electrode.
  • the gate dielectric layers 228 and the gate electrode collectively form the gate structure, such as high-k gate structures. Additional features may be formed for the device 200 , some of the described features may be eliminated or replaced in some embodiments without departing from the spirit of the disclosure. Similarly, steps may be added before, between, or after steps of those described above; and some of the steps may be modified or eliminated without departing from the spirit of the disclosure.
  • the present disclosure is directed to a semiconductor device.
  • the semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer.
  • Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer.
  • the top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.
  • the semiconductor device further includes an interfacial layer interposing between each portion of the gate dielectric layer and the respective semiconductor layer.
  • the interfacial layer is a conformal layer.
  • an intermediate layer interposes between the capping layer and the gate dielectric layer.
  • the intermediate layer includes elements of the gate dielectric layer and elements of the capping layer.
  • a difference between the top thickness and the bottom thickness is about 0.1 to about 0.8.
  • a ratio of the top thickness to the bottom thickness is about 1:0.80 to about 1:0.99.
  • the portions of the gate dielectric layer include a first portion surrounding a bottommost layer of the semiconductor layers and a second portion surrounding a topmost layer of the semiconductor layers.
  • the top thickness of the first portion is less than the top thickness of the second portion.
  • a difference between the top thickness of the first portion and the top thickness of the second portion is about 0.2 to about 0.8.
  • the present disclosure is directed to a method.
  • the method includes receiving a structure of a semiconductor device in a processing chamber.
  • the semiconductor structure includes a semiconductor substrate, a stack of first semiconductor layers and second semiconductor layers over the semiconductor substrate, a dummy gate structure over the stack, and source/drain features on both ends of the stack.
  • the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack.
  • the dummy gate structure wraps around top and side surfaces of the stack.
  • the method also includes removing the dummy gate structure and the first semiconductor layers, forming an interfacial layer surrounding the second semiconductor layers, forming a gate dielectric layer surrounding the interfacial layer, and forming a gate electrode surrounding the gate dielectric layer.
  • the forming of the gate dielectric layer includes adjusting time durations to form the gate dielectric layer having a non-conformal profile.
  • the forming of the gate dielectric layer includes introducing a first precursor to the gate dielectric into the reaction chamber for a first time duration, conducting a first purging process of the processing chamber for a second time duration; introducing a second precursor to the gate dielectric layer into the reaction chamber for a third time duration, and conducting a second purging process of the processing chamber for a fourth time duration.
  • a ratio of the fourth time duration to the first time duration is about 0.2:1 to about 1:1.
  • a ratio of the third time duration to the first time duration is about 0.65 to about 1.6.
  • a ratio of the second time duration to the first time duration is about 0.2:1 to about 1.6:1.
  • the forming of the gate dielectric layer includes repeating the introducing of the first precursor, the conducting of the first purging process, the introducing of the second precursor, and the conducting of the second purging process. In some embodiments, the forming of the gate dielectric layer includes forming the gate dielectric layer with the top section having a first thickness and the bottom section having a second thickness. A difference between the first thickness and the second thickness is at least about 1 ⁇ . In some embodiments, the method further includes forming a capping layer on the gate dielectric layer, and patterning the capping layer. In some embodiments, the patterning of the capping layer includes conducting a dry etching and a wet etching.
  • the present disclosure is directed to a method.
  • the method includes receiving in a processing chamber a semiconductor structure.
  • the semiconductor structure has a stack of first semiconductor layers and second semiconductor layers alternating with each other and vertically arranged above a semiconductor substrate and laterally between a pair of source/drain features.
  • the method also includes removing the first semiconductor layers to expose surfaces of the second semiconductor layers, forming an interfacial layer around the exposed surfaces of the second semiconductor layers, introducing into the processing chamber a first precursor in a first time duration to interact with the interfacial layer, after the introducing of the first precursor, conducting a first purging of the processing chamber, introducing into the processing chamber a second precursor in a second time duration to form a first layer of a gate dielectric, after the introduction of the second precursor, conducting a second purging of the processing chamber, and forming a work function metal layer on the gate dielectric.
  • the first time duration is less than the second time duration.
  • a ratio of the first time duration to the second time duration is about 1:0.65 to about 1:1.6.
  • the conducting of the second purging includes purging for a fourth time duration, and where a ratio of the first time duration to the fourth time duration is about 1:0.2 to about 1:1.
  • the method further includes repeating the introducing of the first precursor, the conducting of the first purging, the introducing of the second precursor, and the conducting of the second purging until a desired thickness of the gate dielectric is reached.
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