US11552082B2 - Reducing gate induced drain leakage in DRAM wordline - Google Patents
Reducing gate induced drain leakage in DRAM wordline Download PDFInfo
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- US11552082B2 US11552082B2 US17/002,415 US202017002415A US11552082B2 US 11552082 B2 US11552082 B2 US 11552082B2 US 202017002415 A US202017002415 A US 202017002415A US 11552082 B2 US11552082 B2 US 11552082B2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Definitions
- Embodiments of the present disclosure pertain to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the disclosure provide dynamic random-access memory cells with buried word lines having reduced gate induced drain leakage.
- DRAMs Dynamic random-access memories
- SRAM Static random-access memories
- DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.
- FET field effect transistor
- the manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage.
- DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with nonarray devices.
- DRAM word line utilize high work-function materials as a gate electrode in order to reduce channel impurities.
- An important leakage component in DRAM devices is gate-induced drain leakage (GIDL), which is caused by trap assisted band-to-band tunneling at the surface of the drain of the transistor, where the gate overlaps the drain.
- GIDL gate-induced drain leakage
- interface states in the substrate are created. These surface states increase the rate of generation of electron-hole pairs, enhancing GIDL.
- High work-function materials, used in DRAM word line can increase gate induced drain leakage near the source/drain area due to band-to-band-tunneling.
- a memory device comprises: a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall; a gate oxide layer on the bottom and sidewall of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work-function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trench; and a second work-function metal layer on the recessed metal layer.
- a method of forming a memory device comprises: providing a substrate having plurality of trenches thereon; depositing a conformal gate oxide layer on the substrate; forming a metal layer on the gate oxide layer; recessing the metal layer to form a recessed metal layer; and depositing a second work-function metal layer on the recessed metal layer.
- a memory cell comprises: a recessed access device; and a word line electrically coupled to the recessed access device, the word line comprising a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall; a gate oxide layer on the bottom and sidewall of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work-function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trench; and a second work-function metal layer on the recessed metal layer.
- FIG. 1 illustrates a circuit diagram of a DRAM cell block in accordance with the prior art
- FIG. 2 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 3 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 4 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 5 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 6 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 7 illustrates a cross-section view of a device according to one or more embodiments of the disclosure
- FIG. 8 illustrates a cross-section view of a device according to one or more embodiments of the disclosure.
- FIG. 9 illustrates a cross-section view of a device according to one or more embodiments of the disclosure.
- the terms “precursor”, “reactant”, “reactive gas” and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.
- DRAM dynamic access random memory
- DRAM dynamic access random memory
- a memory cell that stores a datum bit by storing a packet of charge (or not, for a zero) on a capacitor; the charge is gated onto the capacitor via an access transistor, and sensed by turning on the same transistor and looking at the voltage perturbation created by dumping the charge packet on the interconnect line on the transistor output.
- a single DRAM cell is made of one transistor and one capacitor.
- the DRAM device as illustrated in FIG. 1 , is formed of an array of DRAM cells.
- the rows on access transistors are linked by word lines 52 a , 52 b
- the transistor inputs/outputs are linked by bitlines 54 a , 54 b , 54 c .
- DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to 3-D structures which have diverged into “stack” capacitors with both plates above the substrate), and “trench” capacitors using an etched cavity in the substrate as the common plate.
- DRAM cells have recessed high work-function metal structures in buried word line structure.
- a bitline is formed in a metal level situated above the substrate, while the word line is formed at the polysilicon gate level at the surface of the substrate.
- the buried word line a word line is buried below the surface of a semiconductor substrate using a metal as a gate electrode.
- memory devices e.g. DRAM cells
- DRAM cells which utilize a low work-function material on top of a high work-function material.
- Such memory devices advantageously keep resistance low, while also keeping gate induced drain leakage (GIDL) low.
- Buried word line cell array transistors have a word line buried below the surface of a semiconductor substrate using a metal as a gate electrode in the structure.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the Surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes may be not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- FIGS. 2 through 9 are cross-sectional views illustrating a memory device 100 according to one or more embodiments.
- a substrate 102 is formed having a plurality of trenches 104 forming a recessed channel.
- the trenches have a bottom 106 and sidewall 108 .
- the plurality of trenches 104 may be formed so as to have a width within a range of about 10 to about 100 nm, including, but not limited to a range of about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm.
- the width of the plurality of trenches 104 is defined by a distance W 1 from one sidewall 108 to another sidewall 108 .
- the depth of the plurality of trenches 104 is defined by the distance D 1 from the substrate surface 103 to the bottom 106 of the plurality of trenches 104 .
- a “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process.
- a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application.
- Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and/or bake the substrate surface.
- any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such under-layer as the context indicates.
- substrate surface is intended to include such under-layer as the context indicates.
- a buffer insulating layer e.g. a silicon oxide layer, not shown
- a hard mask layer e.g. a nitride layer, not illustrated
- a gate oxide layer 110 is conformally deposited on the substrate 102 , on the substrate surface 103 and along the sidewall 108 and bottom 106 of the plurality of trenches 104 .
- the gate oxide layer 110 comprises one or more of silicon oxynitride (SiON), silicon oxide, or a high- ⁇ dielectric material.
- SiON silicon oxynitride
- silicon oxide silicon oxide
- a high- ⁇ dielectric material a high- ⁇ dielectric material.
- the term “high- ⁇ dielectric” refers to a material with a high dielectric constant (as compared to, e.g. silicon dioxide).
- the high- ⁇ dielectric material is selected from one or more of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), vanadium oxide (VO 2 ), titanium oxide (TiO 2 ), tin oxide (SnO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), or zirconium silicon oxide (ZrSiO).
- the gate oxide layer 110 has a thickness in a range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.
- a metal layer 113 is formed on the gate oxide layer 110 .
- the metal layer 113 is formed by depositing a conformal first work-functional metal layer 112 (see FIG. 4 ) on the conformal gate oxide layer 110 , followed by depositing a bulk metal layer 114 (see FIG. 5 ) on the first work-function metal layer 112 .
- the bulk metal layer 114 is deposited using any one of a number of methods known to one of skill in the art, including, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
- “Atomic layer deposition” or “cyclical deposition” as used herein refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface.
- the substrate, or portion of the substrate is exposed separately to the two or more reactive compounds which are introduced into a reaction zone of a processing chamber.
- a time-domain ALD process exposure to each reactive compound is separated by a time delay to allow each compound to adhere and/or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be exposed to the substrate sequentially.
- a spatial ALD process different portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to the two or more reactive compounds so that any given point on the substrate is substantially not exposed to more than one reactive compound simultaneously.
- the term “substantially” used in this respect means, as will be understood by those skilled in the art, that there is the possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and that the simultaneous exposure is unintended.
- a first reactive gas i.e., a first precursor or compound A, e.g. aluminum precursor
- a second precursor or compound B e.g. oxidant
- a purge gas such as argon
- the purge gas may flow continuously throughout the deposition process so that only the purge gas flows during the time delay between pulses of reactive compounds.
- the reactive compounds are alternatively pulsed until a desired film or film thickness is formed on the substrate surface.
- the ALD process of pulsing compound A, purge gas, compound B and purge gas is a cycle.
- a cycle can start with either compound A or compound B and continue the respective order of the cycle until achieving a film with the predetermined thickness.
- a first reactive gas and second reactive gas are delivered simultaneously to the reaction zone but are separated by an inert gas curtain and/or a vacuum curtain.
- the substrate is moved relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.
- chemical vapor deposition refers to a process in which a substrate surface is exposed to precursors and/or co-reagents simultaneous or substantially simultaneously.
- substantially simultaneously refers to either co-flow or where there is overlap for a majority of exposures of the precursors.
- PECVD Plasma enhanced chemical vapor deposition
- a hydrocarbon source such as a gas-phase hydrocarbon or a vapor of a liquid-phase hydrocarbon that have been entrained in a carrier gas
- a plasma-initiated gas typically helium
- Plasma is then initiated in the chamber to create excited CH-radicals.
- the excited CH-radicals are chemically bound to the surface of a substrate positioned in the chamber, forming the desired film thereon.
- Embodiments described herein in reference to a PECVD process can be carried out using any suitable thin film deposition system. Any apparatus description described herein is illustrative and should not be construed or interpreted as limiting the scope of the embodiments described herein.
- the term “work-function” refers to the bulk chemical potential of a material (e.g. metal) relative to the vacuum level.
- the first work-function metal layer has a work function greater than or equal to 4.3 eV. In some embodiments, the first work-function metal layer has a work function greater than or equal to 4.5 eV.
- the first work-function metal layer has a work-function greater than or equal to 4.3 eV, including greater than or equal to 4.4 eV, greater than or equal to 4.5 eV, greater than or equal to 4.6, greater than or equal to 4.7 eV, greater than or equal to 4.8 eV, greater than or equal to 4.9 eV, greater than or equal to 5.0 eV, greater than or equal to 5.1 eV, or greater than or equal to 5.2 eV.
- the first work-function metal layer comprises a metal nitride.
- the first work-function metal layer comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN/TiN, or WN/TiN.
- the first work-function metal layer is selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN/TiN, WN/TiN, and combinations thereof.
- the first work-function metal layer comprises titanium nitride.
- the first work-function metal layer may also be referred to the high/mid work-function metal layer.
- the first work-function metal layer 112 has a thickness in a range of about 1 nm to about 5 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm.
- the bulk metal layer 114 is also known as the word-line.
- the bulk metal layer 114 i.e. the word-line
- CMP chemical mechanical polishing
- the buried word line 115 may be formed by forming a word line layer 114 (i.e. bulk metal layer 114 ) on the substrate 102 so as to bury the trench 104 .
- the word line layer 114 may then be polished using a chemical mechanical polishing (CMP) method and etched back using a dry etch process to expose the substrate surface 103 .
- CMP chemical mechanical polishing
- the buried word line 115 may be formed by recessing the polished word line layer 114 into the substrate 102 using a partial etch process. As illustrated in FIG. 6 , the first work-function metal layer 112 is recessed to the same level as the buried word line 115 .
- a top surface 117 of the buried word line 115 and the first work-function metal layer 112 is a recess depth or distance D 2 from the substrate surface 103 in the plurality of trenches 104 .
- the buried word line 115 has a top surface 117 within the depth D 1 of the trench 104 . Accordingly, in one or more embodiments D 2 is less than D 1 .
- the bulk metal layer 114 (i.e. the word line) comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).
- the bulk metal layer 114 comprises tungsten (W).
- the bulk metal layer 114 comprises ruthenium (Ru).
- the buried word line 115 i.e.
- the recessed bulk metal layer 115 comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).
- the buried word line 115 comprises tungsten (W). In other embodiments, the buried word line 115 comprises ruthenium (Ru).
- a second work-function metal layer 116 is deposited on the substrate 102 on the recessed bulk metal layer 115 (i.e. on the buried word line). Referring to FIG. 8 , the second work-function metal layer 116 is then polished using a chemical mechanical polishing (CMP) method and etched back to expose the substrate surface 103 . A top surface 118 of the second work-function metal layer 116 is a distance D 3 from the substrate surface 103 in the plurality of trenches 104 . In one or more embodiments, the second work-function metal layer 116 has a top surface 118 within the depth D 1 of the trench 104 . Accordingly, in one or more embodiments D 3 is less than D 1 .
- the second work-function metal layer 116 has a work-function that is less than the work-function of the first work-function layer. In one or more embodiments, the second-work function metal layer 116 has a work-function less than about 4.3 eV. In some embodiments, the second work-function metal layer 116 has a work function less than or equal to about 4.2 eV.
- the work-function of the second work-function metal layer 116 is less than or equal to about 4.25 eV, less than or equal to about 4.2 eV, less than or equal to about 4.15 eV, less than or equal to about 4.1 eV, less than or equal to about 4.05 eV, less than or equal to about 4 eV, less than or equal to about 3.5 eV, or less than or equal to about 3.0 eV.
- the second work-function metal layer 116 may also be known as the low work-function layer.
- Resistivity is a property of a material that quantifies how strongly that material opposes the flow of electric current. A low resistivity indicates that a material readily permits the flow of electric current. High resistivity materials do not readily permit the flow of electric current.
- high resistivity material refers to a material or substance having a resistivity of greater than about 500 ⁇ -cm.
- the second work-function metal layer 116 has a resistivity of less than about 500 ⁇ -cm, including less than about 400 ⁇ -cm, less than about 300 ⁇ -cm, less than about 200 ⁇ -cm, or less than about 100 ⁇ -cm.
- the second work-function metal layer 116 is substantially free of polysilicon and/or doped polysilicon.
- the term “substantially free” means that there is less than 5%, including less than 4%, less than 3%, less than 2%, less than 1%, and less than 0.5% of polysilicon and/or doped polysilicon present in the second work-function metal layer 116 .
- the term “polysilicon” or “poly-Si” refers to a form of polycrystalline silicon.
- the second work-function metal layer 116 comprises a metal carbide or a metal silicide with one or more metal selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Th).
- metal carbide refers to a composite material composed of carbon and, generally, a less electronegative metal.
- metal silicide refers to a composite material composed of silicon and, generally, a more electropositive metal. As recognized by the skilled artisan, metal silicides, which are composite materials, are distinct from polysilicon and doped polysilicon.
- the second work-function metal layer 116 comprises a metal carbide or a metal silicide with one or more metal selected from gallium (Ga), indium (In), or thallium (Th).
- the second work-function metal layer 116 comprises aluminum carbide or aluminum silicide.
- the second work-function metal layer 116 comprises gallium carbide or gallium silicide.
- the second work-function metal layer 116 comprises indium carbide or indium silicide.
- the second work-function metal layer 116 comprises thallium carbide or thallium silicide.
- the second work-function metal layer 116 comprises one or more metal selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Th). In other embodiments, the second work-function metal layer 116 comprises one or more metal selected from gallium (Ga), indium (In), or thallium (Th). In one or more embodiments, the second work-function metal layer 116 comprises aluminum. In one or more embodiments, the second work-function metal layer 116 comprises gallium. In one or more embodiments, the second work-function metal layer 116 comprises indium. In one or more embodiments, the second work-function metal layer 116 comprises thallium.
- the second work-function metal layer 116 has a thickness T 1 in a range of about 10 nm to about 50 nm, including about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, or about 50 nm.
- an insulating layer 120 is deposited on the second work-function metal layer 116 .
- the insulating layer has a top surface 122 substantially coplanar with the substrate surface 103 .
- the insulating layer 120 comprises a dielectric material.
- the term “dielectric” refers to an electrical insulator material that can be polarized by an applied electric field.
- the dielectric material includes, but is not limited to, oxides, e.g., SiO 2 , Al 2 O 3 , nitrides, e.g., Si 3 N 4 .
- the dielectric material comprises silicon nitride (Si 3 N 4 ).
- the insulating layer composition is non-stoichiometric relative to the ideal molecular formula.
- the dielectric material includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g. silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g. silicon oxycarbonitride (SiNCO)).
- oxides e.g., silicon oxide, aluminum oxide
- nitrides e.g., silicon nitride (SiN)
- oxycarbides e.g. silicon oxycarbide (SiOC)
- SiNCO silicon oxycarbonitride
- a memory cell comprises: a recessed access device; and a word line electrically coupled to the recessed access device, the word line comprising a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall; a gate oxide layer on the bottom and sidewall of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work-function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trench; and a second work-function metal layer on the recessed metal layer.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
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Abstract
Description
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US20230083577A1 (en) * | 2021-09-13 | 2023-03-16 | Applied Materials, Inc. | Recessed metal etching methods |
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KR102008318B1 (en) * | 2012-12-06 | 2019-08-08 | 삼성전자주식회사 | Semiconductor device |
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TW202027233A (en) | 2020-07-16 |
JP2020107883A (en) | 2020-07-09 |
KR20200064925A (en) | 2020-06-08 |
CN111244093A (en) | 2020-06-05 |
TWI825224B (en) | 2023-12-11 |
US20200176451A1 (en) | 2020-06-04 |
US10790287B2 (en) | 2020-09-29 |
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