US11145612B2 - Methods for bump planarity control - Google Patents
Methods for bump planarity control Download PDFInfo
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- US11145612B2 US11145612B2 US15/856,236 US201715856236A US11145612B2 US 11145612 B2 US11145612 B2 US 11145612B2 US 201715856236 A US201715856236 A US 201715856236A US 11145612 B2 US11145612 B2 US 11145612B2
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/07—Polyamine or polyimide
- H01L2924/07025—Polyimide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
Definitions
- Some integrated circuit (IC) packaging technologies utilizes bumps rather than wirebonding to establish electrical contact between an IC die and the substrate or lead frame of a package, or another integrated circuit.
- a bump is made up of the bump itself and a under bump metallization layer located between the bump and an I/O pad of the IC die.
- the bumps themselves, based on the material used, can be classified as solder bumps, gold bumps, copper pillar (or copper post) bumps and bumps with mixed metals.
- copper pillar (or copper post) bump technology instead of using a solder bump, an IC die is connected to a substrate or other external circuitry by copper post bumps. Copper post bumps allow finer I/O pitches than solder bumps, with reduced probability of bump bridging and reduced capacitive loading.
- a method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an integrated circuit die to an external circuit. The method also includes concurrently depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.
- an integrated circuit package in another example, includes a redistribution layer and a plurality of conductive bumps.
- the conductive bumps are formed on the redistribution layer to connect an IC die to an external circuit.
- a first of the bumps includes a metal post.
- the metal post includes a first metal layer extending from the redistribution layer, and a second metal layer deposited on and extending from the first metal layer.
- a method for constructing an integrated circuit integrated circuit package includes forming a redistribution layer on an integrated circuit die. Forming the redistribution layer includes depositing a first layer of photoresist material on the integrated circuit die. The first layer of photoresist material is removed from input/output pads of the integrated circuit die. A first layer of metal is deposited on the photoresist material and the input/output pads of the integrated circuit die. A second layer of photoresist material is deposited on the first layer of metal. The second layer of photoresist material is removed to expose portions of the first layer of metal.
- the first layer of metal is etched to form connections between a first of the input/output pads of the integrated circuit die and a location of a first metal post, and a second of the input/output pads of the integrated circuit die and a location of a second metal post.
- a third layer of photoresist material is deposited on the integrated circuit die.
- the third layer of photoresist material is removed from the location of the first metal post and the location of the second metal post.
- a fourth layer of photoresist material is applied to the integrated circuit die.
- the fourth layer of photoresist material is removed to expose, on the redistribution layer, the location of the first metal post, and to cover, on the redistribution layer, the location of the second metal post.
- the first metal post has a first cross sectional area
- the second metal post has a second cross sectional area.
- the second cross sectional area is larger than the first cross sectional area.
- a first layer of copper is deposited, while the fourth layer of photoresist material is in place, to construct the first metal post.
- the fourth layer of photoresist material is removed.
- a fifth layer of photoresist material that exposes the location of the first metal post and the location of the second metal post is deposited on the integrated circuit die.
- the fifth layer of photoresist material is thicker than the fourth layer of photoresist material.
- a second layer of copper is deposited to construct the first metal post and the second metal post while the fifth layer of photoresist is in place.
- FIG. 1 shows a flow diagram for a method for manufacturing an integrated circuit with bump height equalization in accordance with various examples
- FIG. 2 shows an integrated circuit die prepared for construction of bumps of different sizes in accordance with various examples
- FIG. 3 shows a photoresist material applied to the die in preparation for application of first layer of metal to the bumps in accordance with various examples
- FIG. 4 shows the die with photoresist material removed from bump locations selected for plating with layer of metal in accordance with various examples
- FIG. 5 shows the die with a layer of metal applied to the selected bump locations in accordance with various examples
- FIG. 6 shows the die stripped of photoresist material after deposition of the metal layer in accordance with various examples
- FIG. 7 shows a photoresist material applied to the die in preparation for application of second layer of metal to the bumps in accordance with various examples
- FIG. 8 shows the die with photoresist material removed from all bump locations for plating with a layer of metal in accordance with various examples
- FIG. 9 shows the die with a layer of metal applied to all bump locations in accordance with various examples
- FIG. 10 shows a layer of solder applied to all bump locations in accordance with various examples
- FIG. 11 shows the die with photoresist material removed to expose bumps in accordance with various examples
- FIG. 12 shows varying bump height caused by different cross-sectional bump areas
- FIG. 13 shows bumps with different cross-sectional areas and a same height in accordance with various examples
- FIG. 14 shows a reticle pattern applied to remove the photoresist material from selected bump locations in accordance with various examples
- FIG. 15 shows a reticle pattern applied to remove the photoresist material from all bump locations in accordance with various examples
- FIG. 16 shows a flow diagram for a method for packaging an integrated circuit in accordance with various examples.
- FIG. 17 shows a singulated integrated circuit with completed bumps in accordance with various examples.
- bump terminals While integrated circuit input/output using bump terminals provides a number of advantages, use of bump terminals is not without issue. Many assembly and reliability issues are caused by tilted dies, solder voids and non-wets. These defects are in turn often caused by the condition of the wafers during bumping. Bump feature size is one factor that affects plating thickness. As bump feature size increases, plated thickness also increases. Given that a die includes multiple bump feature sizes, the plating thickness associated with the different feature sizes varies, and the device bumps can consequently exhibit planarity issues that cause die tilt, solder voids, etc. Thus, poor bump planarity is one cause of poor package reliability.
- Implementations of the present disclosure include methods for manufacturing an integrated circuit with equalized bump height. Implementations apply multiple layers of metal to construct bump terminals. At least one layer of the multiple layers of metal is applied to compensate for the difference in bump height attributable to different bump feature sizes of the integrated circuit. By equalizing the height of the various bumps of the integrated circuit, Implementations avoid the solder voids and other problems associated with poor bump planarity.
- FIG. 1 shows a flow diagram for a method 100 for manufacturing an integrated circuit with bump height equalization in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some Implementations may perform only some of the actions shown.
- FIG. 2 shows the integrated circuit die 200 prepared for construction of bumps of different sizes in accordance with various examples.
- the integrated circuit die 200 may include a redistribution layer 202 on which the bumps are to be formed, and a polyimide layer polyimide layer 204 that isolates the redistribution layer 202 .
- An opening 206 in the polyimide layer 204 allows for formation of a first bump and an opening 208 in the polyimide layer 204 allows for formation of a second bump.
- the area of the opening 208 is greater than the area of the opening 206 .
- the cross-sectional area of a bump formed at the opening 208 will be greater than the cross-sectional area of a bump formed at the opening 206 .
- the height of a bump formed at the opening 208 will be greater than the height of a bump formed at the opening 206 by deposition of a single layer of metal.
- the method 100 compensates for the difference in bump height produced by conventional IC processing. While FIG. 2 illustrates a single opening 206 and a single opening 208 , in practice the integrated circuit die 200 may include any number of openings 206 and any number of openings 208 each corresponding to a bump.
- FIG. 3 shows the photoresist material 312 applied to the integrated circuit die 200 in preparation for application of first layer of metal.
- the photoresist material 312 applied to the integrated circuit die 200 in block 102 is removed from the opening 206 to allow addition of metal at the opening 206 .
- FIG. 4 shows the photoresist material 312 removed from the opening 206 .
- the opening 208 remains covered by the photoresist material 312 to prevent addition of metal at the opening 208 .
- FIG. 14 shows an example of a reticle pattern 1400 that may be applied to remove the photoresist material 312 from the opening 206 and any number of additional bump locations of a same area as the opening 206 while leaving the opening 208 and any number of additional bump locations of a same area as the opening 208 covered by the photoresist material 312 .
- the reticle pattern 1400 includes an opening 1402 that corresponds to the opening 206 and lacks an opening corresponding to the opening 208 .
- a layer of metal is deposited at the opening 206 to form a bump (i.e., a metal post) at the opening 206 .
- FIG. 5 shows a layer of metal 502 deposited at the opening 206 .
- the layer of metal 502 is copper is some implementations.
- the thickness of the layer of metal 502 is selected to compensate for the difference in height of a bump formed at the opening 206 and a bump formed at the opening 208 if a single layer of metal is applied to the integrated circuit die 200 that produces a bump of a given height at the opening 208 .
- the photoresist material 312 prevents deposition of metal at the opening 208 .
- FIG. 6 shows the integrated circuit die 200 stripped of the photoresist material 312 after deposition of the layer of metal 502 .
- a second layer of photoresist material is deposited on the integrated circuit die 200 .
- the second layer of photoresist material may be thicker than the layer of photoresist material applied in block 102 .
- FIG. 7 shows the second layer of photoresist material 702 applied to the integrated circuit die 200 .
- the photoresist material 702 covers the opening 208 and covers the layer of metal 502 at the opening 206 .
- the thickness of the second layer of photoresist material 702 may be greater than the thickness of the photoresist material 312 .
- the photoresist material 702 applied in block 110 is removed from the opening 208 and from the layer of metal 502 at the opening 206 to allow addition of metal at the opening 208 and to the layer of metal 502 at the opening 206 .
- FIG. 8 shows the photoresist material 702 removed from the opening 208 and from the layer of metal 502 at the opening 206 for plating with a layer of metal.
- the photoresist material 702 may be removed from all bump locations on the integrated circuit die 200 .
- FIG. 15 shows an example of a reticle pattern 1500 that may be applied to remove the photoresist material 702 from all bump locations (e.g., opening 206 and opening 208 ) of the integrated circuit die 200 .
- the reticle pattern 1500 includes opening 1502 that corresponds to the opening 206 and opening 1504 that corresponds to the opening 208 .
- a layer of metal is deposited at the opening 208 and on the layer of metal 502 at the opening 206 to form a bump (i.e., a metal post) at the opening 208 and to increase the height of the bump (i.e., the metal post) at the opening 206 .
- FIG. 9 shows a layer of metal 902 deposited at the opening 208 and on the layer of metal 502 at the opening 206 .
- the layer of metal 902 is a same metal as the layer of metal 502 .
- the layer of metal 502 and the layer of metal 902 are copper in some Implementations.
- the thickness of the layer of metal 902 is selected to produce a bump at the opening 208 of a given height.
- the bump formed at the opening 206 is substantially the same height as (e.g., coplanar with) the bump formed at the opening 208 , while the volume of the bump formed at the opening 208 is greater than the volume of the bump formed at the opening 206 .
- a layer of solder may be deposited atop the layer of metal 902 to facilitate conductive connection of the die 200 to other circuits when the solder is reflowed.
- FIG. 10 shows a layer of solder 1002 deposited top the layer of metal 902 at the opening 206 and the opening 208 .
- the photoresist material 702 is removed from the integrated circuit die 200 to expose the bumps formed at the opening 206 and the opening 208 .
- FIG. 11 shows the photoresist material 702 removed from the die 200 to expose the bumps formed at the opening 206 and the opening 208 .
- FIG. 12 shows a die 1200 that was not manufactured in accordance with the method 100 after solder reflow.
- the cross-sectional area of the bump 1202 is smaller than the cross-sectional area of the bump 1204 . Consequently, the height of the bump 1202 is less than the height of the bump 1204 which may result in misconnection of the bump 1202 to an underlying pad or cause the die 1200 to be tilted relative to the underlying substrate.
- FIG. 13 shows a die 1300 that was manufactured in accordance with the method 100 after solder reflow. Even though the cross-sectional area of the bump 1302 is smaller than the cross-sectional area of the bump 1304 , the height of the bump 1302 is the same as the height of the bump 1304 due to the compensation provided by the method 100 . As a result, misconnection of the bump 1302 to an underlying pad or tilt of the die 1300 relative to the underlying substrate is avoided.
- FIG. 16 shows a flow diagram for a method 1600 for bump completion and singulation in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some Implementations may perform only some of the actions shown.
- a semiconductor wafer is received.
- a semiconductor wafer produced in a semiconductor wafer factory may be received by a semiconductor packaging facility that is to package the die provided on the semiconductor wafer.
- a redistribution layer is deposited on the semiconductor wafer.
- the redistribution layer provides conductors for connecting the input/output pads of each die of the semiconductor wafer to a location at which a bump is to be deposited.
- Deposition of the redistribution layer may include depositing a layer of photoresist material on the semiconductor wafer, and applying lithography to remove the photoresist material from the locations of input/output pads of each die formed on the semiconductor wafer.
- a layer of metal is deposited on the photoresist material.
- a layer of photoresist material is deposited on the metal layer and lithography is applied to pattern the photoresist material for formation of conductive traces that connect the input/output pads of each die to a location at which a bump is to be deposited.
- the layer of photoresist material and the layer of metal are removed in accordance with the pattern applied to the photoresist to form the conductive traces that connect the input/output pads of each die to a location at which a bump is to be constructed.
- a layer of photoresist material (e.g., a layer of polyimide) is deposited on the semiconductor wafer. Lithography is applied to pattern the photoresist material for exposure of the metal deposited in block 1604 at the locations at which each bump is to be constructed. The photoresist is removed from each location at which a bump is to be constructed.
- bumps are deposited on the semiconductor wafer in accordance with the method 100 .
- the height of the bumps is consistent with varying cross-sectional area.
- the dice are singulated from the semiconductor wafer.
- each die may be attached (e.g., by reflow of the bumps, to a substrate, and encapsulated in a mold compound.
- FIG. 17 shows an integrated circuit package 1700 in accordance with various examples.
- the integrated circuit package 1700 includes an integrated circuit die 1702 , a redistribution layer 1704 , a polyimide layer 1706 , bumps 1714 having a first cross-sectional area, and bumps 1716 having a second cross-sectional area.
- the cross-sectional area of bumps 1716 is greater than the cross-sectional area of bumps 1714 .
- the polyimide layer 1706 is disposed over the metal of the redistribution layer 1704 .
- the bump 1714 includes a first copper layer 1708 and a second copper layer 1710 deposited on the redistribution layer 1704 .
- the bump 1716 includes the second copper layer 1710 deposited on the redistribution layer 1704 (i.e., the bump 1716 does not include the first copper layer 1708 ).
- the bumps 1714 and 1716 include solder 1712 (e.g., tin/silver solder) deposited on the second copper layer 1710 .
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Abstract
Description
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CN110600387A (en) * | 2019-09-11 | 2019-12-20 | 中国电子科技集团公司第五十八研究所 | Preparation method of bumps with different specifications and sizes |
US11676932B2 (en) * | 2019-12-31 | 2023-06-13 | Micron Technology, Inc. | Semiconductor interconnect structures with narrowed portions, and associated systems and methods |
CN114551246B (en) * | 2022-04-25 | 2022-08-02 | 宁波芯健半导体有限公司 | Wafer and method for improving height uniformity of electroplating bumps |
CN114783897B (en) * | 2022-04-25 | 2023-06-06 | 宁波芯健半导体有限公司 | Chip structure planted with different-size solder balls and processing technology thereof |
US20240055383A1 (en) * | 2022-08-11 | 2024-02-15 | Qualcomm Incorporated | Bump coplanarity for die-to-die and other applications |
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US6348401B1 (en) | 2000-11-10 | 2002-02-19 | Siliconware Precision Industries Co., Ltd. | Method of fabricating solder bumps with high coplanarity for flip-chip application |
US20020070440A1 (en) * | 2000-12-12 | 2002-06-13 | Fujitsu Limited | Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal |
US20020139976A1 (en) * | 2001-04-02 | 2002-10-03 | Hembree David R. | Method for fabricating semiconductor components |
US20120043654A1 (en) * | 2010-08-19 | 2012-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US8860222B2 (en) * | 2011-12-27 | 2014-10-14 | Maxim Integrated Products, Inc. | Techniques for wafer-level processing of QFN packages |
US20130193569A1 (en) * | 2012-01-31 | 2013-08-01 | Texas Instruments Incorporated | Integrated Circuit Die And Method Of Fabricating |
US20140159235A1 (en) * | 2012-12-06 | 2014-06-12 | Fujitsu Limited | Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus |
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