US11114004B2 - Gate driving unit, driving method thereof, gate driving circuit and display device - Google Patents

Gate driving unit, driving method thereof, gate driving circuit and display device Download PDF

Info

Publication number
US11114004B2
US11114004B2 US16/094,615 US201816094615A US11114004B2 US 11114004 B2 US11114004 B2 US 11114004B2 US 201816094615 A US201816094615 A US 201816094615A US 11114004 B2 US11114004 B2 US 11114004B2
Authority
US
United States
Prior art keywords
clock signal
pull
electrode
node
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/094,615
Other languages
English (en)
Other versions
US20210225227A1 (en
Inventor
Yan Li
Lingyun SHI
Wei Sun
Xiaobo Xie
Meiling Jin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Assigned to BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, Meiling, LI, YAN, SHI, LINGYUN, SUN, WEI, XIE, XIAOBO
Publication of US20210225227A1 publication Critical patent/US20210225227A1/en
Application granted granted Critical
Publication of US11114004B2 publication Critical patent/US11114004B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the first reference clock signal and the second reference clock signal are at a same frequency and in opposite phases.
  • the present disclosure provides in some embodiments a gate driving circuit including a plurality of the above-mentioned gate driving units connected to each other in a cascaded manner.
  • the present disclosure provides in some embodiments a display device including the above-mentioned gate driving circuit.
  • FIG. 1 is a schematic view showing a gate driving unit according to some embodiments of the present disclosure
  • FIG. 2 is another schematic view showing the gate driving unit according to some embodiments of the present disclosure
  • FIG. 5 is a sequence diagram of signals for the gate driving unit according to the first embodiment of the present disclosure.
  • FIG. 6 is another circuit diagram of the gate driving unit according to a second embodiment of the present disclosure.
  • the clock signals applied to CKB_N and CK_N are those desired for a display function of the gate driving unit.
  • the first control signal and the second control signal are both clock signals.
  • the waveform of the first control signal and the waveform of the second control signal may be adjusted through a display driving Integrated Circuit (IC).
  • IC Integrated Circuit
  • the clock signal control module includes: a first switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the first reference clock signal end, and a second electrode of which is connected to the first clock signal end; a second switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the first clock signal end, and a second electrode of which is connected to the second reference clock signal end; and an inverter, an input end of which is connected to the first clock signal end, and an output end of which is connected to the second clock signal end. Through the inverter, it is able to ensure that the clock signal applied to the first clock signal end is in a phase opposite to the clock signal applied to the second clock signal end.
  • the pull-down node control module is further connected to the gate driving signal output end and a first level input end, and further configured to control the pull-down node to be electrically connected to the first level input end when the potential at the pull-up node is the second level, and control the pull-down node to be electrically connected to the first level input end when the a gate driving signal from the gate driving signal output end is at the second level.
  • the output module is further connected to the first level input end, and further configured to control the gate driving signal output end to be electrically connected to the first level input end when a potential at the pull-down node is the second level.
  • the output module may include: a pull-up transistor, a gate electrode of which is connected to the pull-up node, a first electrode of which is connected to the second clock signal end, and a second electrode of which is connected to the gate driving signal output end; and a pull-down transistor, a gate electrode of which is connected to the pull-down node, a first electrode of which is connected to the gate driving signal output end, and a second electrode of which is connected to the first level input end.
  • the input resetting module includes: an inputting transistor MI, a gate electrode of which is connected to an input end STV, a drain electrode of which is connected to a first scanning level input end CN, and a source electrode of which is connected to the pull-up node PU; and a resetting transistor MR, a gate electrode of which is connected to a resetting end RESET, a drain electrode of which is connected to the pull-up node PU, and a source electrode of which is connected to a second scanning level input end CNB.
  • the storage module includes a storage capacitor Cs, a first end of which is connected to the pull-up node PU, and a second end of which is connected to the gate driving signal output end OUT.
  • the pull-up node control module includes a pull-up node control transistor MUC, a gate electrode of which is connected to the pull-down node PD, a drain electrode of which is connected to the pull-up node PU, and a source electrode of which is connected to the low level input end to which the low level VGL is inputted.
  • CKB_N and CK_N are both clock signals desired for the display operation of the gate driving unit.
  • all the transistors are N-type transistors.
  • the transistors may also be P-type transistors, and at this time, it is necessary to adjust a sequence of the control signals.
  • the types of the transistors will not be particularly defined herein.
  • EN 1 outputs a high level and EN 2 outputs a low level, so CK_N is electrically connected to CK, and CKB_N is electrically connected to CKB.
  • MI is turned on due to an input signal from STV, and CN outputs a high level, so as to pull up the potential at PU, turn on MDC 1 , and pull down the potential at PD.
  • the clock signal applied to CK_N is at a low level, so OUT outputs a low level.
  • a charging time of the gate line is equal to a duration within which the clock signal applied to CK_N is maintained at the high level.
  • the display panel is in a low power consumption mode, so the charging time of the gate line is larger than that in a high definition display mode.
  • MDC 1 and MDC 2 are both turned on, so as to pull down the potential at PD.
  • the display panel is in the high definition display mode, and the first control signal and the second control signal are both clock signals.
  • the gate driving unit includes the input resetting module, the storage module, the pull-up node control module, the pull-down node control module, the output module and the clock signal control module.
  • the pull-down node control module includes: a first pull-down node control transistor MDC 1 , a gate electrode of which is connected to the pull-up node PU, a drain electrode of which is connected to a low level input end to which a low level VGL is inputted, and a source electrode of which is connected to the pull-down node PD; a second pull-down node control transistor MDC 2 , a gate electrode of which is connected to the gate driving signal output end OUT, a drain electrode of which is connected to the pull-down node PD, and a source electrode of which is connected to the low level input end to which the low level VGL is inputted; a third pull-down node control transistor MDC 3 , a gate electrode and a drain electrode of which are connected to the first clock signal end CKB_N, and a source electrode of which is connected to the pull-down node PD; and a pull-down node potential maintenance capacitor Cd, a first end of which is connected to the pull-down node
  • the frequency of the clock signal applied to each of the first clock signal end and the second clock signal end at the high definition display stage is greater than that at the low power consumption display stage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US16/094,615 2017-04-21 2018-03-14 Gate driving unit, driving method thereof, gate driving circuit and display device Active 2039-08-09 US11114004B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201710264805.0 2017-04-21
CN201710264805.0A CN106960652B (zh) 2017-04-21 2017-04-21 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
PCT/CN2018/078958 WO2018192326A1 (fr) 2017-04-21 2018-03-14 Unité d'attaque de grille, procédé d'attaque associé, circuit d'attaque de grille et dispositif d'affichage

Publications (2)

Publication Number Publication Date
US20210225227A1 US20210225227A1 (en) 2021-07-22
US11114004B2 true US11114004B2 (en) 2021-09-07

Family

ID=59483718

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/094,615 Active 2039-08-09 US11114004B2 (en) 2017-04-21 2018-03-14 Gate driving unit, driving method thereof, gate driving circuit and display device

Country Status (3)

Country Link
US (1) US11114004B2 (fr)
CN (1) CN106960652B (fr)
WO (1) WO2018192326A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220293028A1 (en) * 2021-03-11 2022-09-15 Novatek Microelectronics Corp. Timing control device and control method thereof
US11875726B2 (en) * 2021-07-30 2024-01-16 HKC Corporation Limited Drive circuit for display panel and display device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960652B (zh) 2017-04-21 2018-10-30 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN107452318B (zh) * 2017-09-20 2020-04-28 京东方科技集团股份有限公司 复位控制模块、其驱动方法及移位寄存器单元、显示装置
WO2020191695A1 (fr) * 2019-03-28 2020-10-01 京东方科技集团股份有限公司 Unité et procédé d'attaque de grille, circuit d'attaque de grille, panneau d'affichage et dispositif
KR20220017574A (ko) * 2020-08-04 2022-02-14 삼성디스플레이 주식회사 표시장치
KR20230016744A (ko) * 2021-07-26 2023-02-03 삼성디스플레이 주식회사 표시 장치 및 그것의 구동 방법

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110148853A1 (en) 2009-12-18 2011-06-23 Gwang-Bum Ko Display panel
CN103268757A (zh) 2012-06-29 2013-08-28 上海天马微电子有限公司 一种液晶显示面板的栅极驱动模组及液晶显示面板
US20140160000A1 (en) * 2012-12-07 2014-06-12 Hefei Boe Optoelectronics Technology Co., Ltd. Shift register unit, gate driving circuit, and display device comprising the same
US20160049126A1 (en) * 2014-03-27 2016-02-18 Boe Technology Group Co., Ltd. Shift register unit, gate electrode drive circuit and display apparatus
CN106205461A (zh) 2016-09-30 2016-12-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106251804A (zh) 2016-09-30 2016-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US20160372063A1 (en) * 2015-01-04 2016-12-22 Ordos Yuansheng Optoelectronics Co., Ltd. Shift register unit and driving method thereof, gate driving circuit and display apparatus
CN106960652A (zh) 2017-04-21 2017-07-18 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
US20190019442A1 (en) * 2017-07-17 2019-01-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Gate driving circuit and driving method thereof
US20190130858A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driving circuit
US20190130859A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Goa driving circuit
US20190129547A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Single-type goa circuit and display apparatus
US20190228830A1 (en) * 2018-01-25 2019-07-25 Boe Technology Group Co., Ltd. Gate drive unit and driving method thereof and gate drive circuit
US20200226995A1 (en) * 2017-06-27 2020-07-16 Nanjing Cec Panda Fpd Technology Co., Ltd. Gate drive unit circuit, gate drive circuit and liquid crystal display device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110148853A1 (en) 2009-12-18 2011-06-23 Gwang-Bum Ko Display panel
CN103268757A (zh) 2012-06-29 2013-08-28 上海天马微电子有限公司 一种液晶显示面板的栅极驱动模组及液晶显示面板
US20140160000A1 (en) * 2012-12-07 2014-06-12 Hefei Boe Optoelectronics Technology Co., Ltd. Shift register unit, gate driving circuit, and display device comprising the same
US20160049126A1 (en) * 2014-03-27 2016-02-18 Boe Technology Group Co., Ltd. Shift register unit, gate electrode drive circuit and display apparatus
US20160372063A1 (en) * 2015-01-04 2016-12-22 Ordos Yuansheng Optoelectronics Co., Ltd. Shift register unit and driving method thereof, gate driving circuit and display apparatus
CN106251804A (zh) 2016-09-30 2016-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106205461A (zh) 2016-09-30 2016-12-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US20190005866A1 (en) 2016-09-30 2019-01-03 Boe Technology Group Co., Ltd. Shift Register Unit, Driving Method, Gate Driver on Array and Display Device
CN106960652A (zh) 2017-04-21 2017-07-18 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
US20200226995A1 (en) * 2017-06-27 2020-07-16 Nanjing Cec Panda Fpd Technology Co., Ltd. Gate drive unit circuit, gate drive circuit and liquid crystal display device
US20190019442A1 (en) * 2017-07-17 2019-01-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Gate driving circuit and driving method thereof
US20190130858A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driving circuit
US20190130859A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Goa driving circuit
US20190129547A1 (en) * 2017-10-31 2019-05-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Single-type goa circuit and display apparatus
US20190228830A1 (en) * 2018-01-25 2019-07-25 Boe Technology Group Co., Ltd. Gate drive unit and driving method thereof and gate drive circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
International Search Report and Written Opinion for Application No. PCT/CN2018/078958, dated Jun. 13, 2018, 12 Pages.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220293028A1 (en) * 2021-03-11 2022-09-15 Novatek Microelectronics Corp. Timing control device and control method thereof
US11862065B2 (en) * 2021-03-11 2024-01-02 Novatek Microelectronics Corp. Timing control device and control method thereof
US11875726B2 (en) * 2021-07-30 2024-01-16 HKC Corporation Limited Drive circuit for display panel and display device

Also Published As

Publication number Publication date
US20210225227A1 (en) 2021-07-22
WO2018192326A1 (fr) 2018-10-25
CN106960652B (zh) 2018-10-30
CN106960652A (zh) 2017-07-18

Similar Documents

Publication Publication Date Title
US11114004B2 (en) Gate driving unit, driving method thereof, gate driving circuit and display device
US10504601B2 (en) Shift register unit, driving method thereof, gate driving circuit and display device
US10446104B2 (en) Shift register unit, gate line driving device, and driving method
US10217391B2 (en) Shift register unit, gate driving circuit and driving method thereof, and display apparatus
US10210791B2 (en) Shift register unit, driving method, gate driver on array and display device
US10460671B2 (en) Scanning driving circuit and display apparatus
US10665146B2 (en) Shift register circuit, driving method, gate driving circuit and display device
US20170193885A1 (en) Shift register unit, driving method, gate driving circuit and display device
US10607529B2 (en) Shift register unit and driving method thereof, gate driving circuit and display apparatus
US20170287428A1 (en) Gate driving circuit and method of driving the same, display panel
US10140913B2 (en) Shift register unit, gate drive circuit and display device
US9437152B2 (en) Scan driving circuit
US20180335814A1 (en) Shift register unit, gate drive circuit and display apparatus having the same, and driving method thereof
US9306572B2 (en) Output buffer, gate electrode driving circuit and method for controlling the same
US9558704B2 (en) GOA circuit and liquid crystal display
WO2017067432A1 (fr) Unité de registre à décalage et son procédé de commande, registre à décalage et dispositif d'affichage
US10698526B2 (en) Compensation circuit, gate driving unit, gate driving circuit, driving methods thereof and display device
US20150318052A1 (en) Shift register unit, gate drive circuit and display device
US10115335B2 (en) Shift register unit and driving method thereof, gate driving circuit and display device
US10725579B2 (en) Compensation circuit, gate driving unit, gate driving circuit, driving methods thereof and display device
US10388203B2 (en) GOA unit circuits, methods for driving the same, and GOA circuits
US10319324B2 (en) Shift registers, driving methods, gate driving circuits and display apparatuses with reduced shift register output signal voltage switching time
US20200160767A1 (en) Gate driving circuit, shift register and driving control method thereof
US10706947B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US10902930B2 (en) Shift register, gate driving circuit and driving method, and display apparatus

Legal Events

Date Code Title Description
AS Assignment

Owner name: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAN;SHI, LINGYUN;SUN, WEI;AND OTHERS;REEL/FRAME:047216/0280

Effective date: 20180823

Owner name: BOE TECHNOLOGY GROUP CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAN;SHI, LINGYUN;SUN, WEI;AND OTHERS;REEL/FRAME:047216/0280

Effective date: 20180823

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE