US11049817B2 - Semiconductor device with integral EMI shield - Google Patents
Semiconductor device with integral EMI shield Download PDFInfo
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- US11049817B2 US11049817B2 US16/283,853 US201916283853A US11049817B2 US 11049817 B2 US11049817 B2 US 11049817B2 US 201916283853 A US201916283853 A US 201916283853A US 11049817 B2 US11049817 B2 US 11049817B2
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- die
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 150000001875 compounds Chemical group 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 238000005452 bending Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 2
- 230000009972 noncorrosive effect Effects 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 13
- 208000032365 Electromagnetic interference Diseases 0.000 description 11
- 239000004593 Epoxy Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H—ELECTRICITY
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Definitions
- the present invention relates generally to semiconductor devices and semiconductor device packaging and, more particularly, to semiconductor device packages with Electro-Magnetic Interference (EMI) shielding.
- EMI Electro-Magnetic Interference
- FIG. 1 is a perspective view of a convention sensor device
- FIG. 2A is a side view of a semiconductor device in accordance with an embodiment of the present invention.
- FIG. 2B is an enlarged perspective view of a portion of the semiconductor device of FIG. 2A ;
- FIG. 2C is a cross-sectional side view of a portion of the semiconductor device of FIG. 2A ;
- FIG. 3 is an enlarged perspective view of the semiconductor device of FIG. 2A during assembly.
- FIG. 4 is an enlarged perspective view of a portion of a semiconductor device according to another embodiment of the present invention.
- the present invention provides a semiconductor device including a lead frame having a die pad, a plurality of leads that surround the die pad, and a shielding lead.
- a first integrated circuit (IC) die is attached to a surface of the die pad and electrically connected to a first set of leads of the plurality of leads.
- An encapsulation material covers and forms a mold body over the lead frame and the first IC die. Outer ends of the plurality of leads project from the sides of the mold body to allow electrical signals to be transmitted to and from the first IC die.
- the shielding lead projects from a central location of one side of the mold body and is bent up a surface of said one side and at least partially over a top surface of the mold body. The shielding lead inhibits electromagnetic interference.
- the present invention is a shielded semiconductor device, including a lead frame having a die pad, a plurality of leads that surround the die pad, and a shielding lead.
- a first IC die is attached to a surface of the die pad and electrically connected to a first set of leads of the plurality of leads.
- a second IC die is attached to a top surface of the first IC die and electrically connected to at least one of the first die and a second set of the plurality of leads.
- a first set of bond wires electrically connect the first IC die to the first set of leads, and a second set of bond wires electrically connect the second IC die to the first IC die, the second set of leads, and the shielding lead.
- An encapsulation material covers and forms a mold body over the lead frame and the first IC die. Outer ends of the plurality of leads project from the sides of the mold body to allow electrical signals to be transmitted to and from the first IC die.
- the shielding lead projects from a central location of one side of the mold body and is bent up a surface of said one side and at least partially over a top surface of the mold body. The shielding lead inhibits electromagnetic interference.
- the present invention provides a method of assembling a semiconductor device, including providing a lead frame having a die pad, a plurality of leads that surround the die pad, and a shielding lead, attaching a first IC die to the die pad, electrically connecting the first IC die to inner lead ends of a first set of the plurality of leads, electrically connecting the shielding lead to ground, and forming a mold body around the first IC die, the electrical connections and the lead frame with a molding compound, where distal ends of the plurality of leads project outwardly from the mold body and a distal end of the shielding lead projects outwardly from a central location of a side surface of the mold body.
- the distal end of the shielding lead is bent up the side surface of the mold body and over a top surface of the mold body.
- the semiconductor device 10 has a mold body 12 and first and second sets of pins 14 and 16 that project outward from the sides thereof.
- the first set of pins 14 are signal pins (e.g., bus in and bus out), while the second set of pins 16 are used for testing the internal circuitry and include pins for signals such as test clocks, test data in and out, power and ground.
- the conventional device 10 may be covered with a separate metal shield to prevent EMI.
- FIG. 2A is a side view of a semiconductor device 20 in accordance with an embodiment of the present invention.
- the device 20 comprises a mold body 22 , which is formed over one or more dies and a lead frame.
- the lead frame which will be described in more detail in conjunction with FIG. 3 , includes a die pad and a plurality of leads or lead fingers that surround the die pad.
- the plurality of leads includes first and second sets of leads 24 and 26 that project outwardly from the sides of the mold body 22 .
- the first set of leads 24 extend from a front side 25 (left side in FIG. 2A ), while the second set of leads 24 extend from one or more of the other sides of the mold body 22 .
- the first set of leads 24 comprise functional leads used for operation of the device 20
- the second set of leads 26 comprise test leads and are used for testing the device and its internal circuitry.
- the functional leads 24 are much longer than the test leads 26 , but this is not a requirement of the invention. It also is not a requirement of the invention that the signal leads project from only one side of the body 22 , while the test leads project from the other three lateral sides.
- shielding lead 28 that projects outwardly from a central location of one side of the mold body 22 .
- the shielding lead 28 projects from the back side 27 (right side in FIG. 2A ) of the mold body 22 .
- the shielding lead 28 is bent up a surface of the back side 27 and at least partially over a top surface 29 of the mold body 22 . Prior to bending, the shielding lead 28 projects straight out of the back side 27 , as shown in dashed lines.
- the shielding lead 28 may be attached to the back and top surfaces 27 and 29 of the mold body 22 with an adhesive, such as an epoxy or a double-sided tape. As will be discussed in more detail below, the shielding lead 28 provides EMI shielding.
- FIG. 2B is an enlarged perspective view of a portion of the semiconductor device 20 of FIG. 2A .
- FIG. 2B shows the shielding lead 28 projecting from the back side 27 of the device 20 , and extending up the back side 27 and over the top surface 29 . It also can be seen that there are test pins 26 that extend from the back side 27 .
- the shielding lead 28 is of greater dimensions than the test leads 26 .
- the test leads 26 may have a width of about 0.203 mm and a thickness of about 0.0127 mm, while the shielding lead 28 has a width of about 1.0 mm and a thickness of about 0.0127 mm.
- the shielding lead 28 may be formed in other locations of the lead frame, and that the dimensions of the shielding lead 28 will be influenced by the size of the package and the size of the die(s) that the shielding lead extends over.
- FIG. 2C is a cross-sectional side view of a portion of the device 20 , and illustrates that the device 20 includes a first semiconductor integrated circuit (IC) die 30 .
- the first IC die 30 is mounted on a die pad of the lead frame and electrically connected to the functional leads 24 and the test leads 26 .
- the first IC die 30 also may be electrically connected to the shielding lead 28 .
- the first IC die 30 is an Application Specific IC (ASIC) and includes control circuitry and the second IC die 32 is a sensor.
- ASIC Application Specific IC
- the first IC die 30 comprises a microcontroller die and the second die 32 is a sensor.
- the second die 32 is connected to the first die 30
- the first die is connected to the functional pins 14 .
- other arrangements of chips are possible, as will be readily understood by those of skill in the art, so the invention should not be limited by the number or arrangement of dies covered by the mold body 22 .
- FIG. 3 is an enlarged perspective view of one embodiment of the semiconductor device 20 of FIG. 2A during assembly.
- the device 20 is assembled using a lead frame 40 , which includes a die pad 42 and a plurality of leads or lead fingers 44 that surround the die pad 42 , and the shielding lead 28 .
- FIG. 3 is provided to show elements of the lead frame, the dies and the electrical connections therebetween.
- the die pad 42 is sized and shaped to support one or more semiconductor IC dies.
- the leads 44 generally extend perpendicularly away from the sides of the die pad 42 .
- the first IC die 30 is attached to the die pad 42 , such as with an adhesive or adhesive tape, and electrically connected to proximal ends (the ends of the leads near to the die pad) of at least some of the leads 44 and to the shielding lead 28 with first bond wires 46 .
- the shielding lead 28 is connected to ground pads of the first IC die 30 .
- the second IC die 32 is stacked on the first IC die 30 .
- the second IC die 32 is optional and may be located adjacent to the first IC die 30 . Furthermore, there could be one or more stacked dies and one or more adjacent dies.
- the second IC die 32 is electrically connected to the first IC die 30 with second bond wires 48 .
- the interconnection of the first and second dies 30 and 32 by the second bond wires 48 can be a source of EMI.
- the shielding lead 28 extends over the second bond wires 48 .
- the length of the shielding lead 28 will depend on how far the lead 28 must extend over the top surface of the mold body 22 in order to lie overtop of the second bond wires 48 (or any other specific source of EMI).
- the lead frame 40 may comprise copper that is at least partially plated with a non-corrosive metal or metal alloy, as is known in the art, and the die pad 42 may be rectangular.
- the lead frame 32 preferably is formed from a copper sheet by punching, stamping, cutting or etching, as is known in the art, and the underlying metal (e.g., Cu) is plated with one or more other metals or an alloy, such as Ni, Pd, and Au.
- the lead frame 32 includes the leads 14 , the die receiving area 16 , and the bendable strip 28 (shielding lead).
- the device 20 also may include a plurality of passive devices 50 that span some adjacent ones of the leads, but this is not a requirement of the invention.
- An encapsulation material (not shown in FIG. 3 ) is formed over the first and second IC die 30 and 32 , the electrical connections 46 and 48 , and the lead frame 40 to form the mold body 22 . Distal ends of the leads 44 then project outwardly from the sides of the mold body 22 . More particularly, as discussed with reference to FIG. 2A , signal leads 24 project from one side (the left side of the body in FIG. 2 ) of the body 22 and the test leads 24 project from one or more of the other lateral sides of the body 22 .
- the shielding lead 28 also has a distal portion that projects from a central location of one side of the mold body 22 and is bent up a surface of the one side and at least partially over the top surface 29 of the mold body 22 .
- FIG. 4 is an enlarged perspective view of a portion of a semiconductor device 60 in accordance with another embodiment of the present invention.
- the device 60 is similar to the device 20 of FIG. 2A , having a mold body 62 and a shielding lead 64 that projects outwardly therefrom.
- the shielding lead 64 is bent vertically such that it extends up a backside of the body 62 and then bent again so that it extends over a top surface of the body 62 .
- the shielding lead 64 has a first exterior section 66 that extends vertically along the back side of the device 60 and a second exterior portion 68 that extends horizontally over the top surface of the device 60 . Further, what is different from the embodiment shown in FIG.
- the second exterior portion 68 of the shielding lead 64 has a rectangular distal end portion 70 such that the shielding lead 64 is T-shaped.
- the distal end portion 70 is sized and shaped like an underlying IC chip such that the distal end 70 extends over substantially all of the surface of the IC die beneath the mold compound and at least some of the electrical connections between the IC die and the leads to which the die is connected.
- the distal end portion 70 has a width that is greater than a width of the second exterior portion 68 .
- the bottom die could be flip-chip connected to the lead frame.
- trim and form processes are performed in which outer portions of the lead frame are cut away and the outer lead ends of the leads 24 , 28 and 28 extend beyond an outer edge of the body 22 , thereby providing the packaged semiconductor device 20 .
- the outer lead ends of some of the leads, such as the test leads, may or may not extend beyond the outer edge of the body 12 depending on design requirements and the functional leads may be bent into desired shapes such as Gull Wing and J-leads.
- the present invention provides a packaged semiconductor device that has a shielding lead that extends vertically and horizontally around the body of the device to provide EMI and RFI shielding.
- the shielding lead is part of a lead frame.
- the shielding lead may include one or more kinks to facilitate bending the lead around the outside of the package.
- the shielding lead may be bent around the mold body during a normal trim and form operation, thus extra steps for attaching a separate shield or metal cap are not necessary, which saves on assembly time and cost.
- each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range.
- labels such as top, bottom, front and back have been used, it is understood that such are relative terms, so such surfaces or orientations are not absolute.
- stacked die devices are shown and described, the invention is not limited to stacked die devices, as a single die device, a device with side-by-side dies, or a device with a combination of stacked dies and side-by-side dies may be assembled that include the shielding lead.
- each may be used to refer to one or more specified characteristics of a plurality of previously recited elements or steps.
- the open-ended term “comprising” the recitation of the term “each” does not exclude additional, unrecited elements or steps.
- an apparatus may have additional, unrecited elements and a method may have additional, unrecited steps, where the additional, unrecited elements or steps do not have the one or more specified characteristics.
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Abstract
Description
Claims (19)
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US16/283,853 US11049817B2 (en) | 2019-02-25 | 2019-02-25 | Semiconductor device with integral EMI shield |
CN202010100658.5A CN111613598A (en) | 2019-02-25 | 2020-02-18 | Semiconductor device with integrated EMI shielding |
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US16/283,853 US11049817B2 (en) | 2019-02-25 | 2019-02-25 | Semiconductor device with integral EMI shield |
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US20200273810A1 US20200273810A1 (en) | 2020-08-27 |
US11049817B2 true US11049817B2 (en) | 2021-06-29 |
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US11069600B2 (en) * | 2019-05-24 | 2021-07-20 | Infineon Technologies Ag | Semiconductor package with space efficient lead and die pad design |
US11348866B2 (en) * | 2020-06-16 | 2022-05-31 | Infineon Technologies Austria Ag | Package and lead frame design for enhanced creepage and clearance |
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US20200273810A1 (en) | 2020-08-27 |
CN111613598A (en) | 2020-09-01 |
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