US11048476B2 - Non-linear feedback shift register - Google Patents

Non-linear feedback shift register Download PDF

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US11048476B2
US11048476B2 US16/553,460 US201916553460A US11048476B2 US 11048476 B2 US11048476 B2 US 11048476B2 US 201916553460 A US201916553460 A US 201916553460A US 11048476 B2 US11048476 B2 US 11048476B2
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gate
logic gate
taps
stage
nlfsr
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US20210064343A1 (en
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Andrew Johnson
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International Business Machines Corp
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International Business Machines Corp
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Priority to US16/553,460 priority Critical patent/US11048476B2/en
Priority to PCT/IB2020/057618 priority patent/WO2021038356A1/en
Priority to DE112020003328.7T priority patent/DE112020003328T5/de
Priority to GB2202639.7A priority patent/GB2601941B/en
Priority to JP2022513040A priority patent/JP7531579B2/ja
Priority to CN202080059362.1A priority patent/CN114270774B/zh
Publication of US20210064343A1 publication Critical patent/US20210064343A1/en
Priority to US17/241,517 priority patent/US11561768B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register

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  • the present invention relates to feedback shift registers, and more specifically, to a non-linear feedback shift register with maximal or near-maximal length sequences.
  • LFSR linear feedback shift register
  • a LFSR is a shift register whose input bit is a linear function of its previous state.
  • the most commonly used linear function of single bits is exclusive-or (XOR), and the shift register has an input bit driven by the XOR of some bits of the overall shift register value.
  • XOR exclusive-or
  • a rightmost bit of the LFSR is called the output bit.
  • the taps are XOR'd sequentially with the output bit and then fed back into the leftmost bit.
  • the sequence of bits in the rightmost position is called the output stream.
  • a maximum length LFSR produces an n-sequence as it cycles through all possible 2 n ⁇ 1 states within the shift register except the state where all bits are zeros. It is also possible to use XNOR resulting in an equivalent polynomial counter.
  • the arrangement of taps for feedback in an LFSR can be expressed in finite field arithmetic as a polynomial mod 2, where the coefficients of the polynomial must be 1 or 0, referred to as the feedback polynomial.
  • LFSRs with maximum period can be constructed using a primitive generator polynomial over the binary field.
  • the LFSR is maximal length if the corresponding feedback polynomial is primitive with the number of taps being even, and the set of taps being setwise co-prime.
  • the following is a table showing the feedback polynomials for n up to 24 bits from which maximal-length LFSRs can be constructed. There can be more than one maximal-length tap sequence for a given LFSR length.
  • the “+1” in the polynomial does not correspond to a tap; it corresponds to the input to the first bit.
  • the powers of the terms relate to the tapped bits, counting from the left. LFSRs with four terms plus the one, require four taps and therefore three XOR gates.
  • FIG. 1 shown is an example 8-stage LFSR 100 .
  • the 8 bits 101 - 108 of the register are shown numbered from 1-8 with the 8 th bit being the rightmost output bit 108 .
  • the 8 bit register shown has taps from the 4, 5, 6 and 8 bits, according to the polynomial x 8 +x 6 +x 5 +x 4 +1.
  • Each of the taps provide linear feedback using XOR gates 111 , 112 , 113 .
  • the feedback 120 is input to the 1 st bit 101 .
  • top-bottom hybrid LFSR generator in which the top LFSR tap is XOR'd with the last tap and the result is fed into the stage after the top tap.
  • the bottom tap is XOR'd with the last tap and the result is fed into the first stage of the shift register.
  • Top-bottom hybrid LFSR generators can be used to reduce the 4 taps to 3 taps (two XORs) as follows:
  • the first number is the number of stages
  • the second is the top LFSR tap
  • the third is the bottom LFSR tap.
  • a hybrid LFSR can generate a sequence of 2 n ⁇ 1. However, this requires access to both the middle of the shift register and the end to insert data.
  • LFSRs have the drawback that their linear complexity is equal to their order. More recently, non-linear feedback shift registers (NLFSR) have been designed. NLFSRs are a generalization of LFSRs in which a current state is a non-linear function of the previous state. So, in NLFSRs the re-entrant bit is more than just a simple XOR operation of register bits. This frees the registers from the rigidity of Galois, Fibonacci, and other predefined taps, but then it is necessary to make sure that lockup does not occur, and the registers do not settle into a pattern.
  • NLFSRs A problem with NLFSRs is finding a systematic procedure for constructing NLFSRs with a guaranteed long period.
  • FIG. 2 shown is an example 8-stage NLFSR 200 as proposed by Dubrova giving a maximal length sequence which is just one of the examples of the 15 options she proposes with three XOR and one AND gate.
  • the 8 bits 201 - 208 of the register are shown numbered from 1-8 with the 8 th bit being the rightmost output bit 208 .
  • the 8 bit register shown has taps from the 4, 5, and 8 bits (T 4 , T 5 , T 8 ).
  • the non-linear feedback 220 is provided with three XOR 211 - 213 and one AND gate 214 as follows: T 8 XOR T 5 XOR T 4 XOR (T 5 AND T 4 ). In Dubrova's notation where she numbers the taps (7 . . . 0), this is “0, 3, 4, (3, 4)”.
  • the problem addressed is to minimize the number of gates used in a logical feedback whilst maintaining maximal length sequences in pseudo-random number generators using feedback shift registers.
  • Feedback shift registers can also be used in problems expressed using Boolean Satisfiability.
  • LFSR sequences are used to solve the Hamiltonian Cycle problem. Minimizing the number of clauses to express the LFSR simplifies solving of the problem.
  • Embodiments of the present disclosure include a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence with at least near-maximal length for n number of stages, where a maximal length is 2 n ⁇ 1.
  • NLFSR non-linear feedback shift register
  • the first logic gate may be selected from a group consisting of an OR and a NAND gate, and the second logic gate is a XOR gate. In other embodiments, the first logic gate is an AND gate and the second logic gate is an XNOR gate.
  • a maximal length sequence is obtained with two suitable non-end taps
  • a near-maximal length sequence is obtained with two suitable non-end taps
  • the method may include obtaining one or more suitable pairs of non-end taps by identifying, based on the number of stages n, pair combinations that provide at least near-maximal length sequences of the n-stage register.
  • obtaining the one or more suitable pairs of non-end taps may include determining a first suitable pair of non-end taps that includes a first non-end tap A and a second non-end tap B; and obtaining a second suitable pair of non-end taps as the mirror of the first suitable pair of non-end taps in the n-stage register, where tap sequence [n, A, B] mirrors to [n, n ⁇ B, n ⁇ A].
  • obtaining the one or more suitable pairs of non-end taps includes using a search program operating on three taps: the end tap, and two non-end taps, using every combination of logic operation, except all zeros, subject to an optimization restriction that 1 and 0 are equally likely.
  • the search program initializes the register to a value other than all zeros, and runs the register at most 2 n times until a register state is generated that is a repeat, where a length of the sequence is a number of states from a first occasion a state was seen to a second occasion the state was seen.
  • the search program may determine if a number of states seen so far is 2 n-1 or more. If the number of states seen is 2 n-1 or more, then the longest sequence found is the longest possible for that set of taps. If the number of states seen is less than 2 n-1 , then a new state is chosen, the sequence is generated again, and the length is measured; and the search program repeats these steps until all the states are seen or the number of unseen states is less than the length of the longest sequence found.
  • Embodiments of the present disclosure include a NLFSR for generating a pseudo-random sequence with at least near-maximal length for n number of stages, wherein a maximal length is 2 n ⁇ 1.
  • the NLFSR comprises an n-stage register, where n requires more than two taps in maximal length linear feedback shift registers; a first logic gate having two inputs, each input being connected to a non-end tap of the n-stage register; and a second logic gate having two inputs, a first input being connected to an output of the first logic gate and a second input being connected to an end tap of the n-stage register, where an output of the second logic gate is used as feedback to a first stage of the n-stage register.
  • Embodiments of the present disclosure include a NLFSR for generating a pseudo-random sequence with maximal length for 8 stages, where the maximal length is 255.
  • the NLFSR includes a 8-stage register; a first logic gate having a first input connected to a first non-end tap A of the 8-stage register and a second input connected to a second non-end tap B of the 8-stage register; and a second logic gate having inputs connected to an output of the first logic gate and to an end tap of the 8-stage register.
  • Embodiments of the present disclosure include a NLFSR for generating a pseudo-random sequence with maximal length for n number of stages, where the maximal length is 4095.
  • the NLFSR includes a 12-stage register; a first logic gate having a first input connected to a first non-end tap A of the 12-stage register and a second input connected to a second non-end tap B of the 12-stage register; and a second logic gate having inputs connected to an output of the first logic gate and to an end tap of the 12-stage register.
  • FIG. 1 is a schematic circuit diagram showing an 8-stage LFSR.
  • FIG. 2 is a schematic circuit diagram showing an 8-stage NLFSR with a non-linear feedback arrangement providing a maximal length sequence.
  • FIG. 3 is a flow diagram of an example embodiment of a method for providing a NLFSR, in accordance with embodiments of the present disclosure.
  • FIG. 4 is a schematic circuit diagram of a generalized stage NLFSR, in accordance with a first embodiment of the present disclosure.
  • FIG. 5 is a schematic circuit diagram of a mirror generalized stage NLFSR, in accordance with a second embodiment of the present disclosure.
  • FIG. 6 is a schematic circuit diagram of a complement generalized stage NLFSR, in accordance with a third embodiment of the present disclosure.
  • FIG. 7 is a schematic circuit diagram of another complement generalized stage NLFSR, in accordance with a fourth embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit diagram of an 8-stage NLFSR in accordance with the first embodiment of FIG. 4 .
  • FIG. 9 is a schematic circuit diagram of an 8-stage NLFSR in accordance with the second embodiment of FIG. 5 .
  • FIG. 10 is a schematic circuit diagram of an 8-stage NLFSR in accordance with the third embodiment of FIG. 6 .
  • FIG. 11 is a schematic circuit diagram of an 8-stage NLFSR in accordance with the fourth embodiment of FIG. 7 .
  • FIGS. 12A to 12C are schematic circuit diagrams showing more details of the registers of FIGS. 8, 10 and 11 , in accordance with embodiments of the present disclosure.
  • FIG. 13 is block diagram of an example embodiment of a system in accordance with the embodiments of the present disclosure.
  • FIG. 14 is a block diagram of an embodiment of a computer system in which embodiments of the present disclosure may be implemented.
  • the described method and system provide a non-linear feedback shift register (NLFSR) with maximal or near-maximal length sequences for generating a pseudo-random sequence for some registers having n number of stages that require more than two taps for maximal length in linear feedback shift registers (LFSRs), usually four or more taps.
  • LFSRs linear feedback shift registers
  • the four taps in LFSRs use three XOR gates.
  • the maximal length sequences are 2 n ⁇ 1, where the missing state is all 0s, or for a complement logical operation, all 1s. Near-maximal in this description is defined as less than 4% deviation from the maximal length.
  • other n-stage registers that require more than two taps for maximal length sequences in LFSRs may also exist for n>24, and the described arrangements may also be used for these larger values of n.
  • the described non-linear feedback arrangement of two gates may be used by other n-stage registers that require more than two taps for maximal length sequences in LFSRs but may only give near-maximal length sequences. These may also be useful as the non-linear feedback arrangement of only two gates in a simplified feedback.
  • a simplified logic operation is provided as feedback in a NLFSR that provides a minimum number of gates with a maximal or a near-maximal length sequence.
  • a single XOR gate and a single OR gate are used in a feedback logical operation of a NLFSR.
  • the logical feedback of only one OR and only one XOR gate takes logical OR of two selected non-end taps and XOR with the end tap as the feedback to the first stage.
  • An alternative to XOR and OR is to use XNOR and NOR in an equivalent logical operation.
  • the complement diagrams cover a slightly different but just as useful sequence.
  • Other variations utilize one or more of the inverted outputs of the flip flop elements shift register, the Q-bar outputs, to provide the inversions.
  • inputs for the XOR gate are the output of stage n and the output of the OR gate, wherein inputs for the OR gate are the output of two suitable stages y 1 , y 2 (y 1 ⁇ n)), (y 2 ⁇ n)), and y 1 is not equal to y 2 ) and wherein the input for stage 1 is the output of the XOR gate.
  • FIG. 3 an example embodiment of the described method 300 for providing a NLFSR is shown in flow diagram.
  • the method 300 begins by selecting n as the number of stages in the register. This is illustrated at step 301 .
  • n requires more than two taps in a maximal length linear feedback shift register.
  • a normal Fibonacci LFSR requires 4 or more taps but may be implemented with 3 taps by a hybrid LFSR, so n requires more than 2 taps.
  • the method 300 uses feedback logical terms of only one OR gate and only one XOR gate, taking logical OR of two non-end taps and output XOR'd with the end tap for feedback to the first stage. This is illustrated at step 302 .
  • the same logical operation is used with XNOR gate and a NOR gate.
  • the method 300 may use a complement arrangement of only one XNOR and only one AND or a complement arrangement of only one XOR and only one NAND. This is illustrated at step 303 .
  • the method 300 continues by testing different combinations of candidate pairs of non-end taps to determine pair combinations that provide maximal or near-maximal length sequences of the n-stage register by searching for suitable pairs of non-end taps using three taps: the end tap, and candidate pairs of non-end taps, using every logic operation of three bits subject to the optimization restriction that 1 and 0 are equally likely. This is illustrated at step 304 . If is were more likely than 0s as output for all the possible inputs, then the outputs in general would have more is than 0s, so the counter could not cover almost all the states.
  • the number of possible pairs to search may be determined as: selecting the last tap for the XOR, selecting one of the n ⁇ 1 other taps for the first OR input, selecting one of the n ⁇ 2 remaining taps for the second input, and dividing the possibilities by 2, as the order of the OR inputs does not matter.
  • the register may be initialized to a value other than all 0000s (or all 1111s for a complement arrangement of taps) and may run the register at most 2 n times until it generates a register state which has been seen before.
  • the length of the sequence is the number of states from first occasion that repeated state was seen to the second occasion.
  • a near maximal length sequence it may be determined if the number of states seen so far is 2 n-1 or more. If it is, then any other sequence generated from a different starting state cannot be as long. If it is not, a state not seen so far will be chosen and the sequence will be generated again. The length of this sequence will be measured, and the process will be repeated until all the states are seen or the number of unseen states is less than the length of the longest sequence found so far.
  • the method 300 continues by obtaining one or more suitable pairs of non-end taps. This is illustrated at step 305 .
  • the method 300 may identify another suitable pair of non-end taps as the mirror of the taps in the n-stage register, wherein tap sequence [n, A, B] mirrors to [n, n ⁇ B, n ⁇ A]. This is illustrated at step 306 .
  • the method 300 continues by using a suitable pair of non-end taps in the feedback logic arrangement of the register. This is illustrated at step 307 .
  • FIGS. 4 to 7 show generalized n-stage NLFSRs 400 , 500 , 600 , 700 with feedback logical operations, in accordance with embodiments of the present disclosure.
  • n is restricted to n-stage registers that require more than two taps for maximal length sequences in linear feedback arrangements in LFSRs and for which suitable non-end taps are found, for example, using the method 300 of FIG. 3 .
  • FIG. 4 shown is an example register 400 with a first embodiment of the described logical feedback of only one OR 411 and only one XOR gate 412 , for n number of stages, numbered “1” 401 to “n” 404 from left to right in the register.
  • Inputs for the OR gate 411 are the outputs of two suitable stages “A” 402 and “B” 403 , where A, B ⁇ n and A ⁇ B and where A and B are suitable non-end taps.
  • Inputs for the XOR gate 412 are the output of stage n 404 and the output of the OR gate 411 .
  • the input 420 for stage 1 401 is the output of the XOR gate 412 .
  • FIG. 5 shown is an example register 500 with a second embodiment of the described logical feedback of only one OR 511 and only one XOR gate 512 , for n number of stages, numbered “1” 501 to “n” 504 from left to right in the register.
  • the second embodiment is a mirror or reverse of the logical arrangement of the first embodiment.
  • Inputs for the OR gate 511 are the outputs of two mirror suitable stages “n ⁇ B” 502 and “n ⁇ A” 503 .
  • Inputs for the XOR gate 512 are the output of stage n 504 and the output of the OR gate 511 .
  • the input 520 for stage 1 501 is the output of the XOR gate 512 .
  • FIG. 6 shown is an example register 600 with a third embodiment of a complement of the first embodiment. Specifically, shown is the described logical feedback of only one AND 611 and only one XNOR gate 612 , for n number of stages, numbered “1” 601 to “n” 604 from left to right in the register.
  • Inputs for the AND gate 611 are the outputs of two suitable stages “A” 602 and “B” 603 , where A, B ⁇ n and A ⁇ B and where A and B are suitable non-end taps.
  • Inputs for the XNOR gate 612 are the output of stage n 604 and the output of the AND gate 611 .
  • the input 620 for stage 1 601 is the output of the XNOR gate 612 .
  • FIG. 7 shown is an example register 700 with a fourth embodiment of another complement of the first embodiment. Specifically, shown is the described logical feedback of only one NAND 711 and only one XOR gate 712 , for n number of stages, numbered “1” 701 to “n” 704 from left to right in the register.
  • Inputs for the NAND gate 711 are the outputs of two suitable stages “A” 702 and “B” 703 , where A, B ⁇ n and A ⁇ B and where A and B are suitable non-end taps.
  • Inputs for the XOR gate 712 are the output of stage n 704 and the output of the NAND gate 711 .
  • the input 720 for stage 1 701 is the output of the XOR gate 712 .
  • Complement arrangements of the mirror embodiment of FIG. 5 may also be used.
  • mirror arrangements of the complement arrangements of FIGS. 6 and 7 may also be used.
  • taps are referred to by number in a register with the input first stage as 1 and the end stage as n. Where two successive register inputs are described, then A1 to An and B1 to Bn are used.
  • FIG. 8 shown is an example 8-stage register 800 with the described logical feedback of the first embodiment of FIG. 4 .
  • Suitable taps that achieve maximal length for an 8-stage register 800 using the described logical feedback are as follows:
  • the input 820 for stage 1 801 is the output of the XOR gate 812 .
  • A1 to A8 are the current states of an 8-stage shift register and B1 to B8 are the corresponding next states:
  • the illustrated embodiment requires one OR gate and one XOR gate.
  • the taps need to be chosen appropriately, but when they are operable they can generate a sequence of 2 n ⁇ 1.
  • T 8 XOR T 5 OR T 4
  • T 8 XOR T 3 OR T 4
  • FIG. 9 shown is an example 8-stage register 900 with the described logical feedback of the second embodiment of FIG. 5 as a mirror of the embodiment of FIG. 8 .
  • Inputs for the OR gate 911 are the outputs of the mirrors 3 903 and 4 904 .
  • the input 920 for stage 1 901 is the output of the XOR gate 912 .
  • FIG. 10 shown is an example 8-stage register 1000 with the described logical feedback of the third embodiment of FIG. 6 of a complement arrangement.
  • FIG. 10 shows a complement of the register of FIG. 8 .
  • the input 1020 for stage 1 1001 is the output of the XNOR gate 1012 .
  • T 8 XNOR T 5 AND T 4
  • T 3 AND T 4 T 8 XNOR
  • FIG. 11 shown is an example 8-stage register 1100 with the described logical feedback of the fourth embodiment of FIG. 7 of an alternative complement arrangement.
  • FIG. 11 shows another complement of the register of FIG. 8 .
  • the input 1120 for stage 1 1101 is the output of the XOR gate 1112 .
  • T 8 XOR T 5 NAND T 4
  • T 3 NAND T 4 T 8 XOR
  • the described method has an example suitable non-end pair of taps of 5 and 8:
  • the 12-stage register logical operations for the suitable pair of 8 and 5 are:
  • T 12 XOR (T 8 OR T 5 ) or logical equivalent T 12 XNOR (T 8 NOR T 5 )
  • T 12 XOR (T 7 OR T 4 ) or logical equivalent T 12 XNOR (T 7 NOR T 4 )
  • LFSRs can also be used in problems expressed using Boolean Satisfiability.
  • LFSR sequences are used to solve the Hamiltonian Cycle problem. Minimizing the number of clauses to express the LFSR simplifies solving of the problem.
  • FIGS. 12A, 12B and 12C show the registers 800 , 1000 , and 1100 of FIGS. 8, 10 and 11 , respectively, in more detail.
  • Each flip flop 1201 - 1208 has a clock input (CLK) 1211 , data input (D) 1212 , and outputs (Q) 1213 , inverted output (Q) 1214 .
  • FIG. 12A shows the register 800 with non-end taps 804 and 805 , end tap 808 , and the feedback logical operation provided by an OR gate 811 and an XOR gate 812 .
  • the register output 1215 is also shown.
  • Each flip flop 1221 - 1228 has a clock input (CLK) 1231 , data input (D) 1232 , and outputs (Q) 1233 , inverted output (Q) 1234 .
  • FIG. 12B shows the register 1000 with non-end taps 1004 and 1005 , end tap 1008 , and the feedback logical operation provided by an XNOR gate 1012 and an AND gate 1011 .
  • the register output 1235 is also shown.
  • Each flip flop 1241 - 1248 has a clock input (CLK) 1251 , data input (D) 1252 , and outputs (Q) 1253 , inverted output (Q) 1254 .
  • FIG. 12C shows the register 1100 with non-end taps 1104 and 1105 , end tap 1108 , and the feedback logical operation provided by an XOR gate 1112 and a NAND gate 1111 .
  • the register output 1255 is also shown.
  • the described non-linear feedback arrangement of two gates may be used by other n-stage registers that require more than two taps for maximal length sequences in LFSRs but may only give near-maximal length sequences. These may also be useful as the non-linear feedback arrangement of only two gates is a simplified feedback arrangement.
  • Length 8135 (compared to 8191):
  • Length 16570233 (compared to Ser. No. 16/777,215)
  • Length 66542149 (compared to 67/108,863)
  • a hybrid LFSR can generate a sequence of 2 n ⁇ 1 with two XORs.
  • this has the disadvantage of requiring access to both the middle of the shift register and the end to insert data.
  • the described NLFSR only requires access to the end to insert data (although data is read from taps in the middle of the register).
  • the described method provides a maximal length sequence or a near maximal length sequence with only one OR gate and one XOR gate.
  • the described method gives a useful increase in cycle length for a small gate count.
  • the prior art NLFSR of Dubrova includes the following where numbers between commas are taps which are XORed, and inside parentheses are ANDed.
  • Dubrova uses the shift register in the other direction and takes the first tap as tap 0, so this can be converted by replacing each number x by n-x.
  • the described method uses the simpler logical function of one OR and one XOR instead of 3 XORs and 1 AND.
  • Dubrova's taps cannot in general be simplified to those of the described method, except those of the form: n,a,b,(a,b)
  • the simplification is the key to the described method and the appropriate taps must be chosen for this to be possible.
  • a block diagram shows a computer system 1300 including a system for providing a non-linear NLFSR arrangements with maximal length sequences 1310 .
  • the computer system 1300 may include at least one processor 1301 , a hardware module, or a circuit for executing the functions of the described components which may be software units executing on the at least one processor. Multiple processors running parallel processing threads may be provided enabling parallel processing of some or all of the functions of the components.
  • Memory 1302 may be configured to provide computer instructions 1303 to the at least one processor 1301 to carry out the functionality of the components.
  • the system for providing a non-linear NLFSR arrangements 1310 may include a selecting component 1311 for selecting n, where n requires more than two taps in maximal length linear feedback shift registers.
  • the system 1310 includes a feedback arranging component 1312 for arranging a feedback logical operation of only one OR gate and only one XOR gate, taking logical OR of two suitable non-end taps and XOR with the end tap for feedback to the first stage or a complement logical operation.
  • a first complement logical operation is of only one NAND gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage.
  • a second complement logical operation is of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps and logical XNOR with the end tap for feedback to the first stage.
  • the system 1310 may include a testing component 1313 for obtaining one or more suitable pairs of non-end taps by testing different combinations of two non-end taps to determine pair combinations that provide maximal length sequences of the n-stage register.
  • the testing component 1313 may include a search program 1314 operating on three taps: the end tap, and two non-end taps, using every combination of the logic operation subject to the optimization restriction that 1 and 0 are equally likely.
  • the system 1310 may include a suitable tap pair output component 1315 for outputting suitable non-end tap pairs for use in the feedback arranging component 1312 .
  • the system 1310 may include a mirror component 1316 for taking one suitable pair of non-end taps and obtaining another suitable pair of non-end taps as the mirror of the taps in the n-stage register, wherein tap sequence [n, A, B] mirrors to [n, n ⁇ B, n ⁇ A].
  • FIG. 14 depicts a block diagram of components of the computer system 1300 of FIG. 13 , in accordance with an embodiment of the present invention. It should be appreciated that FIG. 14 provides only an illustration of one implementation and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.
  • Computer system 1300 can include one or more processors 1402 , one or more computer-readable RAMs 1404 , one or more computer-readable ROMs 1406 , one or more computer readable storage media 1408 , device drivers 1412 , read/write drive or interface 1414 , and network adapter or interface 1416 , all interconnected over a communications fabric 1418 .
  • Communications fabric 1418 can be implemented with any architecture designed for passing data and/or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripheral devices, and any other hardware components within the system.
  • One or more operating systems 1410 , and application programs 1411 are stored on one or more of the computer readable storage media 1408 for execution by one or more of the processors 1402 via one or more of the respective RAMs 1404 (which typically include cache memory).
  • each of the computer readable storage media 1408 can be a magnetic disk storage device of an internal hard drive, CD-ROM, DVD, memory stick, magnetic tape, magnetic disk, optical disk, a semiconductor storage device such as RAM, ROM, EPROM, flash memory, or any other computer readable storage media that can store a computer program and digital information, in accordance with embodiments of the invention.
  • Computer system 1300 can also include a R/W drive or interface 1414 to read from and write to one or more portable computer readable storage media 1426 .
  • Application programs 1411 on computer system 1300 can be stored on one or more of the portable computer readable storage media 1426 , read via the respective R/W drive or interface 1414 and loaded into the respective computer readable storage media 1408 .
  • Computer system 1300 can also include a network adapter or interface 1416 , such as a TCP/IP adapter card or wireless communication adapter.
  • Application programs 1411 on computer system 1300 can be downloaded to the computing device from an external computer or external storage device via a network (for example, the Internet, a local area network or other wide area networks or wireless networks) and network adapter or interface 1416 . From the network adapter or interface 1416 , the programs may be loaded into the computer readable storage media 1408 .
  • the network may comprise copper wires, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers and edge servers.
  • Computer system 1300 can also include a display screen 1420 , a keyboard or keypad 1422 , and a computer mouse or touchpad 1424 .
  • Device drivers 1412 interface to display screen 1420 for imaging, to keyboard or keypad 1422 , to computer mouse or touchpad 1424 , and/or to display screen 1420 for pressure sensing of alphanumeric character entry and user selections.
  • the device drivers 1412 , R/W drive or interface 1414 , and network adapter or interface 1416 can comprise hardware and software stored in computer readable storage media 1408 and/or ROM 1406 .
  • the present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration
  • the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention
  • the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
  • the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • a non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read-only memory
  • EPROM or Flash memory erasable programmable read-only memory
  • SRAM static random access memory
  • CD-ROM compact disc read-only memory
  • DVD digital versatile disk
  • memory stick a floppy disk
  • a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
  • a computer readable storage medium is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
  • Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
  • the network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
  • a network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
  • Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages.
  • the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
  • electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
  • These computer readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
  • These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
  • the computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
  • the functions noted in the blocks may occur out of the order noted in the Figures.
  • two blocks shown in succession may, in fact, be accomplished as one step, executed concurrently, substantially concurrently, in a partially or wholly temporally overlapping manner, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • a method for using a non-linear feedback shift register (NLFSR) with maximal or near-maximal length sequences for generating a pseudo-random sequence for n number of stages, wherein a maximal length is 2 n ⁇ 1, comprising: selecting n, where n requires more than two taps in maximal length linear feedback shift registers; and for the selected n stage register, using a feedback logical operation of only one OR gate and only one XOR gate in which the logical operation takes logical OR of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage, or an equivalent XNOR gate and NOR gate logical operation, or a complement logical operation.
  • NNLFSR non-linear feedback shift register
  • the method provides the advantage of a simple two-gate logical operation in a NLFSR that provides maximal or near-maximal length sequences for n-stage registers that usually require more than two taps.
  • the method minimizes the number of gates with no middle feedback to the register required whilst providing long pseudo-random sequences.
  • a complement logical operation may be of only one not-AND (NAND) gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage.
  • Another complement logical operation may be of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps and logical XNOR with the end tap for feedback to the first stage.
  • a maximal length sequence is obtained with two suitable non-end taps or a complement arrangement and for some other n, a best near-maximal length sequence is obtained with two suitable non-end taps or a complement arrangement.
  • a non-linear feedback shift register with maximal or near-maximal length sequences for generating a pseudo-random sequence for n number of stages, wherein a maximal length is 2 n ⁇ 1, comprising: an n-stage register, where n requires more than two taps in maximal length linear feedback shift registers; a feedback logical operation of only one OR gate and only one XOR gate, taking logical OR of two suitable non-end taps and XOR with the end tap for feedback to the first stage, or an equivalent XNOR gate and NOR gate logical operation, or a complement logical operation, wherein the suitable non-end taps provide maximal or near-maximal length sequences of the n-stage register.
  • a complement logical operation may be of only one NAND gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage.
  • Another complement logical operation may be of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps and logical XNOR with the end tap for feedback to the first stage.
  • a maximal length sequence is obtained with two suitable non-end taps or a complement arrangement
  • a best near-maximal length sequence is obtained with two suitable non-end taps or a complement arrangement
  • the NLFSR for 8-stage and 12-stage registers provides the maximal length sequences with the defined non-end taps.
  • a complement logical operation is of only one NAND gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps A, B, and logical XOR with the end tap for feedback to the first stage.
  • Another complement logical operation is of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps A, B, and logical XNOR with the end tap for feedback to the first stage.
  • a method for providing a non-linear feedback shift register (NLFSR) with maximal or near maximal length sequences for generating a pseudo-random sequence for n number of stages, wherein a maximal length is 2 n ⁇ 1, comprising: selecting n, where n requires more than two taps in maximal length linear feedback shift registers; for a selected n-stage register, using a feedback logical operation of only one OR gate and only one XOR gate, taking logical OR of two suitable non-end taps and XOR with the end tap for feedback to the first stage, or an equivalent XNOR gate and NOR gate logical operation, or a complement logical operation; and obtaining one or more suitable pairs of non-end taps by testing different combinations of two non-end taps to determine pair combinations that provide maximal or near-maximal length sequences of the n-stage register.
  • NNLFSR non-linear feedback shift register
  • the method may include obtaining one suitable pair of non-end taps and obtaining another suitable pair of non-end taps as the mirror of the taps in the n-stage register, wherein tap sequence [n, A, B] mirrors to [n, n ⁇ B, n ⁇ A].
  • Obtaining one or more suitable pairs of non-end taps may include using a search program operating on three taps: the end tap, and two non-end taps, using every combination of the logic operation, except all zeros, subject to the optimization restriction that 1 and 0 are equally likely.
  • the search program may initialize the register to a value other than all zeros, or all ones for a complement logical operation, and running the register at most 2 n-1 times until a register state is generated that is a repeat with the length of the sequence being the number of states from the first occasion a state was seen to a second occasion the state was seen.
  • the search program may: determine if the number of states seen so far is 2 n-1 or more; if it is, then the longest sequence found is the longest possible for that set of taps; if it is not, then a state not seen is chosen and the sequence generated again and the length measured; and these steps may be repeated until all the states are seen or the number of unseen states is less than the length of the longest sequence found.
  • a complement logical operation is of only one NAND gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage.
  • Another complement logical operation is of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps and logical XNOR with the end tap for feedback to the first stage.
  • a system for providing a non-linear feedback shift register (NLFSR) with maximal or near-maximal length sequences for generating a pseudo-random sequence for n number of stages, wherein a maximal length is 2 n ⁇ 1, comprising: a selecting component for selecting n, where n requires more than two taps in maximal length linear feedback shift registers; a feedback arranging component for arranging a feedback logical operation of only one OR gate and only one XOR gate, taking logical OR of two suitable non-end taps and XOR with the end tap for feedback to the first stage, or an equivalent XNOR gate and NOR gate logical operation, or a complement logical operation; and a testing component for obtaining one or more suitable pairs of non-end taps by testing different combinations of two non-end taps to determine pair combinations that provide maximal or near-maximal length sequences of the n-stage register.
  • NNLFSR non-linear feedback shift register
  • the system may include a mirror component for taking one suitable pair of non-end taps and obtaining another suitable pair of non-end taps as the mirror of the taps in the n-stage register, wherein tap sequence [n, A, B] mirrors to [n, n ⁇ B, n ⁇ A].
  • the testing component for obtaining one or more suitable pairs of non-end taps may include a search program operating on three taps: the end tap, and two non-end taps, using every combination of the logic operation, except all zeros, subject to the optimization restriction that 1 and 0 are equally likely.
  • the search program may be configured to initialize the variables representing the register to a value other than all zeros, or all ones for a complement logical operation, and running the register at most 2 n-1 times until a register state is generated that is a repeat with the length of the sequence being the number of states from the first occasion a state was seen to a second occasion the state was seen.
  • the search program may be configured to, for a near maximal length sequence: determine if the number of states seen so far is 2 n-1 or more; if it is, then the longest sequence found is the longest possible for that set of taps; if it is not, then a state not seen is chosen and the sequence generated again and the length measured; and repeat these steps until all the states are seen or the number of unseen states is less than the length of the longest sequence found.
  • a complement logical operation is of only one NAND gate and only one XOR gate in which the logical operation takes logical NAND of two suitable non-end taps and logical XOR with the end tap for feedback to the first stage.
  • Another complement logical operation is of only one AND gate and only one XNOR gate in which the logical operation takes logical AND of two suitable non-end taps and logical XNOR with the end tap for feedback to the first stage.
  • the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: select n, where n requires more than two taps in maximal length linear feedback shift registers; for a selected n-stage register, use a feedback logical operation of only one OR gate and only one XOR gate, taking logical OR of two suitable non-end taps and XOR with the end tap for feedback to the first stage, or an equivalent XNOR gate and NOR gate logical operation, or a complement logical operation; and obtain one or more suitable pairs of non-end taps by testing different combinations of two non-end taps to determine pair combinations that provide maximal or near-maximal length sequences of the n-stage

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US20210064343A1 (en) 2021-03-04
CN114270774B (zh) 2023-11-21
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